diff --git a/radeon-git-upstream-fixes2.patch b/radeon-git-upstream-fixes2.patch index ff76c92..53c24d9 100644 --- a/radeon-git-upstream-fixes2.patch +++ b/radeon-git-upstream-fixes2.patch @@ -1,1278 +1,3 @@ -commit c3532268875fd24e6519bea2fb1b814d612bbdb4 -Author: Dave Airlie -Date: Wed May 7 02:37:18 2008 +1000 - - radeon: fix zaphod EXA with texture video - -commit ffc437f3606ab8ceba1ff152e4bb08988a58b54c -Author: Dave Airlie -Date: Wed May 7 02:30:28 2008 +1000 - - avivo: fix zaphod cursor in theory - -commit e36ef14e3a1087e1fe41baa26ade2937f396001f -Author: Dave Airlie -Date: Wed May 7 01:39:28 2008 +1000 - - radeon: fix textured-xv on zaphod - -commit 8fc19bee27c0f151d2ab3354f6ac0992b358436d -Author: Dave Airlie -Date: Wed May 7 01:38:24 2008 +1000 - - radeon: zaphod: fix render accel for EXA - -commit fc41b9042a5220a8419cc7b69ca3850cae6b903c -Author: Dave Airlie -Date: Wed May 7 01:32:23 2008 +1000 - - radeon: fix EXA pixmap offset on zaphod - -commit 4568cb820d567c6909a4be956d7e79b91232535e -Author: Dave Airlie -Date: Wed May 7 01:19:39 2008 +1000 - - radeon: zaphod fixes for pciaccess not allowing multiple MMIO maps - -commit ca81fa086b21633a7fd926833fb6d1d4fa080646 -Author: Dave Airlie -Date: Wed May 7 01:12:01 2008 +1000 - - radeon: zaphod fix for cursor on second head - - We don't need to add fbOffset here as the mmap we have of the framebuffer - starts half way. - -commit 24b60c8965f6a0b3f0c2bb1e7236b4d6642c5918 -Author: Julien Cristau -Date: Fri May 2 15:30:45 2008 -0400 - - Add a test for __GLIBC__ to CD_Common_Types.h. - - Atombios redefines the standard types but the definitions conflict - with the ones from glibc (causes build failures on GNU/Hurd - and GNU/kFreeBSD). - -commit f051359ac09c6b9416e39b9ca7d9dc0880aa1557 -Author: thegraze -Date: Fri May 2 14:02:16 2008 -0400 - - ATOM: add support for DragonFlyBSD - -commit 3d469cbc3225d890a895dac7cbc1ab7e08054b48 -Author: Alex Deucher -Date: Wed Apr 30 18:33:04 2008 -0400 - - RADEON: lock the cursors when updating - - this should fix occasional corruption seen when updating - the cursor. - -commit 445b71021843665ba32f37b2ce5c9d2857c07cc7 -Author: Alex Deucher -Date: Tue Apr 29 21:01:41 2008 -0400 - - RADEON: assorted fixes - - - free rotate pixmaps on VT switch - - save crtc/output status so we only turn on - crtcs/outputs if they are off - - show/hide cursors when changing modes - -commit 070cce5255a5c311f9d8b85ec54bd56655014933 -Author: Stephan Wolf -Date: Mon Apr 28 11:26:37 2008 -0400 - - R3xx+: further fix for IGP chips - - see bug 15538 - -commit 211e0041c7fc2df494b77428553943a2b526ee4e -Author: Alex Deucher -Date: Sun Apr 27 21:08:00 2008 -0400 - - IGP: fix EXA composite corruption - -commit 656b06bdde129ca4fc370f5a2cf7311c9179b0ff -Author: Alex Deucher -Date: Sun Apr 27 20:20:49 2008 -0400 - - RADEON: remove duplicate register define - - Also add more bit defs to wait_until register - -commit 8a9820a3aa49bc667f90ac291a27e4d7b4ae38b3 -Author: Alex Deucher -Date: Sun Apr 27 19:02:22 2008 -0400 - - RADEON: decrease crtc/output verbosity - -commit c5d62fa0e8f52c3264ff9db3ff10cdf5a806bfc0 -Author: Owen Taylor -Date: Thu Apr 17 13:14:53 2008 +0200 - - Emulate repeats by drawing in tiles - - When we can't turn on hardware repeats, because the texture - is non-power-of-two, or has padding at the ends of lines, - try to draw the image in multiple tiles rather than falling - back to software. (We can only do this when there is no - transform.) - -commit eeb7b74bb6c813b0e3afa4b704f6ffb0d0aab92b -Author: Owen Taylor -Date: Thu Apr 17 13:14:25 2008 +0200 - - Turn on wrapping when repeating on R100 + R200 - - Actually enable repeats for R100 and R200. This corresponds - to a R300 change made in the patch in: - http://bugs.freedesktop.org/show_bug.cgi?id=15333 - -commit e511f39dfef503006cf249b9f6934091eaade9b5 -Author: Alex Deucher -Date: Thu Apr 17 05:04:34 2008 -0400 - - R300+: move more common code into init3d() - - - pre-load r3xx tex instructions - - setup RS instructions in init3d() - -commit 99435b7c18d931ea620044d0fdb4cc93dfcc6331 -Author: Owen Taylor -Date: Thu Apr 17 02:46:11 2008 -0400 - - Radeon: Omit mask coordinates - - Adapted from Owen's patch on bug 15546 - This fixes the slowness with aatext on r300 - and may speed up other chips marginally. - -commit 37614e1db9a595fbe8a21d7a045895e11d272db9 -Author: Alex Deucher -Date: Tue Apr 15 09:48:16 2008 -0400 - - fix up some things from the last commit - -commit 1286fe5ce1c77453d57817b9b26b1bdb32ca7bc8 -Author: Alex Deucher -Date: Mon Apr 14 20:02:14 2008 -0400 - - R300+: properly setup vap_cntl - - this fixes tcl/pvs on RV515 among other things - -commit f72a4b805db26f10f69330b88459cbeae661189b -Author: Alex Deucher -Date: Mon Apr 14 14:10:40 2008 -0400 - - EXA: Don't wait for 3D idle after each Composite() - - wait in CompositeDone() instead - -commit 4cd4acf1092aeb696b086a382a033aee471d2de9 -Author: Alex Deucher -Date: Mon Apr 14 11:50:59 2008 -0400 - - R300: move more common code to init3d() - -commit 3c523c9a07402e17dff588fad842224c57e98223 -Author: Alex Deucher -Date: Mon Apr 14 11:21:42 2008 -0400 - - R3xx+: 3D engine documentation and minor cleanups - - - document the R300 exa/textured video code - - minor cleanups of textured video code to clarify meaning - -commit ce025bbb2496d4de94b8d4ac450c64441b64ee04 -Author: Alex Deucher -Date: Sat Apr 12 21:22:03 2008 -0400 - - R300+: consolidate some tcl/non-tcl paths - - - Move more code to init3d() - - MMIO textured video seems more reliable now on newer chips - -commit 11b54a319c7c9dd52e3fb13372697059dafe1cd3 -Author: Alex Deucher -Date: Sat Apr 12 16:50:22 2008 -0400 - - R3xx+: fix XAA + textured video on non-TCL path - -commit dd15a2f5906725116b8cd9954243099055e88e37 -Author: Alex Deucher -Date: Sat Apr 12 16:49:03 2008 -0400 - - R3xx+: more fixes to 2D/3D engine init - -commit f3e68d4b7afd2e23675bf6361c496814c9cb4b94 -Author: Alex Deucher -Date: Fri Apr 11 10:59:07 2008 -0400 - - Fix exa glyph corruption on newer chips - -commit b59686d6427cbf8b35e36b020cbbc6a0c5149b22 -Author: Alex Deucher -Date: Fri Apr 11 10:15:25 2008 -0400 - - R300+: pre-load vertex programs in init3D() - -commit acc5833a35ad6c29a57f659607afb27eebdc2ea5 -Author: Alex Deucher -Date: Thu Apr 10 17:52:52 2008 -0400 - - R3xx+: consolidate more tcl code - -commit 6f8f75bd19ef1919c0291141675be2d0e29b3251 -Author: Alex Deucher -Date: Thu Apr 10 17:08:50 2008 -0400 - - R3xx+: consolidate some common 3D code - -commit 4b9234e1c4f7c7f419cb4245d64f3f9756c98bb6 -Author: Alex Deucher -Date: Thu Apr 10 16:58:22 2008 -0400 - - R3xx+: tcl wip - -commit 865c463e3afb4759758f569132be8bf1386da5cc -Author: Alex Deucher -Date: Thu Apr 10 16:51:04 2008 -0400 - - R300+: textured video tcl cleanup - -commit 79c8d4ca36a1c3e5fe759d4ccc379c36af8f1676 -Author: Alex Deucher -Date: Thu Apr 10 16:28:18 2008 -0400 - - RADEON: cleanup - -commit c4821a287d29a65f3bcb7d60dc72ec13c0384008 -Author: Alex Deucher -Date: Thu Apr 10 16:20:17 2008 -0400 - - Revert "R3xx/R5xx: move more VAP, etc. state setup into common init3d() function" - - This reverts commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02. - - Conflicts: - - src/radeon_commonfuncs.c - src/radeon_exa_render.c - src/radeon_textured_videofuncs.c - -commit 0032c80bf30bab189204e3e6929e18a19d753138 -Author: Alex Deucher -Date: Thu Apr 10 14:35:00 2008 -0400 - - RADEON: store tcl status in driver rec - -commit 9e2ffe66d106abe34a670d2edc9905ed62c485e8 -Author: Alex Deucher -Date: Thu Apr 10 14:24:04 2008 -0400 - - R3xx+: use the right register for engine flush - -commit e1a9f26c2d2cbca9ad159e723ec95b95be1ef349 -Author: Alex Deucher -Date: Thu Apr 10 14:12:15 2008 -0400 - - R3xx+: minor textured video fixes - - - set shader output swizzling correctly - - flush the right cache register on r3xx+ - -commit d79040906cd25bd494feb5901f465bbd050aa923 -Author: Alex Deucher -Date: Thu Apr 10 13:59:58 2008 -0400 - - R3xx+: EXA/textured video fixes - - - get pipe config based on GB_PIPE_SELECT where applicable - (adapted from a similar patch from Dave) - - only flush the dst cache after submitting vertices, freeing - the cache lines stalls the pipe - - no need to wait for 3D idle after submitting vertices - - fix PURGE_CACHE() and PURGE_ZCACHE() for r3xx+ - - fix depth 16 with EXA composite - -commit 0a96173cc38e506728d4c3f2dd383ba56e856578 -Author: Michel Dänzer -Date: Mon Apr 7 18:15:34 2008 +0200 - - Increase default CP timeout. - - Helps avoid spurious timeouts causing problems, see - http://bugs.freedesktop.org/show_bug.cgi?id=15203 . - -commit 255fbf465f5e7db2609a5a151bfa810249db52a0 -Author: Owen W. Taylor -Date: Thu Apr 3 02:25:41 2008 -0400 - - Fix rendering of transformed sources for REPEAT_NONE with EXA on >= R300. - - Use the border color when possible, otherwise fall back to software. - -commit bc0407e53237d7968808110bc0243076377acf6e -Author: Alex Deucher -Date: Fri Apr 4 18:40:16 2008 -0400 - - ATOMBIOS: Add support for DynamicClocks option - - This patch adds support for dynamic clock gating and static - power management using the atom command tables. In some cases - the bios may already set this up during post, so YMMV. - - I was only able to test on desktop cards, so I haven't tested - to see how much (if any) power this saves or how it affects the - thermal footprint. - -commit 5f5e21bb50555c56bd371576074c28c929307ff1 -Author: Alex Deucher -Date: Fri Apr 4 14:29:45 2008 -0400 - - RADEON: warning fixes - -commit c8e9a973aaded24aad567a0e36d0c78a05d6b2fd -Author: Alex Deucher -Date: Fri Apr 4 14:26:19 2008 -0400 - - RADEON: add some quirks - -commit 091963a635b79884afe77c026eabb48972fbe175 -Author: Alex Deucher -Date: Thu Apr 3 22:35:16 2008 -0400 - - Minor cleanup - -commit 950e9860643c20acde0eca4e4ff26baacc1f2b69 -Author: Alex Deucher -Date: Thu Apr 3 22:11:48 2008 -0400 - - Revert "RADEON: memmap rework 1" - - This reverts commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94. - - Conflicts: - - src/radeon.h - src/radeon_driver.c - - This rework seems to have caused more trouble than it was worth. - -commit 88a1fe4a94c5d11aff22734b21c89890e4428cd5 -Author: Alex Deucher -Date: Thu Apr 3 22:04:43 2008 -0400 - - Revert "RADEON: remove driver rec copies of mc info, use save rec directly" - - This reverts commit be0858a84fbdf74c0b844f462933a221d48c707d. - - Conflicts: - - src/radeon_driver.c - -commit c40a7aa3989576a8144213e2f31b892d21df8686 -Author: Owen W. Taylor -Date: Thu Apr 3 14:43:55 2008 -0400 - - R3xx/R5xx: Fix pitch and clamp mode for repeating textures - - - We can always use TXPITCH on a R300 even when repeating, - (previous check for pitch matching width was also wrong) - - Fix clamp mode for repeating textures to be WRAP - -commit a8593482c1f2e0f2dbac06c2e5325ba8c83ed9ff -Author: Dave Airlie -Date: Wed Apr 2 09:58:05 2008 +1000 - - atombios: fix the dual-head hopefully. - - tested on r600 with DVI and VGA - -commit 61d883d116fab3e9b513432d65e705afc5bb39f1 -Author: Dave Airlie -Date: Wed Apr 2 09:57:38 2008 +1000 - - Revert "Revert "atombios: fixup the width/height to use the mode values not the scrn ones"" - - This reverts commit fc9af578997b6f22ee8b17e83f37d98689291b0e. - - I see your revert and raise you one... - -commit fc9af578997b6f22ee8b17e83f37d98689291b0e -Author: Alex Deucher -Date: Tue Apr 1 09:25:45 2008 -0400 - - Revert "atombios: fixup the width/height to use the mode values not the scrn ones" - - This reverts commit c2b1c8b706a6c7c1fd0af80091958473133d54e7. - - These registers hold surface size. Using the mode values - breaks dualhead. - -commit 959509dd54de053f526b534e379a46934127231f -Author: Dave Airlie -Date: Mon Mar 31 14:29:44 2008 +1000 - - radeon: use correct DDC interfaces so quirks get applied - - Radeon seemed to mess up applying certain quirks, hopefully this will fix it. - -commit 18f5f1cd2f52afed89fc11ade0920f3dfea87306 -Author: Dave Airlie -Date: Mon Mar 31 14:11:49 2008 +1000 - - radeon: split quirks into separate function and new quirk for IBM RN50 - - Add a connector table quirk for the IBM RN50. - -commit c2b1c8b706a6c7c1fd0af80091958473133d54e7 -Author: Dave Airlie -Date: Sun Mar 30 11:44:14 2008 +1000 - - atombios: fixup the width/height to use the mode values not the scrn ones - - this fixes it properly, legacy appears to be okay. - -commit c5edea3d8c9254d3a21e390b8309e39e4c9635db -Author: Dave Airlie -Date: Sun Mar 30 11:11:22 2008 +1000 - - r500/r600: fix rotation to fill screen - - I'm not 100% sure this is the correct fix (maybe we shouldn't be using scrn - virtualX/Y)... this will fix it for now until I get more time. - -commit 9c62c820ba45ebc14d5f36f5d7885863800b6adb -Author: Michel Dänzer -Date: Fri Mar 28 12:37:29 2008 +0100 - - Include config.h, so FGL_LINUX can actually be defined when it's tested... - -commit a00d9260a85b94a522c442aee24bc5ea4dc31c5c -Author: Alex Deucher -Date: Thu Mar 27 20:03:13 2008 -0400 - - RADEON: fix lid issues on AVIVO chips for real this time :) - -commit f0e89c09074b2c7e641f73692bb39b0bf68eb49c -Author: Alex Deucher -Date: Thu Mar 27 19:15:18 2008 -0400 - - Revert "RADEON: attempt to fix lid issues" - - This reverts commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4. - This doesn't help. - -commit 1442d396b938049b83f009a78ddabe2bf85641b6 -Author: Dave Airlie -Date: Thu Mar 27 14:02:51 2008 +1000 - - radeon: size bios to max of bar vs 64k. - - reported by dwmw2: rhbz 438299 - -commit de2f609ff0004ef8b74727bfebc2c74fb91205ea -Author: Alex Deucher -Date: Wed Mar 26 18:35:21 2008 -0400 - - AVIVO: no need to call PreinitXv() on AVIVO chips as they have no overlay - -commit 75884c257bc2bcfa5b498a77d4c403f09face036 -Author: Alex Deucher -Date: Wed Mar 26 18:16:47 2008 -0400 - - XAA: update message about render so as to not confuse users - -commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4 -Author: Alex Deucher -Date: Wed Mar 26 18:01:29 2008 -0400 - - RADEON: attempt to fix lid issues - - On some laptops the bios attempts to re-program the chip - when a lid event comes in. This should hopefully prevent - the bios from doing that. - -commit 8b144830fe9b4a0cee4745023de5e7d387070f60 -Author: Alex Deucher -Date: Tue Mar 25 01:15:05 2008 -0400 - - RV250: disable textured video due to HW bug - - The YUV->RGB conversion in the texture engine is broken - on RV250 so the colors come out wrong. - -commit 1789f11ab91633d3928f8b71988d51ff44bda9d1 -Author: Alex Deucher -Date: Mon Mar 24 19:03:30 2008 -0400 - - R3xx/R5xx: flush PVS state before enabling pvs-bypass - -commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02 -Author: Alex Deucher -Date: Mon Mar 24 14:25:03 2008 -0400 - - R3xx/R5xx: move more VAP, etc. state setup into common init3d() function - - Also some minor code cleanups - -commit 399b1d405e602c62d6deebea6d7e1f38886cd8e2 -Author: Alex Deucher -Date: Mon Mar 24 13:04:57 2008 -0400 - - R3xx/R5xx: use non VAP/TCP for textured video - - Just extra state to emit. - -commit cd77ec18f32a7b36acb655c927bbfd7044019f97 -Author: Dave Airlie -Date: Mon Mar 24 18:42:21 2008 +1000 - - r300: don't bother with VAP/TCL for render. - - We just send more data to the card to process per transaction, without getting - any actual gains, as we already pre-compute the vertices without needing - any clipping or transforms from the card. - - Perhaps some stuff could be done on-card, but so far the code is a lot - faster if we avoid sending this extra info. - - pre: 150000 glyphs/sec - post: 185000 glyphs/sec - -commit 301c6739b88676a0c78fc72194e993f894b8dc28 -Author: Alex Deucher -Date: Sun Mar 23 11:14:02 2008 -0400 - - RS4xx: Revert back to previous fifo settings for now - - Setup of these registers needs more investigation. - -commit 9bea60b3eb378de5e1d44cc02a2763f4feae7882 -Author: Alex Deucher -Date: Sat Mar 22 11:46:15 2008 -0400 - - RS4xx: more work on disp/disp2 fifo setup - -commit 90f11c3986c28daa7b600b9662da145af325d264 -Author: Alex Deucher -Date: Sat Mar 22 11:29:51 2008 -0400 - - RS4xx: missed this on the last commit. - -commit 6d5066a451017a2683addc9e2496987626795dda -Author: Alex Deucher -Date: Fri Mar 21 16:21:54 2008 -0400 - - RS4xx: attempt to set up disp/disp2 fifos correctly - - If you have an XPRESS chip, please test!!! - -commit fb1cffac05ae20c8365b25a2042b0ae961880faf -Author: Alex Deucher -Date: Fri Mar 21 15:24:36 2008 -0400 - - RS4xx: attempt to fix TMDS/DVO support - - XPRESS chips added a second set of FP control registers. - I don't have the hw to test however. - -commit 5e3b21284482df9974c9a58f248f0100def2bb0c -Author: Alex Deucher -Date: Wed Mar 19 19:15:05 2008 -0400 - - Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST - - See bug 11796 - -commit 17cd42ed31814ba329a6a68edd0d75390a7da40e -Author: Matt Turner -Date: Wed Mar 19 18:17:10 2008 -0400 - - Enable BSR in Log2 functions - - This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead - of looping through bits. It should provide a somewhat of a speed increase in - this function on x86 and AMD64 architectures. - - Note: the BSR instruction was added with the 80386 CPU and is therefore not - compatible with earlier CPUs, though I highly doubt it's even possible to use a - 286 in conjunction with a Radeon. - - The inline assembly also works with Intel's compiler (icc). - -commit c83827b4d2b6f03c54429e757a756eb99ff8be6b -Author: Paulo Cesar Pereira de Andrade -Date: Wed Mar 19 17:58:34 2008 -0400 - - [PATCH] Compile warning fixes. - - Minor changes to avoid declarations mixed with code. - Ansified functions with empty prototype to specify they don't - receive arguments. - Added some prototypes to radeon.h, and major reorder on radeon.h - adding prototypes in alphabetical order and specifying to file that - defines it. - -commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb -Merge: 55e446b... f71ac0e... -Author: Alex Deucher -Date: Wed Mar 19 16:06:41 2008 -0400 - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render - -commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246 -Author: Alex Deucher -Date: Wed Mar 19 13:15:32 2008 -0400 - - R3xx/R5xx: Make sure to clamp the output of the FS - -commit b6aa4279cbe68cc8e4523795e9714fb798b62d98 -Author: Alex Deucher -Date: Wed Mar 19 12:45:01 2008 -0400 - - R5xx: bump textured video limits to 4096 - -commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1 -Author: Alex Deucher -Date: Wed Mar 19 12:31:51 2008 -0400 - - RADEON: add new macros to distinguish between R3xx and R5xx 3D - -commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0 -Author: Alex Deucher -Date: Wed Mar 19 12:07:33 2008 -0400 - - RADEON: fixed textured video with XAA and tiling - -commit f5951db7b3522e0fe6af7f46a170c9c9a60a9bff -Author: Alex Deucher -Date: Wed Mar 19 12:01:50 2008 -0400 - - RV515: fix textured video and EXA Composite - - There seems to be an issue with the PVS setup on RV515, but - bypassing it seems to work fine. - -commit 13573879fe56368ad06234712b677c23fabc56c6 -Author: Dave Airlie -Date: Wed Mar 19 15:06:47 2008 +1000 - - r500: make it work from startup. - - I'm not sure why this worked or what is going wrong here, really the - VAP internal architecture escapes me :) - -commit d331dd64d644a18ec99a2136cd0943b5edca1f03 -Author: Alex Deucher -Date: Tue Mar 18 19:44:26 2008 -0400 - - R3xx/R5xx: remove extra return after last commit - -commit bc34df7a9c35cdd38c49d5c22471f3f487a33d6e -Author: Alex Deucher -Date: Tue Mar 18 19:39:47 2008 -0400 - - R3xx/R5xx: switch an ErrorF() to RADEONFALLBACK() - -commit 6f03f8fe0ecf4181dcf125049cf63bece0451fb2 -Author: Alex Deucher -Date: Tue Mar 18 19:36:05 2008 -0400 - - R3xx: we only use 2 temps, not 3 - -commit 8bb71ab4a3eb4fb6ef7f709e87c8df387cb70ee3 -Author: Tilman Sauerbeck -Date: Tue Mar 18 14:36:08 2008 -0400 - - R3xx/R5xx: fix up a8-src-something_with_colors - -commit c362591d9b496df30668543158e4de44de742dc3 -Author: Alex Deucher -Date: Tue Mar 18 11:15:17 2008 -0400 - - R3xx/R5xx: remove some cruft - -commit 89fe6d2c7d7471e6088558130f6e49f46c31dd47 -Author: Dave Airlie -Date: Tue Mar 18 09:43:43 2008 -0400 - - R5xx: fix typ in r5xx render accel - - This gets render working on r5xx - -commit 79b40ebcd8dedfc83e484c1024beeeaccc6124f3 -Author: Alex Deucher -Date: Tue Mar 18 02:46:49 2008 -0400 - - R5xx: first pass at render support (untested) - -commit 71292c8f193230255d1d980c2e996bb01d04fab6 -Author: Alex Deucher -Date: Tue Mar 18 00:45:37 2008 -0400 - - R5xx: bump tex/dst limits to 4096 - -commit 30b52f8aa6a471455284f59b5b27252743892b13 -Author: Alex Deucher -Date: Mon Mar 17 23:20:10 2008 -0400 - - R3xx/R5xx: whitespace cleanup and cruft removal - -commit 9c9f1b538ed710c3066775fba0a8e936b63087b1 -Author: Alex Deucher -Date: Mon Mar 17 23:01:37 2008 -0400 - - R3xx: get masks working and cleanup - - RS offset was wrong for mask texture - -commit ef94febd74f8ee63081b61e42f093a5a2b8fbf1e -Author: Alex Deucher -Date: Mon Mar 17 22:27:19 2008 -0400 - - R3xx: minor adjustments - -commit f71ac0e40b9d950bcb3bba42a75d41f45b6ed1bf -Author: Alban Browaeys -Date: Mon Mar 17 20:48:48 2008 -0400 - - RADEON: Revert to old behavior when resetting the memmap on VT switch - - Not sure why this needs to be done twice. Should fix bug 14980 - Probably needs more investigation. - -commit bedbbf196dc97ee5142e7dfae16fb6f317fca5a7 -Author: Alex Deucher -Date: Mon Mar 17 20:16:25 2008 -0400 - - R3xx: some progress - -commit af0e626c132de2dd9958fec657fcc85d4c0fe5e1 -Author: Alex Deucher -Date: Mon Mar 17 18:07:12 2008 -0400 - - R3xx: fix errant w - -commit 29ea5bfc0eb3194e2454fc3ee863df54f0300880 -Author: Alex Deucher -Date: Mon Mar 17 16:41:57 2008 -0400 - - RADEON: fix typo in RADEONAdjustMemMapRegisters() - -commit ab317e85c5ab1a249a510c34aeb3a908be1a66fc -Author: Alex Deucher -Date: Mon Mar 17 15:28:09 2008 -0400 - - RADEON: make sure var is initialized properly in RADEONAdjustMemMapRegisters() - -commit 208d307227e15f37a6af5194398ed23266ff743a -Author: Dave Airlie -Date: Sun Mar 16 19:39:23 2008 +1000 - - radeon: the 0x5974 appears to be a mobility chip... - - After debugging with partymola on #radeon, adding this allowed his - Dell Vostro 1000 to work properly - -commit 9bc7c2ec4048e1677547c1d60c51ccb954f7589a -Author: Alex Deucher -Date: Fri Mar 14 20:12:22 2008 -0400 - - R3xx: odds and ends... - - still not working. - - swizzle US output for BGR formats - - no need to write to temps in ALU ops, - write to output only - - flush the PVS before updating - -commit 96bea7906c4706fcd57a9cd8f1ce3feab6ac676d -Author: Alex Deucher -Date: Fri Mar 14 15:59:36 2008 -0400 - - R3xx: theoretical support for component alpha - - masks are still broken so... - -commit cffe3dcc8991cd7c457a9c1a9f41055aa9ea3436 -Author: Alex Deucher -Date: Fri Mar 14 14:37:43 2008 -0400 - - R3xx: VS WIP - -commit b73f52a50dfd6ff8d92f04d6b510c39582c6ac67 -Author: Alex Deucher -Date: Fri Mar 14 14:20:49 2008 -0400 - - R3xx/R5xx: enable VS for mask texture - -commit 569a14ca9be1e18fe9921edc816ac3dc32d6cca7 -Author: Alex Deucher -Date: Fri Mar 14 13:32:12 2008 -0400 - - R3xx/R5xx: Fix magic numbers in vertex shaders - -commit 4878997529601d62e257aa1c9112bd460561de73 -Author: Alex Deucher -Date: Thu Mar 13 21:23:40 2008 -0400 - - R3xx: make sure to set the FS code size correctly - -commit 22f46b88ef05afb6a6b6d70007ac4980a446430e -Author: Alex Deucher -Date: Thu Mar 13 20:25:33 2008 -0400 - - R3xx: attempt to setup the rasterizer properly for mask texture - - Not working yet - -commit 081fc9e892fa3d2e07b7db65b2e2719646255463 -Author: Alex Deucher -Date: Thu Mar 13 18:38:26 2008 -0400 - - R3xx: more mask work - -commit 2bf0236c03538ace3ce6d0e68f0829fc47d1385b -Author: Alex Deucher -Date: Thu Mar 13 18:32:00 2008 -0400 - - R3xx: enable composite for non-mask cases - -commit 74286ba41302107d2fc626fee2181f7c4bc18164 -Author: Alex Deucher -Date: Thu Mar 13 18:25:32 2008 -0400 - - R3xx: add basic mask support - -commit a2bbe10d866567911b68f222b4758624bfe9bf84 -Author: Alex Deucher -Date: Thu Mar 13 18:16:53 2008 -0400 - - R300: setup source selects and output swizzling - -commit b9974ecce7d1932595226004858b08a7a6b188dc -Author: Alex Deucher -Date: Thu Mar 13 17:35:38 2008 -0400 - - R3xx: set the texture id and add some register info - -commit 0ef700b7da5e554a0d0d166f3fde85ff45c9eb1f -Author: Alex Deucher -Date: Thu Mar 13 17:02:25 2008 -0400 - - R3xx/R5xx: enable blending - -commit b35c09a597c93a1d9f06ef0091c96822b0653f98 -Author: Dave Airlie -Date: Thu Mar 13 18:42:29 2008 +1000 - - xv: fixup XAA on r500 textured video - - the XAA area should never end up tiled. This may break with nooffscreen pixmaps - -commit d4446461c3630caff166456c351ace34f57cc119 -Author: Matt Turner -Date: Tue Mar 11 21:20:53 2008 -0400 - - Properly fix uninitialized variables warnings - - According to commit 9fd13e6773371c82b9799a5bda7c96ffa5cafe8c to - xf86-video-intel by Kristian Høgsberg, there is a better way to fix the - possibly initialized variables warnings. This patch will use Kristian's fix. - -commit 20adfd7390d9b1f100e0c4a14f175377b8335c82 -Author: Alex Deucher -Date: Tue Mar 11 20:09:35 2008 -0400 - - RADEON: enable output attributes that require a modeset immediately - - This should fix bug 14915 - -commit 53ba7f5771b0b53fb0d3bc29d64bdd3813756d10 -Author: Alex Deucher -Date: Tue Mar 11 19:12:40 2008 -0400 - - RADEON: fix vblank interrupts after VT switch or suspend/resume - -commit e946c097f0438afbea6f3dd37ee39d67d415708c -Author: Matt Turner -Date: Tue Mar 11 19:07:58 2008 -0400 - - [PATCH] Fix a few warnings - -commit 8e160508520c0a24ca90aad182f296461ca0d9b6 -Author: Alex Deucher -Date: Tue Mar 11 18:11:13 2008 -0400 - - DCE3: add support for PCIEPHY (untested) - -commit fbded88a2925f9f049936dad0736721e7b84a6ee -Author: Alex Deucher -Date: Tue Mar 11 14:10:31 2008 -0400 - - ATOM: remove some cruft - -commit 3263f6e4a410281d620c288a92bb4521f7b6fc06 -Author: Alex Deucher -Date: Tue Mar 11 14:05:48 2008 -0400 - - DCE3: enable DPMS on DIG ports - -commit eb90e235b58c94f3d4d75394725ab2fe246a42ff -Author: Alex Deucher -Date: Tue Mar 11 13:53:54 2008 -0400 - - DCE3: adjust PLL for DCE3 chips - - this fixes stability issues on digital outputs and certain modes. - -commit 552615ccc5360baafb8bb41698c1ca27816fd4b2 -Author: Alex Deucher -Date: Tue Mar 11 13:38:29 2008 -0400 - - ATOMBIOS: enable load detection by default on both DACs - - Load detection is reliable with atom, so enable it by default - on both DACA and DACB, rather than just DACA. - -commit 78b10487cf222c96f8944ba25e2ea970506b3535 -Author: Alex Deucher -Date: Tue Mar 11 13:16:00 2008 -0400 - - DCE3: add output attribute to enable/disable coherent mode - - Enabled by default. The TMDS transmitter can be programmed - slightly differently depending on the chips in the panel. If you - have problems with tmds on a particular panel, try disabling it. - -commit d20be31c46fbec623af4c3628a7c603ceacf500f -Author: Alex Deucher -Date: Mon Mar 10 21:05:43 2008 -0400 - - RV550: MC setup is like RV515 not RV530 - -commit 38606b08b68842fbcc81c233009c1117269f3be9 -Author: Matthieu Herrb -Date: Sat Mar 8 23:22:59 2008 +0100 - - Makefile.am: nuke RCS Id - -commit 9d710ee1a44cf2f3a948fbdbe17ef09521cbe744 -Author: Alex Deucher -Date: Fri Mar 7 15:09:14 2008 -0500 - - AVIVO: clean up some unused variables - -commit c28c30c9f3d7bfebfd56a5c982c96f0090982054 -Author: Alex Deucher -Date: Fri Mar 7 14:10:49 2008 -0500 - - RADEON: Fix crash in last commit - -commit c3a3635865e380c784a226c8ead069d4716d6b75 -Author: Dave Airlie -Date: Thu Mar 6 20:17:45 2008 -0500 - - RADEON: fix tiling/interlaced interaction with randr 1.2 - -commit df1b94dc4eb1f35b636dbf2ec0ab1c2da9937c0d -Author: Alex Deucher -Date: Thu Mar 6 19:22:08 2008 -0500 - - DCE3: Ignore outputs with DIN connectors for now - -commit cb2dc19387c7b6494c47c76d683cf38a48700768 -Author: Alex Deucher -Date: Thu Mar 6 18:33:12 2008 -0500 - - AVIVO: fix typo from a previous commit - - Leave tv dpms hook disabled or you may get bad interactions - with the shared DAC - -commit 77355de48057e5e7e0d5b3f3cf5a7a92220a53b1 -Author: Alex Deucher -Date: Thu Mar 6 17:46:00 2008 -0500 - - AVIVO: don't add outputs for invalid connectors - -commit 600dbe080997a01ceaf6be86723189d518bc1281 -Merge: 594743a... 5b7875d... -Author: Alex Deucher -Date: Thu Mar 6 17:31:37 2008 -0500 - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit 594743a99811a8b0f391412892414fcd158eeb56 -Author: Alex Deucher -Date: Thu Mar 6 17:30:21 2008 -0500 - - AVIVO: fix up memsize detection for IGP chips - -commit 5b7875d0cbfbdbcd1515c4e942d30de298b49dff -Author: Doug Chapman -Date: Thu Mar 6 14:31:06 2008 -0500 - - Bug #14826: Fix a bogus check around xf86SetOperatingState. - -commit 651fe23f4c650ed91843dec48db24e18e8b91219 -Merge: 3de2dc8... 766f464... -Author: Adam Jackson -Date: Thu Mar 6 14:28:27 2008 -0500 - - Merge branch 'master' of git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit 41171c25cd235bafad26bcbabced16ead4b8c54b -Author: Alex Deucher -Date: Thu Mar 6 14:05:18 2008 -0500 - - DCE3.0: add support for crtc memreq table - -commit 766f464dfdfccadef23e4232f2bce5db22195513 -Author: Alex Deucher -Date: Thu Mar 6 13:35:43 2008 -0500 - - RADEON: take 2 on proper pragma pack support for bsds - - See bug 14594. Based on suggestion by Henry Zhao - -commit a842ce9ca6494e724a7828cead9b61c9ef02b6aa -Author: Alex Deucher -Date: Thu Mar 6 12:32:18 2008 -0500 - - DCE3.0: Minor fixups - -commit 8a1ba374033591c725a78923aa30829e4de2a5ae -Author: Alex Deucher -Date: Thu Mar 6 09:53:51 2008 -0500 - - RADEON: option to override TVDAC adj values from bios with driver defaults - - If you have a washed out image on the tv dac, try this option. - Option "DefaultTVDACAdj" "TRUE" - -commit 0ed48f8f651a28e189f9fee8c6b593da0178d21c -Author: Alex Deucher -Date: Wed Mar 5 18:41:01 2008 -0500 - - AVIVO: Initial support for DCE 3.0 using atombios - - DACs are working well, DIG support (DVI, HDMI, LVDS, etc.) - still has some issues. - -commit 2901e99f1942842856cd39c1dcc8b22f3cf7d9e3 -Author: Alex Deucher -Date: Wed Mar 5 10:40:06 2008 -0500 - - RADEON: fix fetching of dac2 adj values from newer bios tables - -commit 74eb981287d76836327830bd51272f605a07e0cc -Author: Alex Deucher -Date: Mon Mar 3 12:02:44 2008 -0500 - - ATOMBIOS: fix atombios parser support on *bsd - - bsd requires a different pragma pack than Linux. - See bug 14594. - -commit f7769ea86e265f347eb58c517ccb5ef8b35eec27 -Author: Paulo Cesar Pereira de Andrade -Date: Sun Mar 2 14:49:21 2008 -0500 - - [PATCH] Ensure symbols used by other modules are visible. - - The xf86-video-ati drivers are one of the cases where LoaderSymbol is - widely used in some obscure ways. This patch fixes the problem, and - allows compiling with -fvisibility=hidden. - -commit a4398ac3ad77216f2c8aa628425bef5f2912a0a9 -Author: Alex Deucher -Date: Sat Mar 1 18:52:26 2008 -0500 - - RS6xx: change isIGP checks to CHIP_FAMILY_RS690 - - these paths are only relevant on RS6xx chips - -commit 67d4d04836c05293b844bc505f303cfb04c0f8a4 -Author: Alex Deucher -Date: Sat Mar 1 18:33:18 2008 -0500 - - RADEON: use xf86SetDesiredModes() in screeninit and enterVT - - this should restore the proper output state on VT switches - -commit be0858a84fbdf74c0b844f462933a221d48c707d -Author: Maciej Cencora -Date: Sat Mar 1 18:11:58 2008 -0500 - - RADEON: remove driver rec copies of mc info, use save rec directly - - info->mc_* were used and the immediately copied into info->ModeReg - ones. Just use the ModeReg copies directly. - -commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94 -Author: Alex Deucher -Date: Sat Mar 1 16:23:51 2008 -0500 - - RADEON: memmap rework 1 - - Don't restore memmap regs on every mode switch. - Just do memmap save/restore/setup on server start and VT switch. - -commit 1f6a23000001f3d1c21b5c04f94714a8caa7aa8b -Author: Alex Deucher -Date: Sat Mar 1 15:53:42 2008 -0500 - - RADEON: only restore legacy dac regs on legacy radeons - -commit dee6cef8e62d0651c00319e03eea92940fd24aa4 -Author: Alex Deucher -Date: Sat Mar 1 14:39:32 2008 -0500 - - RS4xx: enable exa render accel and textured video - - RS6xx paths seem to work fine on RS4xx - -commit 129f737efe4e8d1a368e7db4b063bdcd9339cb09 -Author: Alex Deucher -Date: Sat Mar 1 14:32:30 2008 -0500 - - AVIVO: save/restore regs by block - - Save/Restore the entire block for each output. - This should fix VT switch problems. - -commit b069aadaa63a95d7a71b5cfbab83577b49501094 -Author: Alex Deucher -Date: Fri Feb 29 22:36:02 2008 -0500 - - AVIVO: LVDS panels need dithering enabled - - Fixes bug 14760 - -commit fe87bdee815372b4b4d7d4c705e34681625b90f2 -Author: Alex Deucher -Date: Fri Feb 29 13:10:13 2008 -0500 - - AVIVO: disable pageflipping on avivo chips until we have proper drm support - -commit fb3678c7f511d539a51cd090cb8b5041d7d2ba26 -Author: Alex Deucher -Date: Fri Feb 29 13:01:21 2008 -0500 - - R5xx: fix register count when sending fragment program for textured video - -commit a66d37d1a896ec934989592457c2beff8e6f1639 -Author: Alex Deucher -Date: Fri Feb 29 04:07:05 2008 -0500 - - fix off-by-one in last commit - -commit e56062960be0c8d3947861dd5e0691fce6516b99 -Author: Alex Deucher -Date: Thu Feb 28 19:16:39 2008 -0500 - - AVIVO: save/restore scaler regs - -commit ae1c39a9b3e666404d0931679c9078c2e125a8bc -Author: Alex Deucher -Date: Thu Feb 28 18:53:55 2008 -0500 - - RS6xx: rework output parsing - - Turns out it's not as complex as I originially thought. - IGP chips just have non-standard GPIO entires for DDC. - -commit d8d6c9fe4ae7e1ab67dd041a251e901d97c29ed6 -Author: Alex Deucher -Date: Thu Feb 28 17:01:14 2008 -0500 - - RS6xx: fix typos in previous commit - - Noted by Maciej Cencora on IRC - -commit 46547ae8bdbc5c10f1fd028b95ec4c5c31a5b318 -Author: Alex Deucher -Date: Thu Feb 28 14:29:30 2008 -0500 - - AVIVO: disable dithering on DFPs - - This should fix the color banding some people have noticed. - Also save/restore DDIA regs on RS6xx - -commit 72a53d6f20ac29b3baddb7d8af04f19b76d2e04f -Author: Michel Dänzer -Date: Thu Feb 28 17:38:04 2008 +0100 - - Handle EXA coordinate limits more cleverly. - - Generally set the 2D engine limits, and only enforce the 3D engine limits in the - CheckComposite hook. This should still prevent useless migration of pixmaps the - 3D engine can't handle but allows for basic acceleration of bigger ones. - - Fixes http://bugs.freedesktop.org/show_bug.cgi?id=14708 . - -commit 5249f450a2487475a95531603cc8668db2c21c33 -Author: Michel Dänzer -Date: Thu Feb 28 12:23:58 2008 +0100 - - Fix 16 bit packed YUV XVideo playback on big endian systems with DRI disabled. - - http://bugs.freedesktop.org/show_bug.cgi?id=14668 - -commit e40d75fd8b2aece9dae8076fac822a4a83025fb2 -Author: Alex Deucher -Date: Wed Feb 27 22:53:10 2008 -0500 - - R500: fragment program clean up and magic number conversion - -commit 140dadba36b2191f0e18e41dd987785abd5f55d2 -Author: Alex Deucher -Date: Wed Feb 27 22:21:12 2008 -0500 - - R300: fix up magic numbers in fragment program - -commit e521476bb5e2dfabc93747e43eb911a8a101357e -Author: Alex Deucher -Date: Wed Feb 27 21:26:55 2008 -0500 - - R300/R400: bump up the clip limits for textured video - - This allows up to 2560x2560 (hw limit) - -commit 10db46f11d7e1c055c9ad6034c65ad163dad17dc -Author: Alex Deucher -Date: Wed Feb 27 15:28:50 2008 -0500 - - AVIVO: make sure we select the right LUT for each crtc - -commit ea944f38dcfd871b27345698afea1cb986ecb049 -Author: Alex Deucher -Date: Wed Feb 27 14:37:52 2008 -0500 - - R300+: update RADEONCP_REFRESH() to reflect new location of scissor regs - -commit b865faf95666e2172c3eec143f77fe9c524e4983 -Author: Alex Deucher -Date: Wed Feb 27 14:05:44 2008 -0500 - - R100/R200: move r100/r200 specific 3D setup into appropriate blocks - - R3xx+ doesn't have these regs. - -commit 3de2dc88cf26ff5932f11cecdf975777b8aa2a4a -Author: Adam Jackson -Date: Wed Jan 16 14:55:05 2008 -0500 - - Bump CRTC size limits on AVIVO chips so 30" displays work without tweaking. - - Note that the CRTC size limits we're using right now are _not_ the - hardware limits, they're just heuristics until we can resize the front - buffer properly. diff --git a/configure.ac b/configure.ac index 2412d4f..ab8bd97 100644 --- a/configure.ac @@ -1358,6 +83,942 @@ index 44a0b35..c60b652 100644 typedef unsigned int uint32_t; typedef int int32_t; #else +diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h +index e6d41fe..4b106cf 100644 +--- a/src/AtomBios/includes/ObjectID.h ++++ b/src/AtomBios/includes/ObjectID.h +@@ -18,467 +18,467 @@ + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. +-*/ +-/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ +- +-#ifndef _OBJECTID_H +-#define _OBJECTID_H +- +-#if defined(_X86_) +-#pragma pack(1) +-#endif +- +-/****************************************************/ +-/* Graphics Object Type Definition */ +-/****************************************************/ +-#define GRAPH_OBJECT_TYPE_NONE 0x0 +-#define GRAPH_OBJECT_TYPE_GPU 0x1 +-#define GRAPH_OBJECT_TYPE_ENCODER 0x2 +-#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 +-#define GRAPH_OBJECT_TYPE_ROUTER 0x4 +-/* deleted */ +- +-/****************************************************/ +-/* Encoder Object ID Definition */ +-/****************************************************/ +-#define ENCODER_OBJECT_ID_NONE 0x00 +- +-/* Radeon Class Display Hardware */ +-#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 +-#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 +-#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 +-#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 +-#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ +-#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 +-#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 +- +-/* External Third Party Encoders */ +-#define ENCODER_OBJECT_ID_SI170B 0x08 +-#define ENCODER_OBJECT_ID_CH7303 0x09 +-#define ENCODER_OBJECT_ID_CH7301 0x0A +-#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ +-#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C +-#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D +-#define ENCODER_OBJECT_ID_TITFP513 0x0E +-#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ +-#define ENCODER_OBJECT_ID_VT1623 0x10 +-#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 +-#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 +-/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ +-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 +-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 +-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 +-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ +-#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ +-#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ +-#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 +-#define ENCODER_OBJECT_ID_VT1625 0x1A +-#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B +-#define ENCODER_OBJECT_ID_DP_AN9801 0x1C +-#define ENCODER_OBJECT_ID_DP_DP501 0x1D +-#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E +-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F +- +-/****************************************************/ +-/* Connector Object ID Definition */ +-/****************************************************/ +-#define CONNECTOR_OBJECT_ID_NONE 0x00 +-#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 +-#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 +-#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 +-#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 +-#define CONNECTOR_OBJECT_ID_VGA 0x05 +-#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 +-#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 +-#define CONNECTOR_OBJECT_ID_YPbPr 0x08 +-#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 +-#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ +-#define CONNECTOR_OBJECT_ID_SCART 0x0B +-#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C +-#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D +-#define CONNECTOR_OBJECT_ID_LVDS 0x0E +-#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F +-#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 +-#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 +-#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 +-#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 +- +-/* deleted */ +- +-/****************************************************/ +-/* Router Object ID Definition */ +-/****************************************************/ +-#define ROUTER_OBJECT_ID_NONE 0x00 +-#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 +- +-/****************************************************/ +-// Graphics Object ENUM ID Definition */ +-/****************************************************/ +-#define GRAPH_OBJECT_ENUM_ID1 0x01 +-#define GRAPH_OBJECT_ENUM_ID2 0x02 +-#define GRAPH_OBJECT_ENUM_ID3 0x03 +-#define GRAPH_OBJECT_ENUM_ID4 0x04 +- +-/****************************************************/ +-/* Graphics Object ID Bit definition */ +-/****************************************************/ +-#define OBJECT_ID_MASK 0x00FF +-#define ENUM_ID_MASK 0x0700 +-#define RESERVED1_ID_MASK 0x0800 +-#define OBJECT_TYPE_MASK 0x7000 +-#define RESERVED2_ID_MASK 0x8000 +- +-#define OBJECT_ID_SHIFT 0x00 +-#define ENUM_ID_SHIFT 0x08 +-#define OBJECT_TYPE_SHIFT 0x0C +- +- +-/****************************************************/ +-/* Graphics Object family definition */ +-/****************************************************/ +-#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ +- GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) +-/****************************************************/ +-/* GPU Object ID definition - Shared with BIOS */ +-/****************************************************/ +-#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) +- +-/****************************************************/ +-/* Encoder Object ID definition - Shared with BIOS */ +-/****************************************************/ +-/* +-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 +-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 +-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 +-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 +-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 +-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 +-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 +-#define ENCODER_SIL170B_ENUM_ID1 0x2108 +-#define ENCODER_CH7303_ENUM_ID1 0x2109 +-#define ENCODER_CH7301_ENUM_ID1 0x210A +-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B +-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C +-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D +-#define ENCODER_TITFP513_ENUM_ID1 0x210E +-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F +-#define ENCODER_VT1623_ENUM_ID1 0x2110 +-#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 +-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 +-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 +-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 +-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 +-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 +-#define ENCODER_SI178_ENUM_ID1 0x2117 +-#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 +-#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 +-#define ENCODER_VT1625_ENUM_ID1 0x211A +-#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B +-#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C +-#define ENCODER_DP_DP501_ENUM_ID1 0x211D +-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E +-*/ +-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) +- +-#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) +- +-#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) +- +-#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) +- +-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) +- +-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) +- +- +-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) +- +- +-#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) +- +-#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) +- +-#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) +- +-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) +- +- +-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) +- +- +-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT +- +-#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) +- +-#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) +- +-#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) +- +-#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) +- +-#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) +- +-#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) +- +-#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) +- +-/****************************************************/ +-/* Connector Object ID definition - Shared with BIOS */ +-/****************************************************/ +-/* +-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 +-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 +-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 +-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 +-#define CONNECTOR_VGA_ENUM_ID1 0x3105 +-#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 +-#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 +-#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 +-#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 +-#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A +-#define CONNECTOR_SCART_ENUM_ID1 0x310B +-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C +-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D +-#define CONNECTOR_LVDS_ENUM_ID1 0x310E +-#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F +-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 +-*/ +-#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) +- +- +-#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) +- +-#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ +- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) +- +-/****************************************************/ +-/* Router Object ID definition - Shared with BIOS */ +-/****************************************************/ +-#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ +- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ +- ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) +- +-/* deleted */ +- +-/****************************************************/ +-/* Object Cap definition - Shared with BIOS */ +-/****************************************************/ +-#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L +-#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L +- +- +-#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 +-#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 +-#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 +- +-#if defined(_X86_) +-#pragma pack() +-#endif +- +-#endif /*GRAPHICTYPE */ +- +- +- +- ++*/ ++/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ ++ ++#ifndef _OBJECTID_H ++#define _OBJECTID_H ++ ++#if defined(_X86_) ++#pragma pack(1) ++#endif ++ ++/****************************************************/ ++/* Graphics Object Type Definition */ ++/****************************************************/ ++#define GRAPH_OBJECT_TYPE_NONE 0x0 ++#define GRAPH_OBJECT_TYPE_GPU 0x1 ++#define GRAPH_OBJECT_TYPE_ENCODER 0x2 ++#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 ++#define GRAPH_OBJECT_TYPE_ROUTER 0x4 ++/* deleted */ ++ ++/****************************************************/ ++/* Encoder Object ID Definition */ ++/****************************************************/ ++#define ENCODER_OBJECT_ID_NONE 0x00 ++ ++/* Radeon Class Display Hardware */ ++#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 ++#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 ++#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 ++#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 ++#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ ++#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 ++#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 ++ ++/* External Third Party Encoders */ ++#define ENCODER_OBJECT_ID_SI170B 0x08 ++#define ENCODER_OBJECT_ID_CH7303 0x09 ++#define ENCODER_OBJECT_ID_CH7301 0x0A ++#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ ++#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C ++#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D ++#define ENCODER_OBJECT_ID_TITFP513 0x0E ++#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ ++#define ENCODER_OBJECT_ID_VT1623 0x10 ++#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 ++#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 ++/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ ++#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ ++#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ ++#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 ++#define ENCODER_OBJECT_ID_VT1625 0x1A ++#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B ++#define ENCODER_OBJECT_ID_DP_AN9801 0x1C ++#define ENCODER_OBJECT_ID_DP_DP501 0x1D ++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F ++ ++/****************************************************/ ++/* Connector Object ID Definition */ ++/****************************************************/ ++#define CONNECTOR_OBJECT_ID_NONE 0x00 ++#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 ++#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 ++#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 ++#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 ++#define CONNECTOR_OBJECT_ID_VGA 0x05 ++#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 ++#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 ++#define CONNECTOR_OBJECT_ID_YPbPr 0x08 ++#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 ++#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ ++#define CONNECTOR_OBJECT_ID_SCART 0x0B ++#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C ++#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D ++#define CONNECTOR_OBJECT_ID_LVDS 0x0E ++#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F ++#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 ++#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 ++#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 ++#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 ++ ++/* deleted */ ++ ++/****************************************************/ ++/* Router Object ID Definition */ ++/****************************************************/ ++#define ROUTER_OBJECT_ID_NONE 0x00 ++#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 ++ ++/****************************************************/ ++// Graphics Object ENUM ID Definition */ ++/****************************************************/ ++#define GRAPH_OBJECT_ENUM_ID1 0x01 ++#define GRAPH_OBJECT_ENUM_ID2 0x02 ++#define GRAPH_OBJECT_ENUM_ID3 0x03 ++#define GRAPH_OBJECT_ENUM_ID4 0x04 ++ ++/****************************************************/ ++/* Graphics Object ID Bit definition */ ++/****************************************************/ ++#define OBJECT_ID_MASK 0x00FF ++#define ENUM_ID_MASK 0x0700 ++#define RESERVED1_ID_MASK 0x0800 ++#define OBJECT_TYPE_MASK 0x7000 ++#define RESERVED2_ID_MASK 0x8000 ++ ++#define OBJECT_ID_SHIFT 0x00 ++#define ENUM_ID_SHIFT 0x08 ++#define OBJECT_TYPE_SHIFT 0x0C ++ ++ ++/****************************************************/ ++/* Graphics Object family definition */ ++/****************************************************/ ++#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ ++ GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) ++/****************************************************/ ++/* GPU Object ID definition - Shared with BIOS */ ++/****************************************************/ ++#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) ++ ++/****************************************************/ ++/* Encoder Object ID definition - Shared with BIOS */ ++/****************************************************/ ++/* ++#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 ++#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 ++#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 ++#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 ++#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 ++#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 ++#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 ++#define ENCODER_SIL170B_ENUM_ID1 0x2108 ++#define ENCODER_CH7303_ENUM_ID1 0x2109 ++#define ENCODER_CH7301_ENUM_ID1 0x210A ++#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B ++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C ++#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D ++#define ENCODER_TITFP513_ENUM_ID1 0x210E ++#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F ++#define ENCODER_VT1623_ENUM_ID1 0x2110 ++#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 ++#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 ++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 ++#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 ++#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 ++#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 ++#define ENCODER_SI178_ENUM_ID1 0x2117 ++#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 ++#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 ++#define ENCODER_VT1625_ENUM_ID1 0x211A ++#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B ++#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C ++#define ENCODER_DP_DP501_ENUM_ID1 0x211D ++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E ++*/ ++#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) ++ ++#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) ++ ++#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT ++ ++#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) ++ ++#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) ++ ++/****************************************************/ ++/* Connector Object ID definition - Shared with BIOS */ ++/****************************************************/ ++/* ++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 ++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 ++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 ++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 ++#define CONNECTOR_VGA_ENUM_ID1 0x3105 ++#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 ++#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 ++#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 ++#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 ++#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A ++#define CONNECTOR_SCART_ENUM_ID1 0x310B ++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C ++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D ++#define CONNECTOR_LVDS_ENUM_ID1 0x310E ++#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F ++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 ++*/ ++#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) ++ ++ ++#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) ++ ++/****************************************************/ ++/* Router Object ID definition - Shared with BIOS */ ++/****************************************************/ ++#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) ++ ++/* deleted */ ++ ++/****************************************************/ ++/* Object Cap definition - Shared with BIOS */ ++/****************************************************/ ++#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L ++#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L ++ ++ ++#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 ++#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 ++#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 ++ ++#if defined(_X86_) ++#pragma pack() ++#endif ++ ++#endif /*GRAPHICTYPE */ ++ ++ ++ ++ diff --git a/src/Makefile.am b/src/Makefile.am index 70c05e5..5333495 100644 --- a/src/Makefile.am @@ -1373,9 +1034,18 @@ index 70c05e5..5333495 100644 ati_drv_la_LTLIBRARIES = ati_drv.la diff --git a/src/ati.c b/src/ati.c -index b3f07ca..85da389 100644 +index b3f07ca..387aaca 100644 --- a/src/ati.c +++ b/src/ati.c +@@ -78,7 +78,7 @@ enum + ATI_CHIP_FAMILY_Radeon + }; + +-static int ATIChipID(const CARD16); ++static int ATIChipID(const uint16_t); + + #ifdef XSERVER_LIBPCIACCESS + @@ -102,7 +102,7 @@ ati_device_get_from_busid(int bus, int dev, int func) } @@ -1385,11 +1055,28 @@ index b3f07ca..85da389 100644 { struct pci_device *device = NULL; struct pci_device_iterator *device_iter; +@@ -249,7 +249,7 @@ ati_gdev_subdriver(pointer options) + * This returns the ATI_CHIP_FAMILY_* value associated with a particular ChipID. + */ + static int +-ATIChipID(const CARD16 ChipID) ++ATIChipID(const uint16_t ChipID) + { + switch (ChipID) + { diff --git a/src/ati.h b/src/ati.h -index 828aae1..fa2e45e 100644 +index 828aae1..86c40a1 100644 --- a/src/ati.h +++ b/src/ati.h -@@ -31,4 +31,6 @@ +@@ -24,6 +24,7 @@ + #define ___ATI_H___ 1 + + #include ++#include + #include "xf86Pci.h" + #include "xf86PciInfo.h" + +@@ -31,4 +32,6 @@ #include "xf86_OSproc.h" @@ -1397,7 +1084,7 @@ index 828aae1..fa2e45e 100644 + #endif /* ___ATI_H___ */ diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index 330d1a9..b5e000c 100644 +index 330d1a9..eee1d60 100644 --- a/src/ati_pciids_gen.h +++ b/src/ati_pciids_gen.h @@ -281,9 +281,9 @@ @@ -1413,7 +1100,17 @@ index 330d1a9..b5e000c 100644 #define PCI_CHIP_R580_7240 0x7240 #define PCI_CHIP_R580_7243 0x7243 #define PCI_CHIP_R580_7244 0x7244 -@@ -356,3 +356,22 @@ +@@ -315,6 +315,9 @@ + #define PCI_CHIP_RS350_7835 0x7835 + #define PCI_CHIP_RS690_791E 0x791E + #define PCI_CHIP_RS690_791F 0x791F ++#define PCI_CHIP_RS600_793F 0x793F ++#define PCI_CHIP_RS600_7941 0x7941 ++#define PCI_CHIP_RS600_7942 0x7942 + #define PCI_CHIP_RS740_796C 0x796C + #define PCI_CHIP_RS740_796D 0x796D + #define PCI_CHIP_RS740_796E 0x796E +@@ -356,3 +359,22 @@ #define PCI_CHIP_RV630_958C 0x958C #define PCI_CHIP_RV630_958D 0x958D #define PCI_CHIP_RV630_958E 0x958E @@ -1450,7 +1147,7 @@ index c249333..f0eb147 100644 static XF86ModuleVersionInfo ATIVersionRec = diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c -index bc2df18..bab56b2 100644 +index bc2df18..b5b7ca8 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -1,10 +1,5 @@ @@ -1550,33 +1247,39 @@ index bc2df18..bab56b2 100644 break; } } -@@ -155,12 +165,20 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) +@@ -151,24 +161,34 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ + } + + void +-atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) ++atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) { RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(crtc->scrn); + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); unsigned char *RADEONMMIO = info->MMIO; int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); - CARD32 sclock = mode->Clock; - CARD32 ref_div = 0, fb_div = 0, post_div = 0; +- CARD32 sclock = mode->Clock; +- CARD32 ref_div = 0, fb_div = 0, post_div = 0; - int major, minor; ++ uint32_t sclock = mode->Clock; ++ uint32_t ref_div = 0, fb_div = 0, post_div = 0; + int major, minor, i; SET_PIXEL_CLOCK_PS_ALLOCATION spc_param; + PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; + PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; -+ int pll_flags = 0; -+ + xf86OutputPtr output; + RADEONOutputPrivatePtr radeon_output = NULL; + void *ptr; AtomBiosArgRec data; unsigned char *space; -@@ -168,7 +186,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) + RADEONSavePtr save = info->ModeReg; if (IS_AVIVO_VARIANT) { - CARD32 temp; +- CARD32 temp; - RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0); ++ uint32_t temp; + + if (IS_DCE3_VARIANT) + pll_flags |= RADEON_PLL_DCE3; @@ -1585,7 +1288,7 @@ index bc2df18..bab56b2 100644 sclock = temp; /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ -@@ -193,25 +215,86 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) +@@ -193,25 +213,86 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n", radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned int)fb_div, (unsigned int)fb_div, (unsigned int)post_div); @@ -1682,7 +1385,7 @@ index bc2df18..bab56b2 100644 default: ErrorF("Unknown table version\n"); exit(-1); -@@ -247,26 +330,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -247,26 +328,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation; @@ -1690,8 +1393,9 @@ index bc2df18..bab56b2 100644 int need_tv_timings = 0; int i, ret; SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; +- + Bool tilingChanged = FALSE; - ++ int pll_flags = 0; memset(&crtc_timing, 0, sizeof(crtc_timing)); if (info->allowColorTiling) { @@ -1712,7 +1416,17 @@ index bc2df18..bab56b2 100644 } for (i = 0; i < xf86_config->num_output; i++) { -@@ -334,27 +407,25 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -283,6 +354,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, + need_tv_timings = 2; + + } ++ ++ if (radeon_output->MonType == MT_LCD) ++ pll_flags |= RADEON_PLL_USE_REF_DIV; + } + } + +@@ -334,27 +408,25 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); if (IS_AVIVO_VARIANT) { @@ -1720,7 +1434,7 @@ index bc2df18..bab56b2 100644 - radeon_crtc->fb_height = pScrn->virtualY; - radeon_crtc->fb_pitch = mode->CrtcHDisplay; - radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4; -+ CARD32 fb_format; ++ uint32_t fb_format; + switch (crtc->scrn->bitsPerPixel) { case 15: @@ -1746,7 +1460,7 @@ index bc2df18..bab56b2 100644 } if (radeon_crtc->crtc_id == 0) -@@ -376,17 +447,14 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -376,17 +448,14 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); @@ -1769,7 +1483,7 @@ index bc2df18..bab56b2 100644 OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, crtc->scrn->displayWidth); OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); -@@ -398,7 +466,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -398,7 +467,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, @@ -1778,7 +1492,12 @@ index bc2df18..bab56b2 100644 OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay); -@@ -411,7 +479,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -407,11 +476,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, + + } + +- atombios_crtc_set_pll(crtc, adjusted_mode); ++ atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags); atombios_set_crtc_timing(info->atomBIOS, &crtc_timing); @@ -1788,7 +1507,7 @@ index bc2df18..bab56b2 100644 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ if (pScrn->pScreen) diff --git a/src/atombios_output.c b/src/atombios_output.c -index 07d212f..d8e88ca 100644 +index 07d212f..51be301 100644 --- a/src/atombios_output.c +++ b/src/atombios_output.c @@ -235,7 +235,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) @@ -2025,7 +1744,7 @@ index 07d212f..d8e88ca 100644 atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) { RADEONInfoPtr info = RADEONPTR(output->scrn); -@@ -382,6 +600,33 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -382,6 +600,34 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) } @@ -2040,7 +1759,8 @@ index 07d212f..d8e88ca 100644 + OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, 0); /* TMDSA */ + break; + case ATOM_DEVICE_DFP2_SUPPORT: -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) + OUTREG(AVIVO_DDIA_BIT_DEPTH_CONTROL, 0); /* DDIA */ + else @@ -2059,7 +1779,7 @@ index 07d212f..d8e88ca 100644 static AtomBiosResult atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state) { -@@ -452,40 +697,94 @@ atombios_device_dpms(xf86OutputPtr output, int device, int mode) +@@ -452,40 +698,94 @@ atombios_device_dpms(xf86OutputPtr output, int device, int mode) } } @@ -2183,7 +1903,7 @@ index 07d212f..d8e88ca 100644 } -@@ -498,15 +797,13 @@ atombios_set_output_crtc_source(xf86OutputPtr output) +@@ -498,15 +798,13 @@ atombios_set_output_crtc_source(xf86OutputPtr output) AtomBiosArgRec data; unsigned char *space; SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param; @@ -2201,7 +1921,7 @@ index 07d212f..d8e88ca 100644 switch(major) { case 1: { -@@ -514,6 +811,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) +@@ -514,6 +812,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) case 0: case 1: default: @@ -2210,7 +1930,7 @@ index 07d212f..d8e88ca 100644 if (radeon_output->MonType == MT_CRT) { if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX; -@@ -536,6 +835,46 @@ atombios_set_output_crtc_source(xf86OutputPtr output) +@@ -536,6 +836,46 @@ atombios_set_output_crtc_source(xf86OutputPtr output) if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) crtc_src_param.ucDevice = ATOM_DEVICE_CV_INDEX; } @@ -2257,7 +1977,7 @@ index 07d212f..d8e88ca 100644 break; } break; -@@ -544,11 +883,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) +@@ -544,11 +884,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) break; } @@ -2269,7 +1989,7 @@ index 07d212f..d8e88ca 100644 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id); -@@ -579,19 +915,47 @@ atombios_output_mode_set(xf86OutputPtr output, +@@ -579,19 +916,48 @@ atombios_output_mode_set(xf86OutputPtr output, atombios_output_dac2_setup(output, adjusted_mode); } } else if (radeon_output->MonType == MT_DFP) { @@ -2294,7 +2014,8 @@ index 07d212f..d8e88ca 100644 + if (IS_DCE3_VARIANT) { + // fix me + } else { -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) + atombios_output_ddia_setup(output, adjusted_mode); + else @@ -2329,7 +2050,7 @@ index 07d212f..d8e88ca 100644 if (radeon_output->DACType == DAC_PRIMARY) atombios_output_dac1_setup(output, adjusted_mode); else if (radeon_output->DACType == DAC_TVDAC) -@@ -605,10 +969,13 @@ static AtomBiosResult +@@ -605,10 +971,13 @@ static AtomBiosResult atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) { RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -2343,7 +2064,7 @@ index 07d212f..d8e88ca 100644 if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT; if (radeon_output->DACType == DAC_PRIMARY) -@@ -627,18 +994,21 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) +@@ -627,18 +996,21 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) dac_data.sDacload.ucDacType = ATOM_DAC_A; else if (radeon_output->DACType == DAC_TVDAC) dac_data.sDacload.ucDacType = ATOM_DAC_B; @@ -2366,7 +2087,7 @@ index 07d212f..d8e88ca 100644 data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); data.exec.dataSpace = (void *)&space; -@@ -679,7 +1049,7 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output) +@@ -679,7 +1051,7 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output) bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); else bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); @@ -2375,15 +2096,43 @@ index 07d212f..d8e88ca 100644 if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { if (bios_0_scratch & ATOM_S0_CRT1_MASK) +diff --git a/src/generic_bus.h b/src/generic_bus.h +index 6197eab..a04baa1 100644 +--- a/src/generic_bus.h ++++ b/src/generic_bus.h +@@ -4,6 +4,7 @@ + /* this is meant to be used for proprietary buses where abstraction is needed + but they don't occur often enough to warrant a separate helper library */ + ++#include + + #define GB_IOCTL_GET_NAME 1 + /* third argument is size of the buffer, fourth argument is pointer +@@ -21,10 +22,10 @@ typedef struct _GENERIC_BUS_Rec{ + int scrnIndex; + DevUnion DriverPrivate; + Bool (*ioctl)(GENERIC_BUS_Ptr, long, long, char *); +- Bool (*read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); +- Bool (*write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); +- Bool (*fifo_read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); +- Bool (*fifo_write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); ++ Bool (*read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); ++ Bool (*write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); ++ Bool (*fifo_read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); ++ Bool (*fifo_write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); + + } GENERIC_BUS_Rec; + diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c -index 06ad60c..5ef86ce 100644 +index 06ad60c..489fecf 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c -@@ -78,6 +78,13 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, +@@ -78,6 +78,14 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1); + OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2); + OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1); @@ -2393,7 +2142,25 @@ index 06ad60c..5ef86ce 100644 /* Workaround for the VT switching problem in dual-head mode. This * problem only occurs on RV style chips, typically when a FP and * CRT are connected. -@@ -178,12 +185,6 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, +@@ -85,7 +93,7 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, + if (pRADEONEnt->HasCRTC2 && + info->ChipFamily != CHIP_FAMILY_R200 && + !IS_R300_VARIANT) { +- CARD32 tmp; ++ uint32_t tmp; + + tmp = INREG(RADEON_DAC_CNTL2); + OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); +@@ -148,7 +156,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- /* CARD32 crtc2_gen_cntl;*/ ++ /* uint32_t crtc2_gen_cntl;*/ + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Programming CRTC2, offset: 0x%08x\n", +@@ -178,12 +186,6 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); @@ -2406,12 +2173,72 @@ index 06ad60c..5ef86ce 100644 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); } -@@ -489,6 +490,13 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -238,9 +240,9 @@ RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) + ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); + } + +-static CARD8 +-RADEONComputePLLGain(CARD16 reference_freq, CARD16 ref_div, +- CARD16 fb_div) ++static uint8_t ++RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, ++ uint16_t fb_div) + { + unsigned vcoFreq; + +@@ -277,7 +279,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD8 pllGain; ++ uint8_t pllGain; + + #if defined(__powerpc__) + /* apparently restoring the pll causes a hang??? */ +@@ -316,7 +318,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, + RADEON_PPLL_RESET + | RADEON_PPLL_ATOMIC_UPDATE_EN + | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN +- | ((CARD32)pllGain << RADEON_PPLL_PVG_SHIFT), ++ | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), + ~(RADEON_PPLL_RESET + | RADEON_PPLL_ATOMIC_UPDATE_EN + | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN +@@ -329,7 +331,8 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, + + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_RS300) || +- (info->ChipFamily == CHIP_FAMILY_RS400)) { ++ (info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { + /* When restoring console mode, use saved PPLL_REF_DIV + * setting. +@@ -399,7 +402,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, + RADEONSavePtr restore) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD8 pllGain; ++ uint8_t pllGain; + + pllGain = RADEONComputePLLGain(info->pll.reference_freq, + restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, +@@ -414,7 +417,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, + RADEON_P2PLL_CNTL, + RADEON_P2PLL_RESET + | RADEON_P2PLL_ATOMIC_UPDATE_EN +- | ((CARD32)pllGain << RADEON_P2PLL_PVG_SHIFT), ++ | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), + ~(RADEON_P2PLL_RESET + | RADEON_P2PLL_ATOMIC_UPDATE_EN + | RADEON_P2PLL_PVG_MASK)); +@@ -489,6 +492,14 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->surface_cntl = INREG(RADEON_SURFACE_CNTL); save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); + -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1); + save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2); + save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1); @@ -2420,7 +2247,7 @@ index 06ad60c..5ef86ce 100644 } /* Read CRTC registers */ -@@ -550,13 +558,6 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -550,13 +561,6 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); @@ -2434,12 +2261,13 @@ index 06ad60c..5ef86ce 100644 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); /* track if the crtc is enabled for text restore */ -@@ -677,6 +678,14 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) +@@ -677,6 +681,15 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) save->cap0_trig_cntl = 0; save->cap1_trig_cntl = 0; save->bus_cntl = info->BusCntl; + -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1; + save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2; + save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1; @@ -2449,7 +2277,7 @@ index 06ad60c..5ef86ce 100644 /* * If bursts are enabled, turn on discards * Radeon doesn't have write bursts -@@ -1125,13 +1134,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -1125,13 +1138,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; @@ -2463,12 +2291,85 @@ index 06ad60c..5ef86ce 100644 return TRUE; } -@@ -1554,6 +1556,24 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1143,10 +1149,10 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + int flags) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 feedback_div = 0; +- CARD32 reference_div = 0; +- CARD32 post_divider = 0; +- CARD32 freq = 0; ++ uint32_t feedback_div = 0; ++ uint32_t reference_div = 0; ++ uint32_t post_divider = 0; ++ uint32_t freq = 0; + + struct { + int divider; +@@ -1224,10 +1230,10 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + int flags) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 feedback_div = 0; +- CARD32 reference_div = 0; +- CARD32 post_divider = 0; +- CARD32 freq = 0; ++ uint32_t feedback_div = 0; ++ uint32_t reference_div = 0; ++ uint32_t post_divider = 0; ++ uint32_t freq = 0; + + struct { + int divider; +@@ -1306,16 +1312,16 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; ++ uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; + float mem_tcas; + int k1, c; +- CARD32 MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; +- CARD32 MemTrpExtMemCntl[4] = {1, 2, 3, 4}; +- CARD32 MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; ++ uint32_t MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; ++ uint32_t MemTrpExtMemCntl[4] = {1, 2, 3, 4}; ++ uint32_t MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + +- CARD32 MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; +- CARD32 MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; +- CARD32 MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; ++ uint32_t MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; ++ uint32_t MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; ++ uint32_t MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; + + float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; + float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; +@@ -1338,7 +1344,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + * option. + */ + if ((info->DispPriority == 2) && IS_R300_VARIANT) { +- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); ++ uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + if (pRADEONEnt->pCrtc[1]->enabled) { + mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ + } else { +@@ -1512,7 +1518,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + /* + Find the critical point of the display buffer. + */ +- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); ++ critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); + + /* ???? */ + /* +@@ -1554,6 +1560,25 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); +#if 0 -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + /* attempt to program RS400 disp regs correctly ??? */ + temp = info->SavedReg->disp1_req_cntl1; + temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | @@ -2488,11 +2389,21 @@ index 06ad60c..5ef86ce 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "GRPH_BUFFER_CNTL from %x to %x\n", (unsigned int)info->SavedReg->grph_buffer_cntl, -@@ -1604,6 +1624,28 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1585,7 +1610,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); + time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); + +- critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority + ++ critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + + disp_latency) * disp_drain_rate2 + 0.5); + + if (info->DispPriority == 2) { +@@ -1604,6 +1629,29 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { +#if 0 + /* attempt to program RS400 disp2 regs correctly ??? */ + temp = info->SavedReg->disp2_req_cntl1; @@ -2517,7 +2428,7 @@ index 06ad60c..5ef86ce 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "GRPH2_BUFFER_CNTL from %x to %x\n", (unsigned int)info->SavedReg->grph2_buffer_cntl, -@@ -1658,26 +1700,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -1658,26 +1706,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -2547,7 +2458,7 @@ index 06ad60c..5ef86ce 100644 } for (i = 0; i < xf86_config->num_output; i++) { -@@ -1775,7 +1806,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -1775,7 +1812,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, if (info->DispPriority) RADEONInitDispBandwidth(pScrn); @@ -2557,14 +2468,24 @@ index 06ad60c..5ef86ce 100644 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ if (pScrn->pScreen) diff --git a/src/legacy_output.c b/src/legacy_output.c -index 0de13df..a65a41e 100644 +index 0de13df..4df81ab 100644 --- a/src/legacy_output.c +++ b/src/legacy_output.c -@@ -103,6 +103,12 @@ RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -71,7 +71,7 @@ RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, + OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); + + if ((info->ChipFamily != CHIP_FAMILY_RADEON) && +- (info->ChipFamily != CHIP_FAMILY_R200)) ++ (info->ChipFamily != CHIP_FAMILY_R200)) + OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); + + OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl); +@@ -103,6 +103,13 @@ RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl); -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + OUTREG(RS400_FP_2ND_GEN_CNTL, restore->fp_2nd_gen_cntl); + /*OUTREG(RS400_TMDS2_CNTL, restore->tmds2_cntl);*/ + OUTREG(RS400_TMDS2_TRANSMITTER_CNTL, restore->tmds2_transmitter_cntl); @@ -2573,21 +2494,23 @@ index 0de13df..a65a41e 100644 /* old AIW Radeon has some BIOS initialization problem * with display buffer underflow, only occurs to DFP */ -@@ -121,6 +127,8 @@ RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -121,6 +128,9 @@ RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); -+ if (info->ChipFamily == CHIP_FAMILY_RS400) ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) + OUTREG(RS400_FP2_2_GEN_CNTL, restore->fp2_2_gen_cntl); } /* Write RMX registers */ -@@ -203,6 +211,14 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -203,10 +213,19 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ save->tmds_pll_cntl ^= (1 << 22); } + -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + save->fp_2nd_gen_cntl = INREG(RS400_FP_2ND_GEN_CNTL); + save->fp2_2_gen_cntl = INREG(RS400_FP2_2_GEN_CNTL); + save->tmds2_cntl = INREG(RS400_TMDS2_CNTL); @@ -2597,7 +2520,52 @@ index 0de13df..a65a41e 100644 } Bool -@@ -675,9 +691,9 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +-RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) ++RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch) + { + if (!xf86I2CReadByte(dvo, addr, ch)) { + xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, +@@ -218,7 +237,7 @@ RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) + } + + Bool +-RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch) ++RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch) + { + if (!xf86I2CWriteByte(dvo, addr, ch)) { + xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, +@@ -266,7 +285,7 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) + + OUTREG(radeon_output->dvo_i2c.mask_clk_reg, + INREG(radeon_output->dvo_i2c.mask_clk_reg) & +- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); ++ (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); + + if (!RADEONInitExtTMDSInfoFromBIOS(output)) { + if (radeon_output->DVOChip) { +@@ -596,8 +615,8 @@ RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) + unsigned char *RADEONMMIO = info->MMIO; + + if (IsPrimaryDAC) { +- CARD32 dac_cntl; +- CARD32 dac_macro_cntl = 0; ++ uint32_t dac_cntl; ++ uint32_t dac_macro_cntl = 0; + dac_cntl = INREG(RADEON_DAC_CNTL); + dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); + if (IsOn) { +@@ -614,8 +633,8 @@ RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) + OUTREG(RADEON_DAC_CNTL, dac_cntl); + OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); + } else { +- CARD32 tv_dac_cntl; +- CARD32 fp2_gen_cntl; ++ uint32_t tv_dac_cntl; ++ uint32_t fp2_gen_cntl; + + switch(info->ChipFamily) + { +@@ -675,9 +694,9 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) unsigned long tmp; RADEONOutputPrivatePtr radeon_output; int tv_dac_change = 0, o; @@ -2608,7 +2576,7 @@ index 0de13df..a65a41e 100644 for (o = 0; o < xf86_config->num_output; o++) { if (output == xf86_config->output[o]) { break; -@@ -685,7 +701,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -685,7 +704,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) } if (bEnable) { @@ -2617,11 +2585,12 @@ index 0de13df..a65a41e 100644 if (radeon_output->MonType == MT_CRT) { if (radeon_output->DACType == DAC_PRIMARY) { info->output_crt1 |= (1 << o); -@@ -716,6 +732,13 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -716,6 +735,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); OUTREG(RADEON_FP_GEN_CNTL, tmp); save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + tmp = INREG(RS400_FP_2ND_GEN_CNTL); + tmp |= (RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); + OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); @@ -2631,11 +2600,12 @@ index 0de13df..a65a41e 100644 } else if (radeon_output->TMDSType == TMDS_EXT) { info->output_dfp2 |= (1 << o); tmp = INREG(RADEON_FP2_GEN_CNTL); -@@ -724,6 +747,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -724,6 +751,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) OUTREG(RADEON_FP2_GEN_CNTL, tmp); save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + tmp = INREG(RS400_FP2_2_GEN_CNTL); + tmp &= ~RS400_FP2_2_BLANK_EN; + tmp |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); @@ -2646,7 +2616,7 @@ index 0de13df..a65a41e 100644 } } else if (radeon_output->MonType == MT_LCD) { info->output_lcd1 |= (1 << o); -@@ -744,7 +775,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -744,7 +780,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) radeon_output->tv_on = TRUE; } } else { @@ -2655,11 +2625,12 @@ index 0de13df..a65a41e 100644 if (radeon_output->MonType == MT_CRT) { if (radeon_output->DACType == DAC_PRIMARY) { info->output_crt1 &= ~(1 << o); -@@ -780,6 +811,13 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -780,6 +816,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); OUTREG(RADEON_FP_GEN_CNTL, tmp); save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + tmp = INREG(RS400_FP_2ND_GEN_CNTL); + tmp &= ~(RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); + OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); @@ -2669,11 +2640,12 @@ index 0de13df..a65a41e 100644 } } else if (radeon_output->TMDSType == TMDS_EXT) { info->output_dfp2 &= ~(1 << o); -@@ -790,6 +828,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -790,6 +834,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) OUTREG(RADEON_FP2_GEN_CNTL, tmp); save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + tmp = INREG(RS400_FP2_2_GEN_CNTL); + tmp |= RS400_FP2_2_BLANK_EN; + tmp &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); @@ -2684,11 +2656,26 @@ index 0de13df..a65a41e 100644 } } } else if (radeon_output->MonType == MT_LCD) { -@@ -918,6 +964,29 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -862,11 +915,11 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int i; +- CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; ++ uint32_t tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; + + for (i=0; i<4; i++) { + if (radeon_output->tmds_pll[i].freq == 0) break; +- if ((CARD32)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) { ++ if ((uint32_t)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) { + tmp = radeon_output->tmds_pll[i].value ; + break; + } +@@ -918,6 +971,30 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2; } -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl & + ~(RS400_TMDS2_PLLRST); + save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN); @@ -2714,7 +2701,7 @@ index 0de13df..a65a41e 100644 } static void -@@ -954,6 +1023,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, +@@ -954,6 +1031,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; if (radeon_output->Flags & RADEON_USE_RMX) save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; @@ -2723,11 +2710,12 @@ index 0de13df..a65a41e 100644 } else { save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; } -@@ -966,6 +1037,27 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, +@@ -966,6 +1045,28 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, } } -+ if (info->ChipFamily == CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + if (pScrn->rgbBits == 8) + save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl | + RS400_FP2_2_PANEL_FORMAT; /* 24 bit format, */ @@ -2751,19 +2739,178 @@ index 0de13df..a65a41e 100644 } static void +@@ -1015,14 +1116,15 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int xres = mode->HDisplay; + int yres = mode->VDisplay; +- float Hratio, Vratio; ++ Bool Hscale = TRUE, Vscale = TRUE; + int hsync_wid; + int vsync_wid; + int hsync_start; + + + save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & +- RADEON_VERT_STRETCH_RESERVED; ++ (RADEON_VERT_STRETCH_RESERVED | ++ RADEON_VERT_AUTO_RATIO_INC); + save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & + (RADEON_HORZ_FP_LOOP_STRETCH | + RADEON_HORZ_AUTO_RATIO_INC); +@@ -1069,34 +1171,41 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, + return; + + if (radeon_output->PanelXRes == 0 || radeon_output->PanelYRes == 0) { +- Hratio = 1.0; +- Vratio = 1.0; ++ Hscale = FALSE; ++ Vscale = FALSE; + } else { + if (xres > radeon_output->PanelXRes) xres = radeon_output->PanelXRes; + if (yres > radeon_output->PanelYRes) yres = radeon_output->PanelYRes; + +- Hratio = (float)xres/(float)radeon_output->PanelXRes; +- Vratio = (float)yres/(float)radeon_output->PanelYRes; ++ if (xres == radeon_output->PanelXRes) ++ Hscale = FALSE; ++ if (yres == radeon_output->PanelYRes) ++ Vscale = FALSE; + } + +- if ((Hratio == 1.0) || (!(radeon_output->Flags & RADEON_USE_RMX)) || ++ if ((!Hscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || + (radeon_output->rmx_type == RMX_CENTER)) { + save->fp_horz_stretch |= ((xres/8-1)<<16); + } else { +- save->fp_horz_stretch |= ((((unsigned long) +- (Hratio * RADEON_HORZ_STRETCH_RATIO_MAX)) & +- RADEON_HORZ_STRETCH_RATIO_MASK) | ++ CARD32 scale, inc; ++ inc = (save->fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; ++ scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) ++ / radeon_output->PanelXRes + 1; ++ save->fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | + RADEON_HORZ_STRETCH_BLEND | + RADEON_HORZ_STRETCH_ENABLE | + ((radeon_output->PanelXRes/8-1)<<16)); + } + +- if ((Vratio == 1.0) || (!(radeon_output->Flags & RADEON_USE_RMX)) || ++ if ((!Vscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || + (radeon_output->rmx_type == RMX_CENTER)) { + save->fp_vert_stretch |= ((yres-1)<<12); + } else { +- save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX)) & +- RADEON_VERT_STRETCH_RATIO_MASK) | ++ CARD32 scale, inc; ++ inc = (save->fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; ++ scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) ++ / radeon_output->PanelYRes + 1; ++ save->fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | + RADEON_VERT_STRETCH_ENABLE | + RADEON_VERT_STRETCH_BLEND | + ((radeon_output->PanelYRes-1)<<12)); +@@ -1310,7 +1419,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, + ErrorF("restore FP2\n"); + if (info->IsAtomBios) { + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 fp2_gen_cntl; ++ uint32_t fp2_gen_cntl; + + atombios_external_tmds_setup(output, mode); + /* r4xx atom has hard coded crtc mappings in the atom code +@@ -1354,8 +1463,8 @@ radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 vclk_ecp_cntl, crtc_ext_cntl; +- CARD32 dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; ++ uint32_t vclk_ecp_cntl, crtc_ext_cntl; ++ uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; + RADEONMonitorType found = MT_NONE; + + /* save the regs we need */ +@@ -1421,11 +1530,11 @@ radeon_detect_ext_dac(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; +- CARD32 disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; +- CARD32 disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; +- CARD32 tmp, crtc2_h_total_disp, crtc2_v_total_disp; +- CARD32 crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; ++ uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; ++ uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; ++ uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; ++ uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; ++ uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; + RADEONMonitorType found = MT_NONE; + int connected = 0; + int i = 0; +@@ -1517,8 +1626,8 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; +- CARD32 disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; ++ uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; ++ uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; + RADEONMonitorType found = MT_NONE; + + /* save the regs we need */ +@@ -1619,8 +1728,8 @@ r300_detect_tv(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; +- CARD32 gpiopad_a, disp_output_cntl; ++ uint32_t tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; ++ uint32_t gpiopad_a, disp_output_cntl; + RADEONMonitorType found = MT_NONE; + + /* save the regs we need */ +@@ -1695,8 +1804,8 @@ radeon_detect_tv(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 tmp, dac_cntl2, tv_master_cntl; +- CARD32 tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; ++ uint32_t tmp, dac_cntl2, tv_master_cntl; ++ uint32_t tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; + RADEONMonitorType found = MT_NONE; + + if (IS_R300_VARIANT) diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index 5a2191a..fc340e7 100644 +index 5a2191a..5c89b55 100644 --- a/src/pcidb/ati_pciids.csv +++ b/src/pcidb/ati_pciids.csv -@@ -187,7 +187,7 @@ +@@ -179,20 +179,20 @@ + "0x5656","MACH64VV","MACH64",,,,,, + "0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834" + "0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835" +-"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" +-"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" ++"0x5954","RS480_5954","RS480",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" ++"0x5955","RS480_5955","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" + "0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)" + "0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)" + "0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)" "0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)" "0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)" "0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)" -"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" -+"0x5974","RS482_5974","RS400",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" - "0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" +-"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" ++"0x5974","RS482_5974","RS480",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" ++"0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" "0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)" "0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)" +-"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" +-"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" ++"0x5A61","RC410_5A61","RS480",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" ++"0x5A62","RC410_5A62","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" + "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" + "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" + "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" @@ -282,9 +282,9 @@ "0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT" "0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200" @@ -2777,7 +2924,17 @@ index 5a2191a..fc340e7 100644 "0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950" "0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900" "0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950" -@@ -331,13 +331,13 @@ +@@ -316,6 +316,9 @@ + "0x7835","RS350_7835","RS300",1,1,,,1,"ATI Radeon Mobility 9200 IGP 7835" + "0x791E","RS690_791E","RS690",,1,,,1,"ATI Radeon X1200" + "0x791F","RS690_791F","RS690",,1,,,1,"ATI Radeon X1200" ++"0x793F","RS600_793F","RS600",,1,,,1,"ATI Radeon X1200" ++"0x7941","RS600_7941","RS600",,1,,,1,"ATI Radeon X1200" ++"0x7942","RS600_7942","RS600",,1,,,1,"ATI Radeon X1200" + "0x796C","RS740_796C","RS740",,1,,,1,"ATI RS740" + "0x796D","RS740_796D","RS740",,1,,,1,"ATI RS740M" + "0x796E","RS740_796E","RS740",,1,,,1,"ATI RS740" +@@ -331,13 +334,13 @@ "0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" "0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" "0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" @@ -2793,7 +2950,7 @@ index 5a2191a..fc340e7 100644 "0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610" "0x9500","RV670_9500","RV670",,,,,,"ATI RV670" "0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870" -@@ -348,12 +348,31 @@ +@@ -348,12 +351,31 @@ "0x9580","RV630_9580","RV630",,,,,,"ATI RV630" "0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" "0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" @@ -2830,10 +2987,22 @@ index 5a2191a..fc340e7 100644 +"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" +"0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" diff --git a/src/radeon.h b/src/radeon.h -index aba3c0f..feff48f 100644 +index aba3c0f..9363c29 100644 --- a/src/radeon.h +++ b/src/radeon.h -@@ -167,7 +167,8 @@ typedef enum { +@@ -98,6 +98,11 @@ + #define MIN(a,b) ((a)>(b)?(b):(a)) + #endif + ++/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ ++#if !defined(__GNUC__) && !defined(__FUNCTION__) ++# define __FUNCTION__ __func__ /* C99 */ ++#endif ++ + #ifndef HAVE_XF86MODEBANDWIDTH + extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); + #define MODE_BANDWIDTH MODE_BAD +@@ -167,7 +172,8 @@ typedef enum { OPTION_TVDAC_LOAD_DETECT, OPTION_FORCE_TVOUT, OPTION_TVSTD, @@ -2843,17 +3012,84 @@ index aba3c0f..feff48f 100644 } RADEONOpts; -@@ -213,6 +214,7 @@ typedef struct { +@@ -198,38 +204,39 @@ typedef enum { + + typedef struct { + int revision; +- CARD16 rr1_offset; +- CARD16 rr2_offset; +- CARD16 dyn_clk_offset; +- CARD16 pll_offset; +- CARD16 mem_config_offset; +- CARD16 mem_reset_offset; +- CARD16 short_mem_offset; +- CARD16 rr3_offset; +- CARD16 rr4_offset; ++ uint16_t rr1_offset; ++ uint16_t rr2_offset; ++ uint16_t dyn_clk_offset; ++ uint16_t pll_offset; ++ uint16_t mem_config_offset; ++ uint16_t mem_reset_offset; ++ uint16_t short_mem_offset; ++ uint16_t rr3_offset; ++ uint16_t rr4_offset; + } RADEONBIOSInitTable; + + #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) #define RADEON_PLL_LEGACY (1 << 3) +#define RADEON_PLL_DCE3 (1 << 4) typedef struct { - CARD16 reference_freq; -@@ -268,12 +270,15 @@ typedef enum { +- CARD16 reference_freq; +- CARD16 reference_div; +- CARD32 pll_in_min; +- CARD32 pll_in_max; +- CARD32 pll_out_min; +- CARD32 pll_out_max; +- CARD16 xclk; +- +- CARD32 min_ref_div; +- CARD32 max_ref_div; +- CARD32 min_post_div; +- CARD32 max_post_div; +- CARD32 min_feedback_div; +- CARD32 max_feedback_div; +- CARD32 best_vco; ++ uint16_t reference_freq; ++ uint16_t reference_div; ++ uint32_t pll_in_min; ++ uint32_t pll_in_max; ++ uint32_t pll_out_min; ++ uint32_t pll_out_max; ++ uint16_t xclk; ++ ++ uint32_t min_ref_div; ++ uint32_t max_ref_div; ++ uint32_t min_post_div; ++ uint32_t max_post_div; ++ uint32_t min_feedback_div; ++ uint32_t max_feedback_div; ++ uint32_t best_vco; + } RADEONPLLRec, *RADEONPLLPtr; + + typedef struct { +@@ -260,20 +267,25 @@ typedef enum { + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_RV410, /* RV410, M26 */ +- CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ ++ CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ ++ CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ + CHIP_FAMILY_RV515, /* rv515 */ + CHIP_FAMILY_R520, /* r520 */ + CHIP_FAMILY_RV530, /* rv530 */ + CHIP_FAMILY_R580, /* r580 */ CHIP_FAMILY_RV560, /* rv560 */ CHIP_FAMILY_RV570, /* rv570 */ ++ CHIP_FAMILY_RS600, CHIP_FAMILY_RS690, - CHIP_FAMILY_R600, /* r60 */ + CHIP_FAMILY_RS740, @@ -2869,7 +3105,13 @@ index aba3c0f..feff48f 100644 CHIP_FAMILY_LAST } RADEONChipFamily; -@@ -296,6 +301,25 @@ typedef enum { +@@ -292,10 +304,32 @@ typedef enum { + (info->ChipFamily == CHIP_FAMILY_RV380) || \ + (info->ChipFamily == CHIP_FAMILY_R420) || \ + (info->ChipFamily == CHIP_FAMILY_RV410) || \ +- (info->ChipFamily == CHIP_FAMILY_RS400)) ++ (info->ChipFamily == CHIP_FAMILY_RS400) || \ ++ (info->ChipFamily == CHIP_FAMILY_RS480)) #define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) @@ -2889,13 +3131,252 @@ index aba3c0f..feff48f 100644 + (info->ChipFamily == CHIP_FAMILY_R420) || \ + (info->ChipFamily == CHIP_FAMILY_RV410) || \ + (info->ChipFamily == CHIP_FAMILY_RS690) || \ ++ (info->ChipFamily == CHIP_FAMILY_RS600) || \ + (info->ChipFamily == CHIP_FAMILY_RS740) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS400)) ++ (info->ChipFamily == CHIP_FAMILY_RS400) || \ ++ (info->ChipFamily == CHIP_FAMILY_RS480)) + /* * Errata workarounds */ -@@ -736,6 +760,9 @@ typedef struct { +@@ -333,7 +367,7 @@ typedef enum { + typedef struct _atomBiosHandle *atomBiosHandlePtr; + + typedef struct { +- CARD32 pci_device_id; ++ uint32_t pci_device_id; + RADEONChipFamily chip_family; + int mobility; + int igp; +@@ -353,22 +387,22 @@ typedef struct { + unsigned long LinearAddr; /* Frame buffer physical address */ + unsigned long MMIOAddr; /* MMIO region physical address */ + unsigned long BIOSAddr; /* BIOS physical address */ +- CARD32 fbLocation; +- CARD32 gartLocation; +- CARD32 mc_fb_location; +- CARD32 mc_agp_location; +- CARD32 mc_agp_location_hi; ++ uint32_t fbLocation; ++ uint32_t gartLocation; ++ uint32_t mc_fb_location; ++ uint32_t mc_agp_location; ++ uint32_t mc_agp_location_hi; + + void *MMIO; /* Map of MMIO region */ + void *FB; /* Map of frame buffer */ +- CARD8 *VBIOS; /* Video BIOS pointer */ ++ uint8_t *VBIOS; /* Video BIOS pointer */ + + Bool IsAtomBios; /* New BIOS used in R420 etc. */ + int ROMHeaderStart; /* Start of the ROM Info Table */ + int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ + +- CARD32 MemCntl; +- CARD32 BusCntl; ++ uint32_t MemCntl; ++ uint32_t BusCntl; + unsigned long MMIOSize; /* MMIO region physical address */ + unsigned long FbMapSize; /* Size of frame buffer, in bytes */ + unsigned long FbSecureSize; /* Size of secured fb area at end of +@@ -448,9 +482,9 @@ typedef struct { + /* Computed values for Radeon */ + int pitch; + int datatype; +- CARD32 dp_gui_master_cntl; +- CARD32 dp_gui_master_cntl_clip; +- CARD32 trans_color; ++ uint32_t dp_gui_master_cntl; ++ uint32_t dp_gui_master_cntl_clip; ++ uint32_t trans_color; + + /* Saved values for ScreenToScreenCopy */ + int xdir; +@@ -476,7 +510,7 @@ typedef struct { + #endif + /* Saved values for DashedTwoPointLine */ + int dashLen; +- CARD32 dashPattern; ++ uint32_t dashPattern; + int dash_fg; + int dash_bg; + +@@ -487,7 +521,7 @@ typedef struct { + DGAFunctionRec DGAFuncs; + + RADEONFBLayout CurrentLayout; +- CARD32 dst_pitch_offset; ++ uint32_t dst_pitch_offset; + #ifdef XF86DRI + Bool noBackBuffer; + Bool directRenderingEnabled; +@@ -502,14 +536,14 @@ typedef struct { + RADEONConfigPrivPtr pVisualConfigsPriv; + Bool (*DRICloseScreen)(int, ScreenPtr); + +- drm_handle_t fbHandle; ++ drm_handle_t fbHandle; + + drmSize registerSize; +- drm_handle_t registerHandle; ++ drm_handle_t registerHandle; + + RADEONCardType cardType; /* Current card is a PCI card */ + drmSize pciSize; +- drm_handle_t pciMemHandle; ++ drm_handle_t pciMemHandle; + unsigned char *PCI; /* Map */ + + Bool depthMoves; /* Enable depth moves -- slow! */ +@@ -522,12 +556,12 @@ typedef struct { + + int pciAperSize; + drmSize gartSize; +- drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ ++ drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ + unsigned long gartOffset; + unsigned char *AGP; /* Map */ + int agpMode; + +- CARD32 pciCommand; ++ uint32_t pciCommand; + + Bool CPRuns; /* CP is running */ + Bool CPInUse; /* CP has been used by X server */ +@@ -539,20 +573,20 @@ typedef struct { + + /* CP ring buffer data */ + unsigned long ringStart; /* Offset into GART space */ +- drm_handle_t ringHandle; /* Handle from drmAddMap */ ++ drm_handle_t ringHandle; /* Handle from drmAddMap */ + drmSize ringMapSize; /* Size of map */ + int ringSize; /* Size of ring (in MB) */ + drmAddress ring; /* Map */ + int ringSizeLog2QW; + + unsigned long ringReadOffset; /* Offset into GART space */ +- drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ ++ drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ + drmSize ringReadMapSize; /* Size of map */ + drmAddress ringReadPtr; /* Map */ + + /* CP vertex/indirect buffer data */ + unsigned long bufStart; /* Offset into GART space */ +- drm_handle_t bufHandle; /* Handle from drmAddMap */ ++ drm_handle_t bufHandle; /* Handle from drmAddMap */ + drmSize bufMapSize; /* Size of map */ + int bufSize; /* Size of buffers (in MB) */ + drmAddress buf; /* Map */ +@@ -561,7 +595,7 @@ typedef struct { + + /* CP GART Texture data */ + unsigned long gartTexStart; /* Offset into GART space */ +- drm_handle_t gartTexHandle; /* Handle from drmAddMap */ ++ drm_handle_t gartTexHandle; /* Handle from drmAddMap */ + drmSize gartTexMapSize; /* Size of map */ + int gartTexSize; /* Size of GART tex space (in MB) */ + drmAddress gartTex; /* Map */ +@@ -591,12 +625,12 @@ typedef struct { + int log2TexGran; + + int pciGartSize; +- CARD32 pciGartOffset; ++ uint32_t pciGartOffset; + void *pciGartBackup; + #ifdef USE_XAA +- CARD32 frontPitchOffset; +- CARD32 backPitchOffset; +- CARD32 depthPitchOffset; ++ uint32_t frontPitchOffset; ++ uint32_t backPitchOffset; ++ uint32_t depthPitchOffset; + + /* offscreen memory management */ + int backLines; +@@ -606,15 +640,15 @@ typedef struct { + #endif + + /* Saved scissor values */ +- CARD32 sc_left; +- CARD32 sc_right; +- CARD32 sc_top; +- CARD32 sc_bottom; ++ uint32_t sc_left; ++ uint32_t sc_right; ++ uint32_t sc_top; ++ uint32_t sc_bottom; + +- CARD32 re_top_left; +- CARD32 re_width_height; ++ uint32_t re_top_left; ++ uint32_t re_width_height; + +- CARD32 aux_sc_cntl; ++ uint32_t aux_sc_cntl; + + int irq; + +@@ -639,22 +673,22 @@ typedef struct { + int RageTheatreCompositePort; + int RageTheatreSVideoPort; + int tunerType; +- char* RageTheatreMicrocPath; +- char* RageTheatreMicrocType; +- Bool MM_TABLE_valid; ++ char* RageTheatreMicrocPath; ++ char* RageTheatreMicrocType; ++ Bool MM_TABLE_valid; + struct { +- CARD8 table_revision; +- CARD8 table_size; +- CARD8 tuner_type; +- CARD8 audio_chip; +- CARD8 product_id; +- CARD8 tuner_voltage_teletext_fm; +- CARD8 i2s_config; /* configuration of the sound chip */ +- CARD8 video_decoder_type; +- CARD8 video_decoder_host_config; +- CARD8 input[5]; +- } MM_TABLE; +- CARD16 video_decoder_type; ++ uint8_t table_revision; ++ uint8_t table_size; ++ uint8_t tuner_type; ++ uint8_t audio_chip; ++ uint8_t product_id; ++ uint8_t tuner_voltage_teletext_fm; ++ uint8_t i2s_config; /* configuration of the sound chip */ ++ uint8_t video_decoder_type; ++ uint8_t video_decoder_host_config; ++ uint8_t input[5]; ++ } MM_TABLE; ++ uint16_t video_decoder_type; + int overlay_scaler_buffer_width; + int ecp_div; + +@@ -686,15 +720,15 @@ typedef struct { + DisplayModePtr currentMode, savedCurrentMode; + + /* special handlings for DELL triple-head server */ +- Bool IsDellServer; ++ Bool IsDellServer; + +- Bool VGAAccess; ++ Bool VGAAccess; + +- int MaxSurfaceWidth; +- int MaxLines; ++ int MaxSurfaceWidth; ++ int MaxLines; + +- CARD32 tv_dac_adj; +- CARD32 tv_dac_enable_mask; ++ uint32_t tv_dac_adj; ++ uint32_t tv_dac_enable_mask; + + Bool want_vblank_interrupts; + RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; +@@ -736,6 +770,9 @@ typedef struct { Bool r600_shadow_fb; void *fb_shadow; @@ -2905,7 +3386,7 @@ index aba3c0f..feff48f 100644 } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -745,152 +772,208 @@ do { \ +@@ -745,152 +782,207 @@ do { \ info->fifo_slots -= entries; \ } while (0) @@ -2940,8 +3421,8 @@ index aba3c0f..feff48f 100644 +extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, + DisplayModePtr adjusted_mode); +extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); -+extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch); -+extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch); ++extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); ++extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); +extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); +extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); +extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); @@ -2956,20 +3437,20 @@ index aba3c0f..feff48f 100644 +extern void RADEONEngineInit(ScrnInfoPtr pScrn); +extern void RADEONEngineReset(ScrnInfoPtr pScrn); +extern void RADEONEngineRestore(ScrnInfoPtr pScrn); -+extern CARD8 *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, -+ unsigned int w, CARD32 dstPitchOff, -+ CARD32 *bufPitch, int x, int *y, ++extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, ++ unsigned int w, uint32_t dstPitchOff, ++ uint32_t *bufPitch, int x, int *y, + unsigned int *h, unsigned int *hpass); +extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, + unsigned int bpp, -+ CARD8 *dst, CARD8 *src, ++ uint8_t *dst, uint8_t *src, + unsigned int hpass, + unsigned int dstPitch, + unsigned int srcPitch); -+extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap); -+extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, -+ CARD32 pitch, int cpp, -+ CARD32 *dstPitchOffset, int *x, int *y); ++extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); ++extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, ++ uint32_t pitch, int cpp, ++ uint32_t *dstPitchOffset, int *x, int *y); +extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); +extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); #ifdef XF86DRI @@ -3030,10 +3511,10 @@ index aba3c0f..feff48f 100644 +extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); +extern void RADEONBlank(ScrnInfoPtr pScrn); +extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, -+ CARD32 *chosen_dot_clock_freq, -+ CARD32 *chosen_feedback_div, -+ CARD32 *chosen_reference_div, -+ CARD32 *chosen_post_div, int flags); ++ uint32_t *chosen_dot_clock_freq, ++ uint32_t *chosen_feedback_div, ++ uint32_t *chosen_reference_div, ++ uint32_t *chosen_post_div, int flags); +extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, + DisplayModePtr pMode); +extern void RADEONUnblank(ScrnInfoPtr pScrn); @@ -3153,8 +3634,8 @@ index aba3c0f..feff48f 100644 +extern int RADEONMinBits(int val); +extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); +extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); -+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data); -+extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); ++extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); ++extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); +extern void RADEONPllErrataAfterData(RADEONInfoPtr info); +extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); +extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); @@ -3178,14 +3659,14 @@ index aba3c0f..feff48f 100644 +extern Bool RADEONDrawInitCP(ScreenPtr pScreen); +extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); +extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, -+ CARD32 src_pitch_offset, -+ CARD32 dst_pitch_offset, -+ CARD32 datatype, int rop, ++ uint32_t src_pitch_offset, ++ uint32_t dst_pitch_offset, ++ uint32_t datatype, int rop, + Pixel planemask); +extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, -+ CARD32 src_pitch_offset, -+ CARD32 dst_pitch_offset, -+ CARD32 datatype, int rop, ++ uint32_t src_pitch_offset, ++ uint32_t dst_pitch_offset, ++ uint32_t datatype, int rop, + Pixel planemask); +#endif @@ -3222,9 +3703,9 @@ index aba3c0f..feff48f 100644 -radeon_crtc_load_lut(xf86CrtcPtr crtc); +#if defined(XF86DRI) && defined(USE_EXA) +/* radeon_exa.c */ -+extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type); ++extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); +extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, -+ CARD32 *pitch_offset); ++ uint32_t *pitch_offset); +extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); +#endif @@ -3235,7 +3716,6 @@ index aba3c0f..feff48f 100644 +/* radeon_output.c */ +extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); +extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); -+extern void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output); +extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); +extern void RADEONInitConnector(xf86OutputPtr output); +extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); @@ -3248,7 +3728,7 @@ index aba3c0f..feff48f 100644 extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, xf86OutputPtr output); extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, -@@ -901,47 +984,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save +@@ -901,47 +993,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save DisplayModePtr mode, xf86OutputPtr output); extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary); @@ -3304,7 +3784,7 @@ index aba3c0f..feff48f 100644 #define RADEONCP_START(pScrn, info) \ do { \ -@@ -998,11 +1052,18 @@ do { \ +@@ -998,11 +1061,18 @@ do { \ info->needCacheFlush = FALSE; \ } \ RADEON_WAIT_UNTIL_IDLE(); \ @@ -3328,7 +3808,37 @@ index aba3c0f..feff48f 100644 info->CPInUse = TRUE; \ } \ } while (0) -@@ -1130,15 +1191,27 @@ do { \ +@@ -1020,7 +1090,7 @@ do { \ + + #define RADEON_VERBOSE 0 + +-#define RING_LOCALS CARD32 *__head = NULL; int __expected; int __count = 0 ++#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 + + #define BEGIN_RING(n) do { \ + if (RADEON_VERBOSE) { \ +@@ -1038,7 +1108,7 @@ do { \ + if (!info->indirectBuffer) { \ + info->indirectBuffer = RADEONCPGetBuffer(pScrn); \ + info->indirectStart = 0; \ +- } else if (info->indirectBuffer->used + (n) * (int)sizeof(CARD32) > \ ++ } else if (info->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ + info->indirectBuffer->total) { \ + RADEONCPFlushIndirect(pScrn, 1); \ + } \ +@@ -1065,9 +1135,9 @@ do { \ + "ADVANCE_RING() start: %d used: %d count: %d\n", \ + info->indirectStart, \ + info->indirectBuffer->used, \ +- __count * (int)sizeof(CARD32)); \ ++ __count * (int)sizeof(uint32_t)); \ + } \ +- info->indirectBuffer->used += __count * (int)sizeof(CARD32); \ ++ info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ + } while (0) + + #define OUT_RING(x) do { \ +@@ -1130,15 +1200,27 @@ do { \ #define RADEON_PURGE_CACHE() \ do { \ BEGIN_RING(2); \ @@ -3361,7 +3871,7 @@ index aba3c0f..feff48f 100644 #endif /* XF86DRI */ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 8b2f167..9e7ea7a 100644 +index 8b2f167..92777c6 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -158,17 +158,32 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) @@ -3408,16 +3918,69 @@ index 8b2f167..9e7ea7a 100644 } } -@@ -355,7 +370,52 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -177,10 +192,10 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 clock_cntl_index; +- CARD32 mclk_cntl; +- CARD32 rbbm_soft_reset; +- CARD32 host_path_cntl; ++ uint32_t clock_cntl_index; ++ uint32_t mclk_cntl; ++ uint32_t rbbm_soft_reset; ++ uint32_t host_path_cntl; + + /* The following RBBM_SOFT_RESET sequence can help un-wedge + * an R300 after the command processor got stuck. +@@ -195,7 +210,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + INREG(RADEON_RBBM_SOFT_RESET); +- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) ++ OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) + ~(RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | +@@ -217,7 +232,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + * ASIC-version dependent, so we force all blocks on for now + */ + if (info->HasCRTC2) { +- CARD32 tmp; ++ uint32_t tmp; + + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) | +@@ -251,7 +266,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); + + if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { +- CARD32 tmp; ++ uint32_t tmp; + + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | + RADEON_SOFT_RESET_CP | +@@ -270,7 +285,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + INREG(RADEON_RBBM_SOFT_RESET); +- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) ++ OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) + ~(RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | +@@ -355,7 +370,54 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->CurrentLayout.pixel_code, info->CurrentLayout.bitsPerPixel); - OUTREG(RADEON_RB3D_CNTL, 0); + if ((info->ChipFamily == CHIP_FAMILY_RV410) || + (info->ChipFamily == CHIP_FAMILY_R420) || ++ (info->ChipFamily == CHIP_FAMILY_RS600) || + (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740) || + (info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480) || + IS_R500_3D) { + uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); + if (info->num_gb_pipes == 0) { @@ -3441,7 +4004,7 @@ index 8b2f167..9e7ea7a 100644 + } + + if (IS_R300_3D | IS_R500_3D) { -+ CARD32 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); ++ uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); + + switch(info->num_gb_pipes) { + case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; @@ -3462,7 +4025,7 @@ index 8b2f167..9e7ea7a 100644 RADEONEngineReset(pScrn); -@@ -390,8 +450,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -390,8 +452,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->sc_bottom = RADEON_DEFAULT_SC_BOTTOM_MAX; info->re_top_left = 0x00000000; @@ -3477,14 +4040,154 @@ index 8b2f167..9e7ea7a 100644 info->aux_sc_cntl = 0x00000000; #endif +@@ -617,11 +683,11 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) + * about tiling etc. + */ + void +-RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, +- CARD32 *dstPitchOff, int *x, int *y) ++RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, uint32_t pitch, int cpp, ++ uint32_t *dstPitchOff, int *x, int *y) + { + RADEONInfoPtr info = RADEONPTR( pScrn ); +- CARD32 dstOffs = dst - (CARD8*)info->FB + info->fbLocation; ++ uint32_t dstOffs = dst - (uint8_t*)info->FB + info->fbLocation; + + *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10; + *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch; +@@ -632,21 +698,21 @@ RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, + * framebuffer. Returns the address where the data can be written to and sets + * the dstPitch and hpass variables as required. + */ +-CARD8* ++uint8_t* + RADEONHostDataBlit( + ScrnInfoPtr pScrn, + unsigned int cpp, + unsigned int w, +- CARD32 dstPitchOff, +- CARD32 *bufPitch, ++ uint32_t dstPitchOff, ++ uint32_t *bufPitch, + int x, + int *y, + unsigned int *h, + unsigned int *hpass + ){ + RADEONInfoPtr info = RADEONPTR( pScrn ); +- CARD32 format, dwords; +- CARD8 *ret; ++ uint32_t format, dwords; ++ uint8_t *ret; + RING_LOCALS; + + if ( *h == 0 ) +@@ -719,7 +785,7 @@ RADEONHostDataBlit( + OUT_RING( *hpass << 16 | (*bufPitch / cpp) ); + OUT_RING( dwords ); + +- ret = ( CARD8* )&__head[__count]; ++ ret = ( uint8_t* )&__head[__count]; + + __count += dwords; + ADVANCE_RING(); +@@ -730,7 +796,7 @@ RADEONHostDataBlit( + return ret; + } + +-void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap) ++void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) + { + switch(swap) { + case RADEON_HOST_DATA_SWAP_HDW: +@@ -785,8 +851,8 @@ void + RADEONHostDataBlitCopyPass( + ScrnInfoPtr pScrn, + unsigned int cpp, +- CARD8 *dst, +- CARD8 *src, ++ uint8_t *dst, ++ uint8_t *src, + unsigned int hpass, + unsigned int dstPitch, + unsigned int srcPitch +@@ -1075,7 +1141,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) + /* Reserve space for textures */ + info->textureOffset = ((info->FbMapSize - info->textureSize + + RADEON_BUFFER_ALIGN) & +- ~(CARD32)RADEON_BUFFER_ALIGN); ++ ~(uint32_t)RADEON_BUFFER_ALIGN); + } + + /* Reserve space for the shared depth +@@ -1083,7 +1149,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) + */ + info->depthOffset = ((info->textureOffset - depthSize + + RADEON_BUFFER_ALIGN) & +- ~(CARD32)RADEON_BUFFER_ALIGN); ++ ~(uint32_t)RADEON_BUFFER_ALIGN); + + /* Reserve space for the shared back buffer */ + if (info->noBackBuffer) { +@@ -1091,7 +1157,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) + } else { + info->backOffset = ((info->depthOffset - bufferSize + + RADEON_BUFFER_ALIGN) & +- ~(CARD32)RADEON_BUFFER_ALIGN); ++ ~(uint32_t)RADEON_BUFFER_ALIGN); + } + + info->backY = info->backOffset / width_bytes; diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c -index e3b37c1..bda15ff 100644 +index e3b37c1..3c0b8a0 100644 --- a/src/radeon_accelfuncs.c +++ b/src/radeon_accelfuncs.c -@@ -1302,15 +1302,16 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) - a->CPUToScreenTextureDstFormats = RADEONDstFormats; +@@ -284,7 +284,7 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, + unsigned char *pattern) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 pat = *(CARD32 *)(pointer)pattern; ++ uint32_t pat = *(uint32_t *)(pointer)pattern; + ACCEL_PREAMBLE(); - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + /* Save for determining whether or not to draw last pixel */ +@@ -333,7 +333,7 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, + int fg) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 dp_gui_master_cntl = info->dp_gui_master_cntl_clip; ++ uint32_t dp_gui_master_cntl = info->dp_gui_master_cntl_clip; + ACCEL_PREAMBLE(); + + dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK; +@@ -548,8 +548,8 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, + OUT_ACCEL_REG(RADEON_BRUSH_DATA0, patternx); + OUT_ACCEL_REG(RADEON_BRUSH_DATA1, patterny); + #else +- OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(CARD32 *)(pointer)&pattern[0]); +- OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(CARD32 *)(pointer)&pattern[4]); ++ OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(uint32_t *)(pointer)&pattern[0]); ++ OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(uint32_t *)(pointer)&pattern[4]); + #endif + + FINISH_ACCEL(); +@@ -829,10 +829,10 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn, + { + RADEONInfoPtr info = RADEONPTR(pScrn); + #ifdef ACCEL_MMIO +- CARD32 *p = (pointer)info->scratch_buffer[bufno]; ++ uint32_t *p = (pointer)info->scratch_buffer[bufno]; + int i; + int left = info->scanline_words; +- volatile CARD32 *d; ++ volatile uint32_t *d; + ACCEL_PREAMBLE(); + + if (info->scanline_direct) return; +@@ -1302,15 +1302,16 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) + a->CPUToScreenTextureDstFormats = RADEONDstFormats; + + if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " - "unsupported on Radeon 9500/9700 and newer.\n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XAA Render acceleration " @@ -3502,7 +4205,7 @@ index e3b37c1..bda15ff 100644 a->SetupForCPUToScreenTexture2 = diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index 88c220b..b17b53c 100644 +index 88c220b..fb7d002 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -35,6 +35,8 @@ @@ -3514,6 +4217,26 @@ index 88c220b..b17b53c 100644 #include "xorg-server.h" /* only for testing now */ +@@ -275,8 +277,8 @@ rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, + + Bool + rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, +- CARD8 *contentRev, +- CARD8 *formatRev, ++ uint8_t *contentRev, ++ uint8_t *formatRev, + unsigned short *size) + { + if (!hdr) +@@ -454,7 +456,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, + } + if (fb_base && fb_size && size) { + /* 4k align */ +- fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0); ++ fb_size = (fb_size & ~(uint32_t)0xfff) + ((fb_size & 0xfff) ? 1 : 0); + if ((fb_base + fb_size) > (start + size)) { + xf86DrvMsg(handle->scrnIndex, X_WARNING, + "%s: FW FB scratch area %i (size: %i)" @@ -517,25 +519,52 @@ rhdAtomASICInit(atomBiosHandlePtr handle) return FALSE; } @@ -3582,6 +4305,95 @@ index 88c220b..b17b53c 100644 } # endif +@@ -658,7 +687,7 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, + AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD32 *val = &data->val; ++ uint32_t *val = &data->val; + //RHDFUNC(handle); + + atomDataPtr = handle->atomDataPtr; +@@ -683,7 +712,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, + AtomBiosRequestID func, AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD32 *val = &data->val; ++ uint32_t *val = &data->val; + int idx = *val; + + atomDataPtr = handle->atomDataPtr; +@@ -778,7 +807,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) + } + + static unsigned char* +-rhdAtomLvdsDDC(atomBiosHandlePtr handle, CARD32 offset, unsigned char *record) ++rhdAtomLvdsDDC(atomBiosHandlePtr handle, uint32_t offset, unsigned char *record) + { + unsigned char *EDIDBlock; + +@@ -848,7 +877,7 @@ rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, + AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; ++ uint8_t crev, frev; + DisplayModePtr last = NULL; + DisplayModePtr new = NULL; + DisplayModePtr first = NULL; +@@ -938,7 +967,7 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, + AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; ++ uint8_t crev, frev; + unsigned long offset; + + //RHDFUNC(handle); +@@ -1002,8 +1031,8 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, + AtomBiosRequestID func, AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; +- CARD32 *val = &data->val; ++ uint8_t crev, frev; ++ uint32_t *val = &data->val; + + //RHDFUNC(handle); + +@@ -1112,8 +1141,8 @@ rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, + AtomBiosRequestID func, AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; +- CARD32 *val = &data->val; ++ uint8_t crev, frev; ++ uint32_t *val = &data->val; + + //RHDFUNC(handle); + +@@ -1169,8 +1198,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, + AtomBiosRequestID func, AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; +- CARD32 *val = &data->val; ++ uint8_t crev, frev; ++ uint32_t *val = &data->val; + unsigned short size; + + //RHDFUNC(handle); +@@ -1209,8 +1238,8 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, + AtomBiosRequestID func, AtomBiosArgPtr data) + { + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; +- CARD32 *val = &data->val; ++ uint8_t crev, frev; ++ uint32_t *val = &data->val; + + //RHDFUNC(handle); + @@ -1399,7 +1428,7 @@ const int object_connector_convert[] = CONNECTOR_NONE, CONNECTOR_NONE, @@ -3591,7 +4403,28 @@ index 88c220b..b17b53c 100644 }; static void -@@ -1499,6 +1528,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1434,13 +1463,13 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle, + } + + static RADEONI2CBusRec +-RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id) ++RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) + { + RADEONInfoPtr info = RADEONPTR (pScrn); + atomDataTablesPtr atomDataPtr; + ATOM_GPIO_I2C_ASSIGMENT gpio; + RADEONI2CBusRec i2c; +- CARD8 crev, frev; ++ uint8_t crev, frev; + + memset(&i2c, 0, sizeof(RADEONI2CBusRec)); + i2c.valid = FALSE; +@@ -1495,10 +1524,11 @@ Bool + RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR (pScrn); +- CARD8 crev, frev; ++ uint8_t crev, frev; unsigned short size; atomDataTablesPtr atomDataPtr; ATOM_CONNECTOR_OBJECT_TABLE *con_obj; @@ -3608,7 +4441,16 @@ index 88c220b..b17b53c 100644 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) ((char *)&atomDataPtr->Object_Header->sHeader + atomDataPtr->Object_Header->usConnectorObjectTableOffset); -@@ -1527,10 +1557,34 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1515,7 +1545,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + for (i = 0; i < con_obj->ucNumberOfObjects; i++) { + ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; + ATOM_COMMON_RECORD_HEADER *Record; +- CARD8 obj_id, num, obj_type; ++ uint8_t obj_id, num, obj_type; + int record_base; + + obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; +@@ -1527,18 +1557,42 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) ((char *)&atomDataPtr->Object_Header->sHeader + con_obj->asObjects[i].usSrcDstTableOffset); @@ -3620,7 +4462,7 @@ index 88c220b..b17b53c 100644 + + if ((info->ChipFamily == CHIP_FAMILY_RS780) && + (obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { -+ CARD32 slot_config, ct; ++ uint32_t slot_config, ct; + + igp_obj = info->atomBIOS->atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2; + @@ -3646,7 +4488,8 @@ index 88c220b..b17b53c 100644 info->BiosConnector[i].devices = 0; for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) { -@@ -1538,7 +1592,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +- CARD8 sobj_id; ++ uint8_t sobj_id; sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id); @@ -3703,7 +4546,7 @@ index 88c220b..b17b53c 100644 (ATOM_I2C_RECORD *)Record, &ddc_line); info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); -@@ -1708,6 +1776,22 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ +@@ -1708,12 +1776,28 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ return TRUE; } @@ -3726,7 +4569,14 @@ index 88c220b..b17b53c 100644 Bool RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) { -@@ -1745,12 +1829,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR (pScrn); + atomDataTablesPtr atomDataPtr; +- CARD8 crev, frev; ++ uint8_t crev, frev; + int i, j; + + atomDataPtr = info->atomBIOS->atomDataPtr; +@@ -1745,13 +1829,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) info->BiosConnector[i].valid = TRUE; info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; @@ -3738,16 +4588,24 @@ index 88c220b..b17b53c 100644 - info->BiosConnector[i].devices = (1 << i); + info->BiosConnector[i].devices = (1 << i); info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType; ++ ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE) { ++ info->BiosConnector[i].valid = FALSE; ++ continue; ++ } ++ info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; -@@ -1759,14 +1838,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + /* don't assign a gpio for tv */ +@@ -1759,14 +1844,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) (i == ATOM_DEVICE_TV2_INDEX) || (i == ATOM_DEVICE_CV_INDEX)) info->BiosConnector[i].ddc_i2c.valid = FALSE; - else if ((i == ATOM_DEVICE_DFP3_INDEX) && info->IsIGP) { - /* DDIA port uses non-standard gpio entry */ - if (info->BiosConnector[ATOM_DEVICE_DFP2_INDEX].valid) -+ else if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ else if ((info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { + /* IGP DFP ports use non-standard gpio entries */ + if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX)) @@ -3761,7 +4619,7 @@ index 88c220b..b17b53c 100644 } else info->BiosConnector[i].ddc_i2c = RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); -@@ -1774,16 +1854,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1774,16 +1861,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) if (i == ATOM_DEVICE_DFP1_INDEX) info->BiosConnector[i].TMDSType = TMDS_INT; else if (i == ATOM_DEVICE_DFP2_INDEX) { @@ -3771,7 +4629,8 @@ index 88c220b..b17b53c 100644 - info->BiosConnector[i].TMDSType = TMDS_EXT; - } else if (i == ATOM_DEVICE_DFP3_INDEX) { - if (info->IsIGP) -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) info->BiosConnector[i].TMDSType = TMDS_DDIA; else @@ -3784,7 +4643,7 @@ index 88c220b..b17b53c 100644 info->BiosConnector[i].TMDSType = TMDS_NONE; /* Always set the connector type to VGA for CRT1/CRT2. if they are -@@ -1816,6 +1894,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1816,6 +1902,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) } else { info->BiosConnector[i].hpd_mask = 0; } @@ -3794,7 +4653,7 @@ index 88c220b..b17b53c 100644 } /* CRTs/DFPs may share a port */ -@@ -1859,689 +1940,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1859,689 +1948,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) return TRUE; } @@ -4484,7 +5343,19 @@ index 88c220b..b17b53c 100644 # ifdef ATOM_BIOS_PARSER static AtomBiosResult rhdAtomExec (atomBiosHandlePtr handle, -@@ -2673,7 +2071,7 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) +@@ -2566,9 +1972,9 @@ rhdAtomExec (atomBiosHandlePtr handle, + __func__); + return ATOM_FAILED; + } +- *dataSpace = (CARD8*)info->FB + handle->fbBase; ++ *dataSpace = (uint8_t*)info->FB + handle->fbBase; + } else +- *dataSpace = (CARD8*)handle->scratchBase; ++ *dataSpace = (uint8_t*)handle->scratchBase; + } + ret = ParseTableWrapper(pspace, idx, handle, + handle->BIOSBase, +@@ -2673,7 +2079,7 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) usleep(delay); @@ -4493,7 +5364,7 @@ index 88c220b..b17b53c 100644 } UINT32 -@@ -2686,7 +2084,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx) +@@ -2686,7 +2092,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx) CAILFUNC(CAIL); ret = INREG(idx << 2); @@ -4502,7 +5373,7 @@ index 88c220b..b17b53c 100644 return ret; } -@@ -2699,7 +2097,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) +@@ -2699,7 +2105,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) CAILFUNC(CAIL); OUTREG(idx << 2,data); @@ -4511,29 +5382,43 @@ index 88c220b..b17b53c 100644 } UINT32 -@@ -2714,10 +2112,10 @@ CailReadFBData(VOID* CAIL, UINT32 idx) +@@ -2712,12 +2118,12 @@ CailReadFBData(VOID* CAIL, UINT32 idx) + CAILFUNC(CAIL); + if (((atomBiosHandlePtr)CAIL)->fbBase) { - CARD8 *FBBase = (CARD8*)info->FB; - ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); +- CARD8 *FBBase = (CARD8*)info->FB; +- ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); - DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); ++ uint8_t *FBBase = (uint8_t*)info->FB; ++ ret = *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); + /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { - ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); +- ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); - DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); ++ ret = *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); + /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ } else { xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); -@@ -2731,7 +2129,7 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) +@@ -2731,13 +2137,13 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) { CAILFUNC(CAIL); - DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data)); + /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));*/ if (((atomBiosHandlePtr)CAIL)->fbBase) { - CARD8 *FBBase = (CARD8*) +- CARD8 *FBBase = (CARD8*) ++ uint8_t *FBBase = (uint8_t*) RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB; -@@ -2752,7 +2150,7 @@ CailReadMC(VOID *CAIL, ULONG Address) +- *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; ++ *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; + } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { +- *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; ++ *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; + } else + xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, + "%s: no fbbase set\n",__func__); +@@ -2752,7 +2158,7 @@ CailReadMC(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = INMC(pScrn, Address); @@ -4542,7 +5427,7 @@ index 88c220b..b17b53c 100644 return ret; } -@@ -2762,7 +2160,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) +@@ -2762,7 +2168,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); @@ -4551,7 +5436,24 @@ index 88c220b..b17b53c 100644 OUTMC(pScrn, Address, data); } -@@ -2808,7 +2206,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) +@@ -2793,13 +2199,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) + + switch (size) { + case 8: +- *(CARD8*)ret = pciReadByte(tag,idx << 2); ++ *(uint8_t*)ret = pciReadByte(tag,idx << 2); + break; + case 16: +- *(CARD16*)ret = pciReadWord(tag,idx << 2); ++ *(uint16_t*)ret = pciReadWord(tag,idx << 2); + break; + case 32: +- *(CARD32*)ret = pciReadLong(tag,idx << 2); ++ *(uint32_t*)ret = pciReadLong(tag,idx << 2); + break; + default: + xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, +@@ -2808,7 +2214,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) return; break; } @@ -4560,7 +5462,7 @@ index 88c220b..b17b53c 100644 } -@@ -2818,7 +2216,7 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) +@@ -2818,16 +2224,16 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; CAILFUNC(CAIL); @@ -4568,8 +5470,20 @@ index 88c220b..b17b53c 100644 + /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));*/ switch (size) { case 8: - pciWriteByte(tag,idx << 2,*(CARD8*)src); -@@ -2846,7 +2244,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) +- pciWriteByte(tag,idx << 2,*(CARD8*)src); ++ pciWriteByte(tag,idx << 2,*(uint8_t*)src); + break; + case 16: +- pciWriteWord(tag,idx << 2,*(CARD16*)src); ++ pciWriteWord(tag,idx << 2,*(uint16_t*)src); + break; + case 32: +- pciWriteLong(tag,idx << 2,*(CARD32*)src); ++ pciWriteLong(tag,idx << 2,*(uint32_t*)src); + break; + default: + xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, +@@ -2846,7 +2252,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = RADEONINPLL(pScrn, Address); @@ -4578,7 +5492,7 @@ index 88c220b..b17b53c 100644 return ret; } -@@ -2856,7 +2254,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) +@@ -2856,7 +2262,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); @@ -4588,9 +5502,18 @@ index 88c220b..b17b53c 100644 } diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h -index 9cb279e..955f2e4 100644 +index 9cb279e..b4a19aa 100644 --- a/src/radeon_atombios.h +++ b/src/radeon_atombios.h +@@ -98,7 +98,7 @@ typedef struct AtomFb { + + typedef union AtomBiosArg + { +- CARD32 val; ++ uint32_t val; + struct rhdConnectorInfo *connectorInfo; + unsigned char* EDIDBlock; + atomBiosHandlePtr atomhandle; @@ -116,6 +116,12 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn); extern Bool RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn); @@ -4604,6 +5527,15 @@ index 9cb279e..955f2e4 100644 extern Bool RADEONGetATOMTVInfo(xf86OutputPtr output); +@@ -236,7 +242,7 @@ typedef struct _atomBiosHandle { + atomDataTablesPtr atomDataPtr; + unsigned int cmd_offset; + pointer *scratchBase; +- CARD32 fbBase; ++ uint32_t fbBase; + #if XSERVER_LIBPCIACCESS + struct pci_device *device; + #else diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c index 259366c..3e7ae01 100644 --- a/src/radeon_atomwrapper.c @@ -4618,7 +5550,7 @@ index 259366c..3e7ae01 100644 #define INT32 INT32 #include "CD_Common_Types.h" diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 8e6bd8d..6be3528 100644 +index 8e6bd8d..fa09aae 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -75,7 +75,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) @@ -4631,7 +5563,7 @@ index 8e6bd8d..6be3528 100644 #else info->VBIOS = xalloc(RADEON_VBIOS_SIZE); #endif -@@ -216,6 +217,54 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -216,6 +217,55 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) return FALSE; } @@ -4639,17 +5571,18 @@ index 8e6bd8d..6be3528 100644 +{ + RADEONInfoPtr info = RADEONPTR (pScrn); + -+ /* most XPRESS chips seem to specify DDC_CRT2 for their -+ * VGA DDC port, however DDC never seems to work on that -+ * port. Some have reported success on DDC_MONID, so -+ * lets see what happens with that. ++ /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the ++ * MONID gpio, but use different pins. ++ * CRT2_DDC uses the standard pinout, MONID_DDC uses ++ * something else. + */ -+ if (info->ChipFamily == CHIP_FAMILY_RS400 && ++ if ((info->ChipFamily == CHIP_FAMILY_RS400 || ++ info->ChipFamily == CHIP_FAMILY_RS480) && + info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && + info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { + info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); + } -+ ++ + /* XPRESS desktop chips seem to have a proprietary connector listed for + * DVI-D, try and do the right thing here. + */ @@ -4686,7 +5619,7 @@ index 8e6bd8d..6be3528 100644 static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); -@@ -297,28 +346,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -297,28 +347,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) else info->BiosConnector[i].TMDSType = TMDS_INT; @@ -4716,7 +5649,16 @@ index 8e6bd8d..6be3528 100644 } } else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); -@@ -620,6 +649,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -541,7 +571,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR (pScrn); + RADEONPLLPtr pll = &info->pll; +- CARD16 pll_info_block; ++ uint16_t pll_info_block; + + if (!info->VBIOS) { + return FALSE; +@@ -620,6 +650,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) if (!info->VBIOS) return FALSE; @@ -4726,7 +5668,7 @@ index 8e6bd8d..6be3528 100644 if (info->IsAtomBios) { /* not implemented yet */ return FALSE; -@@ -628,7 +660,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -628,7 +661,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); if (offset) { rev = RADEON_BIOS8(offset + 0x3); @@ -4749,7 +5691,7 @@ index 8e6bd8d..6be3528 100644 bg = RADEON_BIOS8(offset + 0xc) & 0xf; dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20); -@@ -656,6 +702,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -656,6 +703,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj; return TRUE; @@ -4764,19 +5706,189 @@ index 8e6bd8d..6be3528 100644 } } } +@@ -793,16 +848,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) + + memcpy(EDID, (char*)(info->VBIOS + tmp), 256); + +- radeon_output->DotClock = (*(CARD16*)(EDID+54)) * 10; +- radeon_output->PanelXRes = (*(CARD8*)(EDID+56)) + ((*(CARD8*)(EDID+58))>>4)*256; +- radeon_output->HBlank = (*(CARD8*)(EDID+57)) + ((*(CARD8*)(EDID+58)) & 0xf)*256; +- radeon_output->HOverPlus = (*(CARD8*)(EDID+62)) + ((*(CARD8*)(EDID+65)>>6)*256); +- radeon_output->HSyncWidth = (*(CARD8*)(EDID+63)) + (((*(CARD8*)(EDID+65)>>4) & 3)*256); +- radeon_output->PanelYRes = (*(CARD8*)(EDID+59)) + ((*(CARD8*)(EDID+61))>>4)*256; +- radeon_output->VBlank = ((*(CARD8*)(EDID+60)) + ((*(CARD8*)(EDID+61)) & 0xf)*256); +- radeon_output->VOverPlus = (((*(CARD8*)(EDID+64))>>4) + (((*(CARD8*)(EDID+65)>>2) & 3)*16)); +- radeon_output->VSyncWidth = (((*(CARD8*)(EDID+64)) & 0xf) + ((*(CARD8*)(EDID+65)) & 3)*256); +- radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(CARD8*)(EDID+71);*/ ++ radeon_output->DotClock = (*(uint16_t*)(EDID+54)) * 10; ++ radeon_output->PanelXRes = (*(uint8_t*)(EDID+56)) + ((*(uint8_t*)(EDID+58))>>4)*256; ++ radeon_output->HBlank = (*(uint8_t*)(EDID+57)) + ((*(uint8_t*)(EDID+58)) & 0xf)*256; ++ radeon_output->HOverPlus = (*(uint8_t*)(EDID+62)) + ((*(uint8_t*)(EDID+65)>>6)*256); ++ radeon_output->HSyncWidth = (*(uint8_t*)(EDID+63)) + (((*(uint8_t*)(EDID+65)>>4) & 3)*256); ++ radeon_output->PanelYRes = (*(uint8_t*)(EDID+59)) + ((*(uint8_t*)(EDID+61))>>4)*256; ++ radeon_output->VBlank = ((*(uint8_t*)(EDID+60)) + ((*(uint8_t*)(EDID+61)) & 0xf)*256); ++ radeon_output->VOverPlus = (((*(uint8_t*)(EDID+64))>>4) + (((*(uint8_t*)(EDID+65)>>2) & 3)*16)); ++ radeon_output->VSyncWidth = (((*(uint8_t*)(EDID+64)) & 0xf) + ((*(uint8_t*)(EDID+65)) & 3)*256); ++ radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(uint8_t*)(EDID+71);*/ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); + } + return TRUE; +@@ -813,7 +868,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- CARD32 tmp, maxfreq; ++ uint32_t tmp, maxfreq; + int i, n; + + if (!info->VBIOS) return FALSE; +@@ -934,7 +989,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) + unsigned char *RADEONMMIO = info->MMIO; + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int offset, index, id; +- CARD32 val, reg, andmask, ormask; ++ uint32_t val, reg, andmask, ormask; + + if (!info->VBIOS) return FALSE; + +@@ -1044,11 +1099,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) + #define RADEON_PLL_WAIT_DLL_READY_MASK 4 + #define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 + +-static CARD16 +-RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, CARD16 offset) ++static uint16_t ++RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) + { + RADEONInfoPtr info = RADEONPTR (pScrn); +- CARD8 revision = RADEON_BIOS8(offset - 1); ++ uint8_t revision = RADEON_BIOS8(offset - 1); + + if (revision > 0x10) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +@@ -1069,7 +1124,7 @@ Bool + RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR (pScrn); +- CARD8 val; ++ uint8_t val; + + if (!info->VBIOS) { + return FALSE; +@@ -1163,14 +1218,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) + } + + static void +-RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) ++RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) + { + RADEONInfoPtr info = RADEONPTR (pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD16 offset = table_offset; +- CARD16 value, flag, index, count; +- CARD32 andmask, ormask, val, channel_complete_mask; +- CARD8 command; ++ uint16_t offset = table_offset; ++ uint16_t value, flag, index, count; ++ uint32_t andmask, ormask, val, channel_complete_mask; ++ uint8_t command; + + if (offset == 0) + return; +@@ -1271,14 +1326,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) + } + + static void +-RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) ++RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) + { + RADEONInfoPtr info = RADEONPTR (pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD16 offset = table_offset; +- CARD16 count; +- CARD32 ormask, val, channel_complete_mask; +- CARD8 index; ++ uint16_t offset = table_offset; ++ uint16_t count; ++ uint32_t ormask, val, channel_complete_mask; ++ uint8_t index; + + if (offset == 0) + return; +@@ -1315,7 +1370,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) + val = (val & RADEON_SDRAM_MODE_MASK) | ormask; + OUTREG(RADEON_MM_DATA, val); + +- ormask = (CARD32)index << 24; ++ ormask = (uint32_t)index << 24; + + ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", + RADEON_B3MEM_RESET_MASK, (unsigned)ormask); +@@ -1330,13 +1385,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) + } + + static void +-RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) ++RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) + { + RADEONInfoPtr info = RADEONPTR (pScrn); +- CARD16 offset = table_offset; +- CARD8 index, shift; +- CARD32 andmask, ormask, val, clk_pwrmgt_cntl; +- CARD16 count; ++ uint16_t offset = table_offset; ++ uint8_t index, shift; ++ uint32_t andmask, ormask, val, clk_pwrmgt_cntl; ++ uint16_t count; + + if (offset == 0) + return; +@@ -1398,11 +1453,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) + offset++; + + andmask = +- (((CARD32)RADEON_BIOS8(offset)) << shift) | +- ~((CARD32)0xff << shift); ++ (((uint32_t)RADEON_BIOS8(offset)) << shift) | ++ ~((uint32_t)0xff << shift); + offset++; + +- ormask = ((CARD32)RADEON_BIOS8(offset)) << shift; ++ ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; + offset++; + + ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index 420f5d8..de1d109 100644 +index 420f5d8..3459002 100644 --- a/src/radeon_chipinfo_gen.h +++ b/src/radeon_chipinfo_gen.h -@@ -106,7 +106,7 @@ RADEONCardInfo RADEONCards[] = { +@@ -98,20 +98,20 @@ RADEONCardInfo RADEONCards[] = { + { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, + { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, + { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, +- { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, +- { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, ++ { 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, + { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, + { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, + { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, - { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, -+ { 0x5974, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, - { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, +- { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, ++ { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, +- { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, +- { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5A61, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, ++ { 0x5A62, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, + { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, + { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, + { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, @@ -201,9 +201,9 @@ RADEONCardInfo RADEONCards[] = { { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, @@ -4790,7 +5902,17 @@ index 420f5d8..de1d109 100644 { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, -@@ -276,4 +276,23 @@ RADEONCardInfo RADEONCards[] = { +@@ -235,6 +235,9 @@ RADEONCardInfo RADEONCards[] = { + { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, + { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, + { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, ++ { 0x793F, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, ++ { 0x7941, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, ++ { 0x7942, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, + { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, + { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, + { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, +@@ -276,4 +279,23 @@ RADEONCardInfo RADEONCards[] = { { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, @@ -4815,7 +5937,7 @@ index 420f5d8..de1d109 100644 + { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, }; diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index e6890be..b668823 100644 +index e6890be..b60e7e8 100644 --- a/src/radeon_chipset_gen.h +++ b/src/radeon_chipset_gen.h @@ -201,9 +201,9 @@ static SymTabRec RADEONChipsets[] = { @@ -4831,7 +5953,17 @@ index e6890be..b668823 100644 { PCI_CHIP_R580_7240, "ATI Radeon X1950" }, { PCI_CHIP_R580_7243, "ATI Radeon X1900" }, { PCI_CHIP_R580_7244, "ATI Radeon X1950" }, -@@ -250,13 +250,13 @@ static SymTabRec RADEONChipsets[] = { +@@ -235,6 +235,9 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, + { PCI_CHIP_RS690_791E, "ATI Radeon X1200" }, + { PCI_CHIP_RS690_791F, "ATI Radeon X1200" }, ++ { PCI_CHIP_RS600_793F, "ATI Radeon X1200" }, ++ { PCI_CHIP_RS600_7941, "ATI Radeon X1200" }, ++ { PCI_CHIP_RS600_7942, "ATI Radeon X1200" }, + { PCI_CHIP_RS740_796C, "ATI RS740" }, + { PCI_CHIP_RS740_796D, "ATI RS740M" }, + { PCI_CHIP_RS740_796E, "ATI RS740" }, +@@ -250,13 +253,13 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV610_94C0, "ATI RV610" }, { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, @@ -4847,7 +5979,7 @@ index e6890be..b668823 100644 { PCI_CHIP_RV610_94CC, "ATI RV610" }, { PCI_CHIP_RV670_9500, "ATI RV670" }, { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" }, -@@ -267,14 +267,33 @@ static SymTabRec RADEONChipsets[] = { +@@ -267,14 +270,33 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV630_9580, "ATI RV630" }, { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, @@ -4886,7 +6018,7 @@ index e6890be..b668823 100644 { -1, NULL } }; diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index 0250aef..9a450f9 100644 +index 0250aef..b1dd6e8 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -55,53 +55,49 @@ @@ -4894,7 +6026,7 @@ index 0250aef..9a450f9 100644 { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 gb_tile_config; -+ CARD32 gb_tile_config, su_reg_dest, vap_cntl; ++ uint32_t gb_tile_config, su_reg_dest, vap_cntl; ACCEL_PREAMBLE(); info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; @@ -5397,12 +6529,14 @@ index 0250aef..9a450f9 100644 OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); -@@ -205,12 +590,13 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -205,12 +590,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | (8191 << R300_SCISSOR_Y_SHIFT))); - if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) { -+ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690) || ++ if (IS_R300_VARIANT || ++ (info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { /* clip has offset 1440 */ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | @@ -5414,7 +6548,7 @@ index 0250aef..9a450f9 100644 } else { OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | (0 << R300_CLIP_Y_SHIFT))); -@@ -239,6 +625,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -239,6 +627,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | R200_VAP_VF_MAX_VTX_NUM); FINISH_ACCEL(); @@ -5434,7 +6568,7 @@ index 0250aef..9a450f9 100644 } else { BEGIN_ACCEL(2); if ((info->ChipFamily == CHIP_FAMILY_RADEON) || -@@ -252,20 +651,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -252,20 +653,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) RADEON_VTX_ST1_NONPARAMETRIC | RADEON_TEX1_W_ROUTING_USE_W0); FINISH_ACCEL(); @@ -5469,7 +6603,7 @@ index 0250aef..9a450f9 100644 diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index 3524b75..6a9a76d 100644 +index 3524b75..b1e978c 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -57,12 +57,7 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, @@ -5507,7 +6641,7 @@ index 3524b75..6a9a76d 100644 } static Bool -@@ -103,6 +106,10 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -103,10 +106,14 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, static void radeon_crtc_mode_prepare(xf86CrtcPtr crtc) { @@ -5518,6 +6652,70 @@ index 3524b75..6a9a76d 100644 radeon_crtc_dpms(crtc, DPMSModeOff); } +-static CARD32 RADEONDiv(CARD64 n, CARD32 d) ++static uint32_t RADEONDiv(CARD64 n, uint32_t d) + { + return (n + (d / 2)) / d; + } +@@ -114,22 +121,22 @@ static CARD32 RADEONDiv(CARD64 n, CARD32 d) + void + RADEONComputePLL(RADEONPLLPtr pll, + unsigned long freq, +- CARD32 *chosen_dot_clock_freq, +- CARD32 *chosen_feedback_div, +- CARD32 *chosen_reference_div, +- CARD32 *chosen_post_div, ++ uint32_t *chosen_dot_clock_freq, ++ uint32_t *chosen_feedback_div, ++ uint32_t *chosen_reference_div, ++ uint32_t *chosen_post_div, + int flags) + { +- CARD32 min_ref_div = pll->min_ref_div; +- CARD32 max_ref_div = pll->max_ref_div; +- CARD32 best_vco = pll->best_vco; +- CARD32 best_post_div = 1; +- CARD32 best_ref_div = 1; +- CARD32 best_feedback_div = 1; +- CARD32 best_freq = 1; +- CARD32 best_error = 0xffffffff; +- CARD32 best_vco_diff = 1; +- CARD32 post_div; ++ uint32_t min_ref_div = pll->min_ref_div; ++ uint32_t max_ref_div = pll->max_ref_div; ++ uint32_t best_vco = pll->best_vco; ++ uint32_t best_post_div = 1; ++ uint32_t best_ref_div = 1; ++ uint32_t best_feedback_div = 1; ++ uint32_t best_freq = 1; ++ uint32_t best_error = 0xffffffff; ++ uint32_t best_vco_diff = 1; ++ uint32_t post_div; + + freq = freq * 1000; + +@@ -139,8 +146,8 @@ RADEONComputePLL(RADEONPLLPtr pll, + min_ref_div = max_ref_div = pll->reference_div; + + for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { +- CARD32 ref_div; +- CARD32 vco = (freq / 10000) * post_div; ++ uint32_t ref_div; ++ uint32_t vco = (freq / 10000) * post_div; + + if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) + continue; +@@ -159,8 +166,8 @@ RADEONComputePLL(RADEONPLLPtr pll, + continue; + + for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { +- CARD32 feedback_div, current_freq, error, vco_diff; +- CARD32 pll_in = pll->reference_freq / ref_div; ++ uint32_t feedback_div, current_freq, error, vco_diff; ++ uint32_t pll_in = pll->reference_freq / ref_div; + + if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) + continue; @@ -190,8 +197,10 @@ RADEONComputePLL(RADEONPLLPtr pll, best_vco_diff = vco_diff; } @@ -5542,7 +6740,7 @@ index 3524b75..6a9a76d 100644 } void -@@ -275,6 +288,10 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) +@@ -275,12 +288,16 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); } @@ -5553,6 +6751,14 @@ index 3524b75..6a9a76d 100644 } + static void +-radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, +- CARD16 *blue, int size) ++radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, ++ uint16_t *blue, int size) + { + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + ScrnInfoPtr pScrn = crtc->scrn; @@ -533,11 +550,12 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) { @@ -5644,7 +6850,7 @@ index 3524b75..6a9a76d 100644 + return changed; +} diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c -index 0f7e668..42f9a85 100644 +index 0f7e668..c4472db 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -92,6 +92,7 @@ @@ -5674,7 +6880,7 @@ index 0f7e668..42f9a85 100644 + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(crtc->scrn); + unsigned char *RADEONMMIO = info->MMIO; -+ CARD32 tmp; ++ uint32_t tmp; + + tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); + @@ -5727,15 +6933,48 @@ index 0f7e668..42f9a85 100644 } else { if (crtc_id == 0) { OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK -@@ -274,7 +299,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) +@@ -230,8 +255,8 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) + { + ScrnInfoPtr pScrn = crtc->scrn; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ uint32_t *pixels = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset); + int pixel, i; + CURSOR_SWAPPING_DECL_MMIO + +@@ -272,9 +297,9 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) + { + ScrnInfoPtr pScrn = crtc->scrn; + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; +- RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONInfoPtr info = RADEONPTR(pScrn); CURSOR_SWAPPING_DECL_MMIO - CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); -+ CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset); ++ uint32_t *d = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset); RADEONCTRACE(("RADEONLoadCursorARGB\n")); +@@ -300,13 +325,13 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + int width_bytes; + int height; + int size_bytes; +- CARD32 cursor_offset = 0; ++ uint32_t cursor_offset = 0; + int c; + +- size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; +- width = pScrn->displayWidth; +- width_bytes = width * (pScrn->bitsPerPixel / 8); +- height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; ++ size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; ++ width = pScrn->displayWidth; ++ width_bytes = width * (pScrn->bitsPerPixel / 8); ++ height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; + + #ifdef USE_XAA + if (!info->useEXA) { @@ -346,14 +371,6 @@ Bool RADEONCursorInit(ScreenPtr pScreen) return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT, @@ -5751,6 +6990,117 @@ index 0f7e668..42f9a85 100644 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | HARDWARE_CURSOR_ARGB)); +diff --git a/src/radeon_dga.c b/src/radeon_dga.c +index ab5d278..d623fe4 100644 +--- a/src/radeon_dga.c ++++ b/src/radeon_dga.c +@@ -374,7 +374,7 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn, + /* XXX */ + if (info->useEXA) { + /* +- info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (CARD32)(~0)); ++ info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (uint32_t)(~0)); + info->exa.accel.Solid(pScrn, x, y, x+w, y+h); + info->exa.accel.DoneSolid(); + */ +@@ -383,7 +383,7 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn, + #endif /* USE_EXA */ + #ifdef USE_XAA + if (!info->useEXA) { +- (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (CARD32)(~0)); ++ (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (uint32_t)(~0)); + (*info->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h); + if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) + RADEON_MARK_SYNC(info, pScrn); +@@ -404,7 +404,7 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn, + /* XXX */ + if (info->useEXA) { + /* +- info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (CARD32)(~0)); ++ info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (uint32_t)(~0)); + info->exa.accel.Copy(pScrn, srcx, srcy, dstx, dsty, w, h); + info->exa.accel.DoneCopy(); + */ +@@ -414,7 +414,7 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn, + #ifdef USE_XAA + if (!info->useEXA) { + (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, +- GXcopy, (CARD32)(~0), -1); ++ GXcopy, (uint32_t)(~0), -1); + (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy, + dstx, dsty, w, h); + if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) +@@ -433,7 +433,7 @@ static void RADEON_BlitTransRect(ScrnInfoPtr pScrn, + + info->XAAForceTransBlit = TRUE; + (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, +- GXcopy, (CARD32)(~0), color); ++ GXcopy, (uint32_t)(~0), color); + + info->XAAForceTransBlit = FALSE; + +diff --git a/src/radeon_dri.c b/src/radeon_dri.c +index ac8d03c..9fdc5b6 100644 +--- a/src/radeon_dri.c ++++ b/src/radeon_dri.c +@@ -451,17 +451,17 @@ static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType, + + /* 16-bit depth buffer functions */ + #define WRITE_DEPTH16(_x, _y, d) \ +- *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) ++ *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) + + #define READ_DEPTH16(d, _x, _y) \ +- (d) = *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) ++ (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) + + /* 32-bit depth buffer (stencil and depth simultaneously) functions */ + #define WRITE_DEPTHSTENCIL32(_x, _y, d) \ +- *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) ++ *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) + + #define READ_DEPTHSTENCIL32(d, _x, _y) \ +- (d) = *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) ++ (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) + + /* Screen to screen copy of data in the depth buffer */ + static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, +@@ -646,7 +646,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, + info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; + + (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy, +- (CARD32)(-1), -1); ++ (uint32_t)(-1), -1); + + for (; nbox-- ; pbox++) { + int xa = pbox->x1; +@@ -724,7 +724,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) + unsigned int device = drmAgpDeviceId(info->drmFD); + /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with + pcie-agp rialto bridge chip - use the one from bridge which must match */ +- CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; ++ uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; + Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); + unsigned int defaultMode; + MessageType from; +@@ -1903,7 +1903,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) + + #ifdef USE_EXA + if (info->useEXA) { +- CARD32 src_pitch_offset, dst_pitch_offset, datatype; ++ uint32_t src_pitch_offset, dst_pitch_offset, datatype; + + RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset); + dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10); +@@ -1924,7 +1924,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) + info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; + (*info->accel->SetupForScreenToScreenCopy)(pScrn, + 1, 1, GXcopy, +- (CARD32)(-1), -1); ++ (uint32_t)(-1), -1); + } + #endif + diff --git a/src/radeon_dri.h b/src/radeon_dri.h index 3b54626..67892a6 100644 --- a/src/radeon_dri.h @@ -5765,7 +7115,7 @@ index 3b54626..67892a6 100644 #define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 5cf8d51..2701f57 100644 +index 5cf8d51..83e0f85 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -126,35 +126,6 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); @@ -5804,7 +7154,7 @@ index 5cf8d51..2701f57 100644 static const OptionInfoRec RADEONOptions[] = { { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, -@@ -219,18 +190,17 @@ static const OptionInfoRec RADEONOptions[] = { +@@ -219,24 +190,23 @@ static const OptionInfoRec RADEONOptions[] = { { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, @@ -5827,6 +7177,44 @@ index 5cf8d51..2701f57 100644 } struct RADEONInt10Save { +- CARD32 MEM_CNTL; +- CARD32 MEMSIZE; +- CARD32 MPP_TB_CONFIG; ++ uint32_t MEM_CNTL; ++ uint32_t MEMSIZE; ++ uint32_t MPP_TB_CONFIG; + }; + + static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); +@@ -253,7 +223,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, + stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; + *size = stride; + +- return ((CARD8 *)info->FB + pScrn->fbOffset + ++ return ((uint8_t *)info->FB + pScrn->fbOffset + + row * stride + offset); + } + static Bool +@@ -292,8 +262,8 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 CardTmp; +- static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; ++ uint32_t CardTmp; ++ static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; + + if (!IS_AVIVO_VARIANT) { + /* Save the values and zap MEM_CNTL */ +@@ -319,7 +289,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + struct RADEONInt10Save *pSave = ptr; +- CARD32 CardTmp; ++ uint32_t CardTmp; + + /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ + if (!pSave || !pSave->MEM_CNTL) @@ -387,6 +357,12 @@ static void RADEONFreeRec(ScrnInfoPtr pScrn) static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) { @@ -5897,22 +7285,62 @@ index 5cf8d51..2701f57 100644 info->LinearAddr, info->FbMapSize, PCI_DEV_MAP_FLAG_WRITABLE | -@@ -585,10 +572,10 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) +@@ -540,7 +527,7 @@ void RADEONPllErrataAfterData(RADEONInfoPtr info) + * may not be correct. + */ + if (info->ChipErrata & CHIP_ERRATA_R300_CG) { +- CARD32 save, tmp; ++ uint32_t save, tmp; + + save = INREG(RADEON_CLOCK_CNTL_INDEX); + tmp = save & ~(0x3f | RADEON_PLL_WR_EN); +@@ -555,7 +542,7 @@ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) + { + RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 data; +- CARD32 data; ++ uint32_t data; + OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); + RADEONPllErrataAfterIndex(info); +@@ -566,7 +553,7 @@ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) + } + + /* Write PLL information */ +-void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) ++void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +@@ -583,12 +570,15 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 data; +- - if (info->ChipFamily == CHIP_FAMILY_RS690) - { - OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); - data = INREG(RS690_MC_DATA); ++ uint32_t data; ++ + if ((info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { + OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); + data = INREG(RS690_MC_DATA); ++ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { ++ OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); ++ data = INREG(RS600_MC_DATA); } else if (IS_AVIVO_VARIANT) { OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); (void)INREG(AVIVO_MC_INDEX); -@@ -614,12 +601,12 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) +@@ -609,17 +599,22 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) + } + + /* Write MC information */ +-void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) ++void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) + { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -5928,10 +7356,15 @@ index 5cf8d51..2701f57 100644 + RS690_MC_INDEX_WR_EN)); + OUTREG(RS690_MC_DATA, data); + OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); ++ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { ++ OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | ++ RS600_MC_INDEX_WR_EN)); ++ OUTREG(RS600_MC_DATA, data); ++ OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); } else if (IS_AVIVO_VARIANT) { OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); (void)INREG(AVIVO_MC_INDEX); -@@ -636,7 +623,7 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) +@@ -636,7 +631,7 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) } } @@ -5940,30 +7373,40 @@ index 5cf8d51..2701f57 100644 { RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -648,7 +635,8 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) +@@ -648,7 +643,13 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) return TRUE; else return FALSE; - } else if (info->ChipFamily == CHIP_FAMILY_RS690) { ++ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { ++ if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) ++ return TRUE; ++ else ++ return FALSE; + } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) return TRUE; else -@@ -663,7 +651,7 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) +@@ -663,7 +664,7 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) #define LOC_FB 0x1 #define LOC_AGP 0x2 -void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi) -+static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi) ++static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; -@@ -681,12 +669,13 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, +@@ -681,12 +682,18 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, if (mask & LOC_AGP) OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); (void)INMC(pScrn, RV515_MC_AGP_LOCATION); - } else if (info->ChipFamily == CHIP_FAMILY_RS690) { ++ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { ++ if (mask & LOC_FB) ++ OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); ++ /* if (mask & LOC_AGP) ++ OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/ + } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { if (mask & LOC_FB) @@ -5975,45 +7418,176 @@ index 5cf8d51..2701f57 100644 if (mask & LOC_FB) OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); if (mask & LOC_AGP) -@@ -700,7 +689,7 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, +@@ -700,7 +707,7 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, } } -void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi) -+static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi) ++static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; -@@ -719,7 +708,8 @@ void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, +@@ -719,7 +726,15 @@ void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); *agp_loc_hi = 0; } - } else if (info->ChipFamily == CHIP_FAMILY_RS690) { ++ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { ++ if (mask & LOC_FB) ++ *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); ++ if (mask & LOC_AGP) { ++ *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); ++ *agp_loc_hi = 0; ++ } + } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { if (mask & LOC_FB) *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); if (mask & LOC_AGP) { -@@ -1259,7 +1249,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) +@@ -758,7 +773,7 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 crtc_gen_cntl; ++ uint32_t crtc_gen_cntl; + struct timeval timeout; + + crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); +@@ -781,7 +796,7 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 crtc2_gen_cntl; ++ uint32_t crtc2_gen_cntl; + struct timeval timeout; + + crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); +@@ -938,12 +953,12 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) + xtal = 2700; + } else { + if (prev_xtal == 0) { +- prev_xtal = xtal; +- tries = 0; +- goto again; ++ prev_xtal = xtal; ++ tries = 0; ++ goto again; + } else if (prev_xtal != xtal) { +- prev_xtal = 0; +- goto again; ++ prev_xtal = 0; ++ goto again; + } + } + +@@ -952,16 +967,18 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) + + /* Some sanity check based on the BIOS code .... */ + if (ref_div < 2) { +- CARD32 tmp; ++ uint32_t tmp; + tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); +- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300) +- || (info->ChipFamily == CHIP_FAMILY_RS400)) +- ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> +- R300_PPLL_REF_DIV_ACC_SHIFT; ++ if (IS_R300_VARIANT ++ || (info->ChipFamily == CHIP_FAMILY_RS300) ++ || (info->ChipFamily == CHIP_FAMILY_RS400) ++ || (info->ChipFamily == CHIP_FAMILY_RS480)) ++ ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> ++ R300_PPLL_REF_DIV_ACC_SHIFT; + else +- ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; ++ ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; + if (ref_div < 2) +- ref_div = 12; ++ ref_div = 12; + } + + /* Calculate "base" xclk straight from MPLL, though that isn't +@@ -1031,11 +1048,12 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + We'll probably need a new routine to calculate the best ref_div from BIOS + provided min_input_pll and max_input_pll + */ +- CARD32 tmp; ++ uint32_t tmp; + tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_RS300) || +- (info->ChipFamily == CHIP_FAMILY_RS400)) { ++ (info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { + pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; + } else { + pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; +@@ -1226,8 +1244,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 mem_size; +- CARD32 aper_size; ++ uint32_t mem_size; ++ uint32_t aper_size; + + radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, + &info->mc_agp_location, &info->mc_agp_location_hi); +@@ -1259,7 +1277,9 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) } #endif - if (info->ChipFamily != CHIP_FAMILY_RS690) { -+ if ((info->ChipFamily != CHIP_FAMILY_RS690) && ++ if ((info->ChipFamily != CHIP_FAMILY_RS600) && ++ (info->ChipFamily != CHIP_FAMILY_RS690) && + (info->ChipFamily != CHIP_FAMILY_RS740)) { if (info->IsIGP) info->mc_fb_location = INREG(RADEON_NB_TOM); else -@@ -1458,23 +1449,20 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -1271,7 +1291,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) + else + #endif + { +- CARD32 aper0_base; ++ uint32_t aper0_base; + + if (info->ChipFamily >= CHIP_FAMILY_R600) { + aper0_base = INREG(R600_CONFIG_F0_BASE); +@@ -1338,7 +1358,7 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 tmp; ++ uint32_t tmp; + + if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) || + (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) +@@ -1379,11 +1399,11 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) + * accessible to the CPU can vary. This function is our best shot at figuring + * it out. Returns a value in KB. + */ +-static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) ++static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 aper_size; ++ uint32_t aper_size; + unsigned char byte; + + if (info->ChipFamily >= CHIP_FAMILY_R600) +@@ -1456,25 +1476,22 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) + GDevPtr dev = pEnt->device; + unsigned char *RADEONMMIO = info->MMIO; MessageType from = X_PROBED; - CARD32 accessible, bar_size; +- CARD32 accessible, bar_size; ++ uint32_t accessible, bar_size; - if (info->ChipFamily == CHIP_FAMILY_RS690) { - pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE); - } else if (info->IsIGP) { - CARD32 tom = INREG(RADEON_NB_TOM); + if ((!IS_AVIVO_VARIANT) && info->IsIGP) { -+ CARD32 tom = INREG(RADEON_NB_TOM); ++ uint32_t tom = INREG(RADEON_NB_TOM); pScrn->videoRam = (((tom >> 16) - (tom & 0xffff) + 1) << 6); @@ -6031,7 +7605,21 @@ index 5cf8d51..2701f57 100644 /* Some production boards of m6 will return 0 if it's 8 MB */ if (pScrn->videoRam == 0) { pScrn->videoRam = 8192; -@@ -1811,6 +1799,19 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1636,6 +1653,13 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); + } + break; ++ case PCI_CHIP_RS482_5974: ++ /* RH BZ 444586 - non mobility version ++ * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ ++ if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { ++ info->IsMobility = FALSE; ++ } + default: + break; + } +@@ -1811,6 +1835,21 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) if (!xf86LoadSubModule(pScrn, "shadow")) return FALSE; } @@ -6041,6 +7629,8 @@ index 5cf8d51..2701f57 100644 + (info->ChipFamily == CHIP_FAMILY_RS200) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480) || ++ (info->ChipFamily == CHIP_FAMILY_RS600) || + (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) + info->has_tcl = FALSE; @@ -6051,7 +7641,34 @@ index 5cf8d51..2701f57 100644 return TRUE; } -@@ -2163,7 +2164,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -1939,7 +1978,7 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) + #if !defined(__powerpc__) && !defined(__sparc__) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 fp2_gen_ctl_save = 0; ++ uint32_t fp2_gen_ctl_save = 0; + + if (xf86LoadSubModule(pScrn, "int10")) { + /* The VGA BIOS on the RV100/QY cannot be read when the digital output +@@ -1996,13 +2035,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) + info->Chipset == PCI_CHIP_RC410_5A61 || + info->Chipset == PCI_CHIP_RC410_5A62 || + info->Chipset == PCI_CHIP_RS485_5975 || ++ info->ChipFamily == CHIP_FAMILY_RS600 || + info->ChipFamily >= CHIP_FAMILY_R600) { +- if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Direct rendering for RN50/RC410/RS485/R600 forced on -- " ++ "Direct rendering for RN50/RC410/RS485/RS600/R600 forced on -- " + "This is NOT officially supported at the hardware level " + "and may cause instability or lockups\n"); +- } else { ++ } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Direct rendering not officially supported on RN50/RC410/R600\n"); + return FALSE; +@@ -2163,7 +2203,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) } else { from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, &info->allowPageFlip) ? X_CONFIG : X_DEFAULT; @@ -6067,7 +7684,7 @@ index 5cf8d51..2701f57 100644 } #else from = X_DEFAULT; -@@ -2221,7 +2229,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2221,7 +2268,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) info->pKernelDRMVersion->version_minor, info->pKernelDRMVersion->version_patchlevel); info->allowColorTiling = FALSE; @@ -6076,7 +7693,20 @@ index 5cf8d51..2701f57 100644 } #endif /* XF86DRI */ -@@ -2366,7 +2374,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) +@@ -2236,9 +2283,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) + static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD16 mm_table; +- CARD16 bios_header; +- CARD16 pll_info_block; ++ uint16_t mm_table; ++ uint16_t bios_header; ++ uint16_t pll_info_block; + #ifdef XvExtension + char* microc_path = NULL; + char* microc_type = NULL; +@@ -2366,7 +2413,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) } bios_header=info->VBIOS[0x48]; @@ -6085,7 +7715,7 @@ index 5cf8d51..2701f57 100644 mm_table=info->VBIOS[bios_header+0x38]; if(mm_table==0) -@@ -2636,8 +2644,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2636,8 +2683,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; @@ -6095,7 +7725,7 @@ index 5cf8d51..2701f57 100644 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; -@@ -2689,7 +2696,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2689,7 +2735,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitWeight(pScrn)) goto fail; @@ -6104,7 +7734,7 @@ index 5cf8d51..2701f57 100644 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { if (strcmp(s, "AUTO") == 0) { info->DispPriority = 1; -@@ -2698,7 +2705,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2698,7 +2744,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } else if (strcmp(s, "HIGH") == 0) { info->DispPriority = 2; } else @@ -6113,7 +7743,7 @@ index 5cf8d51..2701f57 100644 } if (!RADEONPreInitInt10(pScrn, &pInt10)) -@@ -2739,17 +2746,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2739,17 +2785,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (crtc_max_Y > 8192) crtc_max_Y = 8192; } else { @@ -6143,7 +7773,7 @@ index 5cf8d51..2701f57 100644 } } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", -@@ -2793,14 +2805,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2793,14 +2844,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitAccel(pScrn)) goto fail; @@ -6163,7 +7793,16 @@ index 5cf8d51..2701f57 100644 if (pScrn->modes == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); goto fail; -@@ -3001,7 +3015,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) +@@ -2858,7 +2911,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int i; + int index, j; +- CARD16 lut_r[256], lut_g[256], lut_b[256]; ++ uint16_t lut_r[256], lut_g[256], lut_b[256]; + int c; + + #ifdef XF86DRI +@@ -3001,7 +3054,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) /* let the bios control the backlight */ save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; /* tell the bios not to handle mode switching */ @@ -6173,7 +7812,7 @@ index 5cf8d51..2701f57 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) { OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); -@@ -3014,7 +3029,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) +@@ -3014,7 +3068,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) /* let the bios control the backlight */ save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; /* tell the bios not to handle mode switching */ @@ -6183,7 +7822,7 @@ index 5cf8d51..2701f57 100644 /* tell the bios a driver is loaded */ save->bios_7_scratch |= RADEON_DRV_LOADED; -@@ -3032,9 +3048,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3032,9 +3087,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -6193,7 +7832,7 @@ index 5cf8d51..2701f57 100644 #ifdef RENDER int subPixelOrder = SubPixelUnknown; char* s; -@@ -3080,11 +3094,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3080,11 +3133,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONBlank(pScrn); if (info->IsMobility && !IS_AVIVO_VARIANT) { @@ -6213,7 +7852,7 @@ index 5cf8d51..2701f57 100644 } if (IS_R300_VARIANT || IS_RV100_VARIANT) -@@ -3139,12 +3158,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3139,12 +3197,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONInitMemoryMap(pScrn); /* empty the surfaces */ @@ -6234,7 +7873,7 @@ index 5cf8d51..2701f57 100644 } #ifdef XF86DRI -@@ -3340,28 +3361,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3340,28 +3400,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* xf86CrtcRotate() accesses pScrn->pScreen */ pScrn->pScreen = pScreen; @@ -6263,11 +7902,42 @@ index 5cf8d51..2701f57 100644 RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); -@@ -3760,15 +3761,15 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -3544,7 +3584,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + int timeout; +- CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; ++ uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; + + radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, + &mc_agp_loc, &mc_agp_loc_hi); +@@ -3564,7 +3604,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + + if (mc_fb_loc != restore->mc_fb_location || + mc_agp_loc != restore->mc_agp_location) { +- CARD32 tmp; ++ uint32_t tmp; + + RADEONWaitForIdleMMIO(pScrn); + +@@ -3620,8 +3660,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + */ + if (mc_fb_loc != restore->mc_fb_location || + mc_agp_loc != restore->mc_agp_location) { +- CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; +- CARD32 old_mc_status, status_idle; ++ uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; ++ uint32_t old_mc_status, status_idle; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + " Map Changed ! Applying ...\n"); +@@ -3759,16 +3799,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 fb, agp, agp_hi; +- CARD32 fb, agp, agp_hi; - int changed; ++ uint32_t fb, agp, agp_hi; + int changed = 0; if (info->IsSecondary) @@ -6283,7 +7953,7 @@ index 5cf8d51..2701f57 100644 changed = 1; if (changed) { -@@ -4039,12 +4040,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4039,12 +4079,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) } #endif @@ -6298,7 +7968,7 @@ index 5cf8d51..2701f57 100644 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); -@@ -4110,8 +4112,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4110,8 +4151,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); @@ -6307,7 +7977,7 @@ index 5cf8d51..2701f57 100644 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); -@@ -4151,57 +4151,207 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4151,57 +4190,208 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); @@ -6499,7 +8169,8 @@ index 5cf8d51..2701f57 100644 + j++; + } + -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { + j = 0; + /* save DDIA regs */ @@ -6550,7 +8221,7 @@ index 5cf8d51..2701f57 100644 // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); -@@ -4266,8 +4416,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4266,8 +4456,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); @@ -6559,7 +8230,7 @@ index 5cf8d51..2701f57 100644 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); -@@ -4306,49 +4454,199 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4306,49 +4494,200 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); @@ -6753,7 +8424,8 @@ index 5cf8d51..2701f57 100644 + } + + /* DDIA regs */ -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740)) { + j = 0; + for (i = 0x7200; i <= 0x7290; i += 4) { @@ -6761,8 +8433,8 @@ index 5cf8d51..2701f57 100644 + j++; + } + } -+ } -+ + } + + /* scalers */ + j = 0; + for (i = 0x6578; i <= 0x65e4; i += 4) { @@ -6779,10 +8451,10 @@ index 5cf8d51..2701f57 100644 + for (i = 0x66e8; i <= 0x66fc; i += 4) { + OUTREG(i, state->dxscl[j]); + j++; - } ++ } + OUTREG(0x6e30, state->dxscl[6]); + OUTREG(0x6e34, state->dxscl[7]); - ++ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); } @@ -6794,7 +8466,17 @@ index 5cf8d51..2701f57 100644 RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; struct avivo_state *state = &restore->avivo; -@@ -4471,7 +4769,7 @@ static void RADEONSave(ScrnInfoPtr pScrn) +@@ -4434,6 +4773,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) + * setup in the card at all !! + */ + vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ ++# elif defined(__linux__) ++ /* Save only mode * & fonts */ ++ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); + # else + /* Save mode * & fonts & cmap */ + vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); +@@ -4471,7 +4813,7 @@ static void RADEONSave(ScrnInfoPtr pScrn) } /* Restore the original (text) mode */ @@ -6803,7 +8485,18 @@ index 5cf8d51..2701f57 100644 { RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -@@ -4567,7 +4865,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4555,7 +4897,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) + * write VGA fonts, will find a better solution in the future + */ + vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); +-# else ++# elif defined(__linux__) ++ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); ++# else + vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); + # endif + vgaHWLock(hwp); +@@ -4567,7 +4911,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) */ if (IS_AVIVO_VARIANT) avivo_restore_vga_regs(pScrn, restore); @@ -6814,7 +8507,7 @@ index 5cf8d51..2701f57 100644 #if 0 RADEONWaitForVerticalSync(pScrn); -@@ -4885,8 +5185,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4885,8 +5231,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -6823,7 +8516,7 @@ index 5cf8d51..2701f57 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); -@@ -4907,41 +5205,34 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4907,41 +5251,34 @@ Bool RADEONEnterVT(int scrnIndex, int flags) RADEONWaitForIdleMMIO(pScrn); if (info->IsMobility && !IS_AVIVO_VARIANT) { @@ -6856,11 +8549,11 @@ index 5cf8d51..2701f57 100644 - crtc->desiredX = 0; - crtc->desiredY = 0; - } - +- - if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, - crtc->desiredX, crtc->desiredY)) - return FALSE; -- + - } + if (!xf86SetDesiredModes(pScrn)) + return FALSE; @@ -6880,7 +8573,7 @@ index 5cf8d51..2701f57 100644 } /* get the DRI back into shape after resume */ -@@ -4966,8 +5257,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4966,8 +5303,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) } #endif @@ -6889,7 +8582,7 @@ index 5cf8d51..2701f57 100644 return TRUE; } -@@ -4978,6 +5267,10 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4978,6 +5313,10 @@ void RADEONLeaveVT(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -6900,7 +8593,7 @@ index 5cf8d51..2701f57 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT\n"); -@@ -4988,8 +5281,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4988,8 +5327,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); @@ -6912,7 +8605,7 @@ index 5cf8d51..2701f57 100644 /* we need to backup the PCIE GART TABLE from fb memory */ memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize); } -@@ -5009,6 +5303,23 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5009,6 +5349,23 @@ void RADEONLeaveVT(int scrnIndex, int flags) } #endif @@ -6936,11 +8629,29 @@ index 5cf8d51..2701f57 100644 RADEONRestore(pScrn); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +@@ -5121,7 +5478,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) + static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) + { + /* It appears from r300 and rv100 may need some clocks forced-on */ +- CARD32 tmp; ++ uint32_t tmp; + + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; +@@ -5133,7 +5490,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 tmp; ++ uint32_t tmp; + switch(mode) { + case 0: /* Turn everything OFF (ForceON to everything)*/ + if ( !pRADEONEnt->HasCRTC2 ) { diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 4da4841..fa6ac0d 100644 +index 4da4841..0193a28 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c -@@ -99,10 +99,17 @@ static __inline__ int +@@ -99,17 +99,24 @@ static __inline__ int RADEONLog2(int val) { int bits; @@ -6958,8 +8669,47 @@ index 4da4841..fa6ac0d 100644 +#endif } - static __inline__ CARD32 F_TO_DW(float val) -@@ -182,7 +189,7 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset) +-static __inline__ CARD32 F_TO_DW(float val) ++static __inline__ uint32_t F_TO_DW(float val) + { + union { + float f; +- CARD32 l; ++ uint32_t l; + } tmp; + tmp.f = val; + return tmp.l; +@@ -118,7 +125,7 @@ static __inline__ CARD32 F_TO_DW(float val) + /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we + * require src and dest datatypes to be equal. + */ +-Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type) ++Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type) + { + switch (bpp) { + case 8: +@@ -152,7 +159,7 @@ static Bool RADEONPixmapIsColortiled(PixmapPtr pPix) + return FALSE; + } + +-static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset, ++static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset, + unsigned int offset, unsigned int pitch) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); +@@ -172,17 +179,17 @@ static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset, + return TRUE; + } + +-Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset) ++Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- CARD32 pitch, offset; ++ uint32_t pitch, offset; + int bpp; + + bpp = pPix->drawable.bitsPerPixel; if (bpp == 24) bpp = 8; @@ -6968,6 +8718,45 @@ index 4da4841..fa6ac0d 100644 pitch = exaGetPixmapPitch(pPix); return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); +@@ -196,9 +203,9 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 offset = exaGetPixmapOffset(pPix); ++ uint32_t offset = exaGetPixmapOffset(pPix); + int bpp, soff; +- CARD32 size, flags; ++ uint32_t size, flags; + + /* Front buffer is always set with proper swappers */ + if (offset == 0) +@@ -262,7 +269,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 offset = exaGetPixmapOffset(pPix); ++ uint32_t offset = exaGetPixmapOffset(pPix); + int soff; + + /* Front buffer is always set with proper swappers */ +@@ -293,7 +300,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) + + #define RADEON_SWITCH_TO_2D() \ + do { \ +- CARD32 wait_until = 0; \ ++ uint32_t wait_until = 0; \ + BEGIN_ACCEL(1); \ + switch (info->engineMode) { \ + case EXA_ENGINEMODE_UNKNOWN: \ +@@ -310,7 +317,7 @@ do { \ + + #define RADEON_SWITCH_TO_3D() \ + do { \ +- CARD32 wait_until = 0; \ ++ uint32_t wait_until = 0; \ + BEGIN_ACCEL(1); \ + switch (info->engineMode) { \ + case EXA_ENGINEMODE_UNKNOWN: \ @@ -395,7 +402,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) else screen_size = pScrn->virtualY * byteStride; @@ -6978,10 +8767,128 @@ index 4da4841..fa6ac0d 100644 info->exa->offScreenBase = screen_size; diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 10221c0..272ffa9 100644 +index 10221c0..13a7de5 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c -@@ -533,18 +533,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -88,7 +88,7 @@ static Bool + FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- CARD32 datatype, dst_pitch_offset; ++ uint32_t datatype, dst_pitch_offset; + ACCEL_PREAMBLE(); + + TRACE; +@@ -143,8 +143,8 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) + } + + void +-FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, CARD32 src_pitch_offset, +- CARD32 dst_pitch_offset, CARD32 datatype, int rop, ++FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, ++ uint32_t dst_pitch_offset, uint32_t datatype, int rop, + Pixel planemask) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +@@ -178,7 +178,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, + Pixel planemask) + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); +- CARD32 datatype, src_pitch_offset, dst_pitch_offset; ++ uint32_t datatype, src_pitch_offset, dst_pitch_offset; + + TRACE; + +@@ -241,12 +241,12 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + char *src, int src_pitch) + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); +- CARD8 *dst = info->FB + exaGetPixmapOffset(pDst); ++ uint8_t *dst = info->FB + exaGetPixmapOffset(pDst); + unsigned int dst_pitch = exaGetPixmapPitch(pDst); + unsigned int bpp = pDst->drawable.bitsPerPixel; + #ifdef ACCEL_CP + unsigned int hpass; +- CARD32 buf_pitch, dst_pitch_off; ++ uint32_t buf_pitch, dst_pitch_off; + #endif + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +@@ -263,7 +263,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + #ifdef ACCEL_CP + if (info->directRenderingEnabled && + RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) { +- CARD8 *buf; ++ uint8_t *buf; + int cpp = bpp / 8; + ACCEL_PREAMBLE(); + +@@ -271,7 +271,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + while ((buf = RADEONHostDataBlit(pScrn, + cpp, w, dst_pitch_off, &buf_pitch, + x, &y, (unsigned int*)&h, &hpass)) != 0) { +- RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (CARD8 *)src, ++ RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (uint8_t *)src, + hpass, buf_pitch, src_pitch); + src += hpass * src_pitch; + } +@@ -319,8 +319,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + #ifdef ACCEL_CP + /* Emit blit with arbitrary source and destination offsets and pitches */ + static void +-RADEONBlitChunk(ScrnInfoPtr pScrn, CARD32 datatype, CARD32 src_pitch_offset, +- CARD32 dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, ++RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, ++ uint32_t dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, + int w, int h) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +@@ -357,11 +357,11 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + #endif +- CARD8 *src = info->FB + exaGetPixmapOffset(pSrc); ++ uint8_t *src = info->FB + exaGetPixmapOffset(pSrc); + int src_pitch = exaGetPixmapPitch(pSrc); + int bpp = pSrc->drawable.bitsPerPixel; + #ifdef ACCEL_CP +- CARD32 datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0; ++ uint32_t datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0; + drmBufPtr scratch; + #endif + +@@ -379,7 +379,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + { + int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8; + int hpass = min(h, scratch->total/2 / scratch_pitch); +- CARD32 scratch_pitch_offset = scratch_pitch << 16 ++ uint32_t scratch_pitch_offset = scratch_pitch << 16 + | (info->gartLocation + info->bufStart + + scratch->idx * scratch->total) >> 10; + drmRadeonIndirect indirect; +@@ -406,7 +406,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + while (h) { + int oldhpass = hpass, i = 0; + +- src = (CARD8*)scratch->address + scratch_off; ++ src = (uint8_t*)scratch->address + scratch_off; + + y += oldhpass; + h -= oldhpass; +@@ -439,10 +439,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + + /* Copy out data from previous blit */ + if (wpass == scratch_pitch && wpass == dst_pitch) { +- RADEONCopySwap((CARD8*)dst, src, wpass * oldhpass, swap); ++ RADEONCopySwap((uint8_t*)dst, src, wpass * oldhpass, swap); + dst += dst_pitch * oldhpass; + } else while (oldhpass--) { +- RADEONCopySwap((CARD8*)dst, src, wpass, swap); ++ RADEONCopySwap((uint8_t*)dst, src, wpass, swap); + src += scratch_pitch; + dst += dst_pitch; + } +@@ -533,21 +533,27 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) #ifdef RENDER if (info->RenderAccel) { @@ -6993,6 +8900,11 @@ index 10221c0..272ffa9 100644 - else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS690)) { + "unsupported on R600 and newer cards.\n"); + else if (IS_R300_3D || IS_R500_3D) { ++ if ((info->ChipFamily < CHIP_FAMILY_RS400) ++#ifdef XF86DRI ++ || (info->directRenderingEnabled) ++#endif ++ ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " - "enabled for R300 type cards.\n"); + "enabled for R300/R400/R500 type cards.\n"); @@ -7001,11 +8913,19 @@ index 10221c0..272ffa9 100644 FUNC_NAME(R300PrepareComposite); info->exa->Composite = FUNC_NAME(RadeonComposite); - info->exa->DoneComposite = RadeonDoneComposite; +- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || +- (info->ChipFamily == CHIP_FAMILY_RV280) || +- (info->ChipFamily == CHIP_FAMILY_RS300) || + info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite); - } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280) || - (info->ChipFamily == CHIP_FAMILY_RS300) || -@@ -555,7 +554,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) ++ } else ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n"); ++ } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || ++ (info->ChipFamily == CHIP_FAMILY_RV280) || ++ (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " + "enabled for R200 type cards.\n"); +@@ -555,7 +561,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->exa->PrepareComposite = FUNC_NAME(R200PrepareComposite); info->exa->Composite = FUNC_NAME(RadeonComposite); @@ -7014,7 +8934,7 @@ index 10221c0..272ffa9 100644 } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R100 type cards.\n"); -@@ -563,7 +562,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -563,7 +569,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->exa->PrepareComposite = FUNC_NAME(R100PrepareComposite); info->exa->Composite = FUNC_NAME(RadeonComposite); @@ -7023,7 +8943,7 @@ index 10221c0..272ffa9 100644 } } #endif -@@ -572,11 +571,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -572,11 +578,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); info->exa->maxPitchBytes = 16320; @@ -7039,7 +8959,7 @@ index 10221c0..272ffa9 100644 RADEONEngineInit(pScrn); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 9bbccb5..54b0272 100644 +index 9bbccb5..2319e3b 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -26,6 +26,7 @@ @@ -7050,7 +8970,7 @@ index 9bbccb5..54b0272 100644 * */ -@@ -57,6 +58,13 @@ +@@ -57,11 +58,18 @@ #ifdef ONLY_ONCE static Bool is_transform[2]; static PictTransform *transform[2]; @@ -7064,7 +8984,40 @@ index 9bbccb5..54b0272 100644 struct blendinfo { Bool dst_alpha; -@@ -177,9 +185,8 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) + Bool src_alpha; +- CARD32 blend_cntl; ++ uint32_t blend_cntl; + }; + + static struct blendinfo RadeonBlendOp[] = { +@@ -95,7 +103,7 @@ static struct blendinfo RadeonBlendOp[] = { + + struct formatinfo { + int fmt; +- CARD32 card_fmt; ++ uint32_t card_fmt; + }; + + /* Note on texture formats: +@@ -134,7 +142,7 @@ static struct formatinfo R300TexFormats[] = { + + /* Common Radeon setup code */ + +-static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) ++static Bool RADEONGetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) + { + switch (pDstPicture->format) { + case PICT_a8r8g8b8: +@@ -159,7 +167,7 @@ static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) + return TRUE; + } + +-static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) ++static Bool R300GetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) + { + switch (pDstPicture->format) { + case PICT_a8r8g8b8: +@@ -177,16 +185,15 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) *dst_format = R300_COLORFORMAT_I8; break; default: @@ -7076,8 +9029,21 @@ index 9bbccb5..54b0272 100644 } return TRUE; } -@@ -221,6 +228,95 @@ union intfloat { - CARD32 i; + +-static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) ++static uint32_t RADEONGetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) + { +- CARD32 sblend, dblend; ++ uint32_t sblend, dblend; + + sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; + dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; +@@ -218,9 +225,98 @@ static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) + + union intfloat { + float f; +- CARD32 i; ++ uint32_t i; }; +/* Check if we need a software-fallback because of a repeating @@ -7110,7 +9076,7 @@ index 9bbccb5..54b0272 100644 +{ + int w = pPix->drawable.width; + int h = pPix->drawable.height; -+ CARD32 txpitch = exaGetPixmapPitch(pPix); ++ uint32_t txpitch = exaGetPixmapPitch(pPix); + + if (h > 1 && ((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch) + return FALSE; @@ -7183,8 +9149,12 @@ index 9bbccb5..54b0272 100644 if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) -@@ -261,11 +357,12 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - CARD32 txfilter, txformat, txoffset, txpitch; +@@ -258,14 +354,15 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, + int unit) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- CARD32 txfilter, txformat, txoffset, txpitch; ++ uint32_t txfilter, txformat, txoffset, txpitch; int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; + Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y)); @@ -7236,8 +9206,9 @@ index 9bbccb5..54b0272 100644 static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { +- CARD32 tmp1; + PixmapPtr pSrcPixmap, pDstPixmap; - CARD32 tmp1; ++ uint32_t tmp1; /* Check for unsupported compositing operations. */ if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) @@ -7315,6 +9286,17 @@ index 9bbccb5..54b0272 100644 if (!RADEONGetDestFormat(pDstPicture, &tmp1)) return FALSE; +@@ -390,8 +524,8 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, + PixmapPtr pDst) + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); +- CARD32 dst_format, dst_offset, dst_pitch, colorpitch; +- CARD32 pp_cntl, blendcntl, cblend, ablend; ++ uint32_t dst_format, dst_offset, dst_pitch, colorpitch; ++ uint32_t pp_cntl, blendcntl, cblend, ablend; + int pixel_shift; + ACCEL_PREAMBLE(); + @@ -400,22 +534,32 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, if (!info->XInited3D) RADEONInit3DEngine(pScrn); @@ -7379,8 +9361,12 @@ index 9bbccb5..54b0272 100644 if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) -@@ -522,17 +670,18 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - CARD32 txfilter, txformat, txoffset, txpitch; +@@ -519,20 +667,21 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, + int unit) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- CARD32 txfilter, txformat, txoffset, txpitch; ++ uint32_t txfilter, txformat, txoffset, txpitch; int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; + Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y)); @@ -7426,8 +9412,9 @@ index 9bbccb5..54b0272 100644 static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, PicturePtr pDstPicture) { +- CARD32 tmp1; + PixmapPtr pSrcPixmap, pDstPixmap; - CARD32 tmp1; ++ uint32_t tmp1; TRACE; @@ -7500,6 +9487,17 @@ index 9bbccb5..54b0272 100644 if (!RADEONGetDestFormat(pDstPicture, &tmp1)) return FALSE; +@@ -643,8 +823,8 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, + PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); +- CARD32 dst_format, dst_offset, dst_pitch; +- CARD32 pp_cntl, blendcntl, cblend, ablend, colorpitch; ++ uint32_t dst_format, dst_offset, dst_pitch; ++ uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch; + int pixel_shift; + ACCEL_PREAMBLE(); + @@ -653,10 +833,17 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, if (!info->XInited3D) RADEONInit3DEngine(pScrn); @@ -7547,12 +9545,16 @@ index 9bbccb5..54b0272 100644 OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); -@@ -744,13 +938,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -744,13 +938,26 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, #ifdef ONLY_ONCE -static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit) -+static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit, Bool is_r500) ++static Bool R300CheckCompositeTexture(PicturePtr pPict, ++ PicturePtr pDstPict, ++ int op, ++ int unit, ++ Bool is_r500) { int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; @@ -7572,7 +9574,7 @@ index 9bbccb5..54b0272 100644 RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h)); for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) -@@ -762,13 +965,24 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit) +@@ -762,13 +969,26 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit) RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); @@ -7593,13 +9595,24 @@ index 9bbccb5..54b0272 100644 + * matter. I have not, however, verified that the X server always does such + * clipping. + */ -+ if (pPict->transform != 0 && !pPict->repeat && PICT_FORMAT_A(pPict->format) == 0) -+ RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); ++ if (pPict->transform != 0 && !pPict->repeat && PICT_FORMAT_A(pPict->format) == 0) { ++ if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) ++ RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); ++ } + return TRUE; } -@@ -787,13 +1001,14 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -778,7 +998,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, + int unit) + { + RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; ++ uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; + int w = pPict->pDrawable->width; + int h = pPict->pDrawable->height; + int i, pixel_shift; +@@ -787,13 +1007,14 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, TRACE; txpitch = exaGetPixmapPitch(pPix); @@ -7615,7 +9628,7 @@ index 9bbccb5..54b0272 100644 pixel_shift = pPix->drawable.bitsPerPixel >> 4; txpitch >>= pixel_shift; txpitch -= 1; -@@ -809,24 +1024,35 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -809,24 +1030,35 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, txformat1 = R300TexFormats[i].card_fmt; @@ -7663,7 +9676,7 @@ index 9bbccb5..54b0272 100644 switch (pPict->filter) { case PictFilterNearest: -@@ -839,13 +1065,15 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -839,13 +1071,15 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } @@ -7681,7 +9694,12 @@ index 9bbccb5..54b0272 100644 FINISH_ACCEL(); if (pPict->transform != 0) { -@@ -867,8 +1095,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP +@@ -863,12 +1097,12 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, + static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, + PicturePtr pDstPicture) + { +- CARD32 tmp1; ++ uint32_t tmp1; ScreenPtr pScreen = pDstPicture->pDrawable->pScreen; PixmapPtr pSrcPixmap, pDstPixmap; ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -7692,7 +9710,7 @@ index 9bbccb5..54b0272 100644 TRACE; -@@ -876,51 +1104,64 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP +@@ -876,51 +1110,64 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); @@ -7779,26 +9797,33 @@ index 9bbccb5..54b0272 100644 + } } + -+ if (!R300CheckCompositeTexture(pMaskPicture, 1, IS_R500_3D)) ++ if (!R300CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1, IS_R500_3D)) + return FALSE; } - if (!R300CheckCompositeTexture(pSrcPicture, 0)) - return FALSE; - if (pMaskPicture != NULL && !R300CheckCompositeTexture(pMaskPicture, 1)) -+ if (!R300CheckCompositeTexture(pSrcPicture, 0, IS_R500_3D)) ++ if (!R300CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0, IS_R500_3D)) return FALSE; if (!R300GetDestFormat(pDstPicture, &tmp1)) -@@ -940,7 +1181,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - CARD32 txenable, colorpitch; - CARD32 blendcntl; +@@ -936,11 +1183,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); +- CARD32 dst_format, dst_offset, dst_pitch; +- CARD32 txenable, colorpitch; +- CARD32 blendcntl; ++ uint32_t dst_format, dst_offset, dst_pitch; ++ uint32_t txenable, colorpitch; ++ uint32_t blendcntl; int pixel_shift; - int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); ACCEL_PREAMBLE(); TRACE; -@@ -948,10 +1188,17 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -948,10 +1194,17 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, if (!info->XInited3D) RADEONInit3DEngine(pScrn); @@ -7818,7 +9843,7 @@ index 9bbccb5..54b0272 100644 dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; -@@ -965,6 +1212,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -965,6 +1218,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); @@ -7828,7 +9853,7 @@ index 9bbccb5..54b0272 100644 if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0)) return FALSE; txenable = R300_TEX_0_ENABLE; -@@ -980,28 +1230,32 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -980,28 +1236,32 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, RADEON_SWITCH_TO_3D(); /* setup the VAP */ @@ -7880,7 +9905,7 @@ index 9bbccb5..54b0272 100644 OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | -@@ -1009,35 +1263,15 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1009,35 +1269,15 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R300_SIGNED_0 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | @@ -7919,7 +9944,7 @@ index 9bbccb5..54b0272 100644 OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | (0 << R300_SKIP_DWORDS_0_SHIFT) | -@@ -1046,223 +1280,569 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1046,223 +1286,569 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | (0 << R300_SKIP_DWORDS_1_SHIFT) | (6 << R300_DST_VEC_LOC_1_SHIFT) | @@ -8108,7 +10133,7 @@ index 9bbccb5..54b0272 100644 - FINISH_ACCEL(); - } + if (IS_R300_3D) { -+ CARD32 output_fmt; ++ uint32_t output_fmt; + int src_color, src_alpha; + int mask_color, mask_alpha; @@ -8341,9 +10366,9 @@ index 9bbccb5..54b0272 100644 } else { - cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B; - ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B; -+ CARD32 output_fmt; -+ CARD32 src_color, src_alpha; -+ CARD32 mask_color, mask_alpha; ++ uint32_t output_fmt; ++ uint32_t src_color, src_alpha; ++ uint32_t mask_color, mask_alpha; + + if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) + src_color = (R500_ALU_RGB_R_SWIZ_A_0 | @@ -8678,7 +10703,7 @@ index 9bbccb5..54b0272 100644 do { \ OUT_RING_F(_dstX); \ OUT_RING_F(_dstY); \ -@@ -1272,9 +1852,17 @@ do { \ +@@ -1272,9 +1858,17 @@ do { \ OUT_RING_F(_maskY); \ } while (0) @@ -8697,7 +10722,7 @@ index 9bbccb5..54b0272 100644 do { \ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ -@@ -1284,6 +1872,14 @@ do { \ +@@ -1284,6 +1878,14 @@ do { \ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ } while (0) @@ -8712,7 +10737,7 @@ index 9bbccb5..54b0272 100644 #endif /* !ACCEL_CP */ #ifdef ONLY_ONCE -@@ -1299,11 +1895,11 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point) +@@ -1299,11 +1901,11 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point) } #endif @@ -8729,7 +10754,7 @@ index 9bbccb5..54b0272 100644 { RINFO_FROM_SCREEN(pDst->drawable.pScreen); int vtx_count; -@@ -1347,9 +1943,12 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -1347,9 +1949,12 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, transformPoint(transform[1], &maskBottomRight); } @@ -8744,7 +10769,7 @@ index 9bbccb5..54b0272 100644 BEGIN_ACCEL(1); OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); FINISH_ACCEL(); -@@ -1360,17 +1959,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -1360,17 +1965,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, BEGIN_RING(4 * vtx_count + 3); OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 4 * vtx_count + 1)); @@ -8771,7 +10796,7 @@ index 9bbccb5..54b0272 100644 else BEGIN_RING(4 * vtx_count + 2); -@@ -1382,8 +1985,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -1382,8 +1991,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, } #else /* ACCEL_CP */ @@ -8782,7 +10807,7 @@ index 9bbccb5..54b0272 100644 else BEGIN_ACCEL(1 + vtx_count * 4); -@@ -1399,24 +2002,34 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -1399,24 +2008,34 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, } #endif @@ -8833,7 +10858,7 @@ index 9bbccb5..54b0272 100644 #ifdef ACCEL_CP ADVANCE_RING(); #else -@@ -1426,14 +2039,88 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -1426,14 +2045,90 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, LEAVE_DRAW(0); } #undef VTX_OUT @@ -8909,6 +10934,8 @@ index 9bbccb5..54b0272 100644 ENTER_DRAW(0); + + if (IS_R500_3D || ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480) || ++ (info->ChipFamily == CHIP_FAMILY_RS600) || + (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740))) { + /* r500 shows corruption on small things like glyphs without a 3D idle @@ -8925,11 +10952,157 @@ index 9bbccb5..54b0272 100644 #undef ONLY_ONCE #undef FUNC_NAME +diff --git a/src/radeon_macros.h b/src/radeon_macros.h +index 7f532a8..f19bc3e 100644 +--- a/src/radeon_macros.h ++++ b/src/radeon_macros.h +@@ -67,12 +67,12 @@ + #define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) + #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) + +-#define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr))) ++#define ADDRREG(addr) ((volatile uint32_t *)(pointer)(RADEONMMIO + (addr))) + + + #define OUTREGP(addr, val, mask) \ + do { \ +- CARD32 tmp = INREG(addr); \ ++ uint32_t tmp = INREG(addr); \ + tmp &= (mask); \ + tmp |= ((val) & ~(mask)); \ + OUTREG(addr, tmp); \ +@@ -84,7 +84,7 @@ do { \ + + #define OUTPLLP(pScrn, addr, val, mask) \ + do { \ +- CARD32 tmp_ = INPLL(pScrn, addr); \ ++ uint32_t tmp_ = INPLL(pScrn, addr); \ + tmp_ &= (mask); \ + tmp_ |= ((val) & ~(mask)); \ + OUTPLL(pScrn, addr, tmp_); \ +@@ -108,7 +108,7 @@ do { \ + } \ + } while (0) + +-#define OUTPAL_NEXT_CARD32(v) \ ++#define OUTPAL_NEXT_uint32_t(v) \ + do { \ + OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ + } while (0) +@@ -148,7 +148,7 @@ do { \ + } else { \ + if (!idx) { \ + OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ +- (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \ ++ (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL); \ + } else { \ + OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ + RADEON_DAC2_PALETTE_ACC_CTL); \ +diff --git a/src/radeon_mm_i2c.c b/src/radeon_mm_i2c.c +index 0524fa9..bb45407 100644 +--- a/src/radeon_mm_i2c.c ++++ b/src/radeon_mm_i2c.c +@@ -64,9 +64,9 @@ static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv); + * I2C_NACK - an NACK was received from the slave * + * I2C_HALT - a timeout condition has occured * + ****************************************************************************/ +-static CARD8 RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) ++static uint8_t RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) + { +- CARD8 retval = 0; ++ uint8_t retval = 0; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + long counter = 0; +@@ -103,7 +103,7 @@ static void RADEON_I2C_Halt (ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD8 reg; ++ uint8_t reg; + + /* reset status flags */ + RADEONWaitForIdleMMIO(pScrn); +@@ -124,8 +124,8 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + I2CByte *ReadBuffer, int nRead) + { + int loop, status; +- CARD32 i2c_cntl_0, i2c_cntl_1; +- CARD8 reg; ++ uint32_t i2c_cntl_0, i2c_cntl_1; ++ uint8_t reg; + RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); + ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); +@@ -141,7 +141,7 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); + + /* Write the address into the buffer first */ +- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1)); ++ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); + + /* Write Value into the buffer */ + for (loop = 0; loop < nWrite; loop++) +@@ -172,7 +172,7 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); + + /* Write the address into the buffer first */ +- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1)); ++ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); + + i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | + nRead | 0x100; +@@ -209,8 +209,8 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + I2CByte *ReadBuffer, int nRead) + { + int loop, status; +- CARD32 i2c_cntl_0, i2c_cntl_1; +- CARD8 reg; ++ uint32_t i2c_cntl_0, i2c_cntl_1; ++ uint8_t reg; + RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); + ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); +@@ -226,7 +226,7 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); + + /* Write the address into the buffer first */ +- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1)); ++ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); + + /* Write Value into the buffer */ + for (loop = 0; loop < nWrite; loop++) +@@ -257,7 +257,7 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, + OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); + + /* Write the address into the buffer first */ +- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1)); ++ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); + + i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | + nRead | 0x010; diff --git a/src/radeon_output.c b/src/radeon_output.c -index 62cc5d4..907d824 100644 +index 62cc5d4..72addef 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c -@@ -178,15 +178,9 @@ static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state); +@@ -145,7 +145,7 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = + {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ + }; + +-static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = ++static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = + { + 0x00000000, /* unknown */ + 0x00000000, /* legacy */ +@@ -168,7 +168,6 @@ static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = + }; + + +-static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output); + static void RADEONUpdatePanelSize(xf86OutputPtr output); + static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output); + #define AVIVO_I2C_DISABLE 0 +@@ -178,15 +177,9 @@ static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state); extern void atombios_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); @@ -8945,7 +11118,202 @@ index 62cc5d4..907d824 100644 static void radeon_bios_output_dpms(xf86OutputPtr output, int mode); static void -@@ -239,6 +233,8 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output) +@@ -217,122 +210,99 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) + + } + +-static RADEONMonitorType +-avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output) ++static xf86MonPtr ++radeon_do_ddc(xf86OutputPtr output) + { +- RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONMonitorType MonType = MT_NONE; +- xf86MonPtr MonInfo = NULL; +- RADEONOutputPrivatePtr radeon_output = output->driver_private; +- +- if (radeon_output->pI2CBus) { +- AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE); +- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); +- AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE); +- } +- if (MonInfo) { +- if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) +- xf86OutputSetEDID(output, MonInfo); +- if (radeon_output->type == OUTPUT_LVDS) +- MonType = MT_LCD; +- else if (radeon_output->type == OUTPUT_DVI_D) +- MonType = MT_DFP; +- else if (radeon_output->type == OUTPUT_HDMI) +- MonType = MT_DFP; +- else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ +- MonType = MT_DFP; +- else +- MonType = MT_CRT; +- } else MonType = MT_NONE; +- +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); +- +- return MonType; +-} +- +-static RADEONMonitorType +-RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) +-{ +- RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONInfoPtr info = RADEONPTR(output->scrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 DDCReg; +- RADEONMonitorType MonType = MT_NONE; ++ uint32_t DDCReg; + xf86MonPtr MonInfo = NULL; + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int i, j; + +- if (!radeon_output->ddc_i2c.valid) +- return MT_NONE; ++ if (radeon_output->pI2CBus) { ++ DDCReg = radeon_output->ddc_i2c.mask_clk_reg; + +- DDCReg = radeon_output->ddc_i2c.mask_clk_reg; ++ if (IS_AVIVO_VARIANT) { ++ AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE); ++ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); ++ AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE); ++ } else if ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG)) { ++ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); ++ } else { ++ OUTREG(DDCReg, INREG(DDCReg) & ++ (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); + +- /* Read and output monitor info using DDC2 over I2C bus */ +- if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) { +- OUTREG(DDCReg, INREG(DDCReg) & +- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); ++ /* For some old monitors (like Compaq Presario FP500), we need ++ * following process to initialize/stop DDC ++ */ ++ OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); ++ for (j = 0; j < 3; j++) { ++ OUTREG(DDCReg, ++ INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); ++ usleep(13000); ++ ++ OUTREG(DDCReg, ++ INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); ++ for (i = 0; i < 10; i++) { ++ usleep(15000); ++ if (INREG(DDCReg) & RADEON_GPIO_Y_1) ++ break; ++ } ++ if (i == 10) continue; + +- /* For some old monitors (like Compaq Presario FP500), we need +- * following process to initialize/stop DDC +- */ +- OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); +- for (j = 0; j < 3; j++) { +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); +- usleep(13000); +- +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); +- for (i = 0; i < 10; i++) { + usleep(15000); +- if (INREG(DDCReg) & RADEON_GPIO_Y_1) +- break; +- } +- if (i == 10) continue; + +- usleep(15000); ++ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); ++ usleep(15000); + +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); +- usleep(15000); ++ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); ++ usleep(15000); ++ OUTREG(DDCReg, ++ INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); ++ usleep(15000); + +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); +- usleep(15000); +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); +- usleep(15000); ++ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); + +- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); ++ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); ++ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); ++ usleep(15000); ++ OUTREG(DDCReg, ++ INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); ++ for (i = 0; i < 5; i++) { ++ usleep(15000); ++ if (INREG(DDCReg) & RADEON_GPIO_Y_1) ++ break; ++ } ++ usleep(15000); ++ OUTREG(DDCReg, ++ INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); ++ usleep(15000); + +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); +- usleep(15000); +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); +- for (i = 0; i < 5; i++) { ++ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); ++ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); + usleep(15000); +- if (INREG(DDCReg) & RADEON_GPIO_Y_1) +- break; ++ if (MonInfo) break; + } +- usleep(15000); +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); +- usleep(15000); +- +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); +- usleep(15000); +- if (MonInfo) break; ++ OUTREG(DDCReg, INREG(DDCReg) & ++ ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); + } +- } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) { +- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); +- } else { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n"); +- MonType = MT_NONE; + } + +- OUTREG(DDCReg, INREG(DDCReg) & +- ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); ++ return MonInfo; ++} + ++static RADEONMonitorType ++radeon_ddc_connected(xf86OutputPtr output) ++{ ++ ScrnInfoPtr pScrn = output->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONMonitorType MonType = MT_NONE; ++ xf86MonPtr MonInfo = NULL; ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ ++ if (radeon_output->pI2CBus) ++ MonInfo = radeon_do_ddc(output); + if (MonInfo) { + if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) + xf86OutputSetEDID(output, MonInfo); +@@ -342,67 +312,21 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) MonType = MT_DFP; else if (radeon_output->type == OUTPUT_HDMI) MonType = MT_DFP; @@ -8954,25 +11322,139 @@ index 62cc5d4..907d824 100644 else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ MonType = MT_DFP; else -@@ -301,7 +297,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) - INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); - usleep(15000); + MonType = MT_CRT; +- } else MonType = MT_NONE; +- ++ } else ++ MonType = MT_NONE; ++ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); -- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); -+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); + return MonType; + } + +- +-/* Primary Head (DVI or Laptop Int. panel)*/ +-/* A ddc capable display connected on DVI port */ +-/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ +-void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) +-{ +- RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONOutputPrivatePtr radeon_output = output->driver_private; +- +- if (radeon_output->MonType == MT_UNKNOWN) { +- if (IS_AVIVO_VARIANT) { +- radeon_output->MonType = avivo_display_ddc_connected(pScrn, output); +- if (!radeon_output->MonType) { +- if (radeon_output->type == OUTPUT_LVDS) +- radeon_output->MonType = MT_LCD; +- else +- radeon_output->MonType = atombios_dac_detect(pScrn, output); +- } +- } else { +- radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output); +- if (!radeon_output->MonType) { +- if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI) +- radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output); +- if (!radeon_output->MonType) { +- if (info->IsAtomBios) +- radeon_output->MonType = atombios_dac_detect(pScrn, output); +- else +- radeon_output->MonType = legacy_dac_detect(pScrn, output); +- } +- } +- } +- } +- +- /* update panel info for RMX */ +- if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) +- RADEONUpdatePanelSize(output); +- +- /* panel is probably busted or not connected */ +- if ((radeon_output->MonType == MT_LCD) && +- ((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0))) +- radeon_output->MonType = MT_NONE; +- +- if (output->MonInfo) { +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n", +- output->name); +- xf86PrintEDID( output->MonInfo ); +- } +-} +- + #ifndef __powerpc__ + + static RADEONMonitorType +@@ -449,42 +373,58 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn) + + #endif /* __powerpc__ */ + +-static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output) ++static void ++RADEONConnectorFindMonitor(xf86OutputPtr output) + { +- RADEONInfoPtr info = RADEONPTR(output->scrn); ++ ScrnInfoPtr pScrn = output->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- RADEONMonitorType MonType = MT_NONE; - OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); - OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -@@ -324,7 +320,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) - if (MonInfo) break; +- if (radeon_output->type == OUTPUT_LVDS) { +- if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS, TRUE)) +- MonType = MT_LCD; +- else ++ if (radeon_output->MonType == MT_UNKNOWN) { ++ radeon_output->MonType = radeon_ddc_connected(output); ++ if (!radeon_output->MonType) { ++ if (radeon_output->type == OUTPUT_LVDS) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS, TRUE)) ++ radeon_output->MonType = MT_LCD; ++ else + #if defined(__powerpc__) +- MonType = MT_LCD; ++ radeon_output->MonType = MT_LCD; + #else +- MonType = RADEONDetectLidStatus(pScrn); ++ radeon_output->MonType = RADEONDetectLidStatus(pScrn); + #endif +- } /*else if (radeon_output->type == OUTPUT_DVI) { +- if (radeon_output->TMDSType == TMDS_INT) { +- if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) +- MonType = MT_DFP; +- } else if (radeon_output->TMDSType == TMDS_EXT) { +- if (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) +- MonType = MT_DFP; ++ } else { ++ if (info->IsAtomBios) ++ radeon_output->MonType = atombios_dac_detect(pScrn, output); ++ else ++ radeon_output->MonType = legacy_dac_detect(pScrn, output); ++ } } - } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) { -- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); -+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n"); - MonType = MT_NONE; -@@ -485,6 +481,10 @@ static void +- }*/ ++ } + +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Detected non-DDC Monitor Type: %d\n", MonType); ++ /* update panel info for RMX */ ++ if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) ++ RADEONUpdatePanelSize(output); + +- return MonType; ++ /* panel is probably busted or not connected */ ++ if ((radeon_output->MonType == MT_LCD) && ++ ((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0))) ++ radeon_output->MonType = MT_NONE; + ++ if (output->MonInfo) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n", ++ output->name); ++ xf86PrintEDID( output->MonInfo ); ++ } + } + + static void radeon_dpms(xf86OutputPtr output, int mode) { RADEONInfoPtr info = RADEONPTR(output->scrn); @@ -8983,7 +11465,7 @@ index 62cc5d4..907d824 100644 if (IS_AVIVO_VARIANT) { atombios_output_dpms(output, mode); -@@ -493,6 +493,11 @@ radeon_dpms(xf86OutputPtr output, int mode) +@@ -493,6 +433,11 @@ radeon_dpms(xf86OutputPtr output, int mode) } radeon_bios_output_dpms(output, mode); @@ -8995,7 +11477,7 @@ index 62cc5d4..907d824 100644 } static void -@@ -673,15 +678,15 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock) +@@ -673,15 +618,15 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock) if (info->IsAtomBios) { if (lock) { @@ -9015,7 +11497,50 @@ index 62cc5d4..907d824 100644 } } if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -1168,6 +1173,7 @@ static Atom tmds_pll_atom; +@@ -1032,7 +977,7 @@ radeon_detect(xf86OutputPtr output) + + radeon_output->MonType = MT_UNKNOWN; + radeon_bios_output_connected(output, FALSE); +- RADEONConnectorFindMonitor(pScrn, output); ++ RADEONConnectorFindMonitor(output); + + /* nothing connected, light up some defaults so the server comes up */ + if (radeon_output->MonType == MT_NONE && +@@ -1101,24 +1046,6 @@ radeon_detect(xf86OutputPtr output) + break; + } + +-#if 0 +- if (!connected) { +- /* default to unknown for flaky chips/connectors +- * so we can get something on the screen +- */ +- if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) && +- (radeon_output->DACType == DAC_TVDAC) && +- (info->ChipFamily == CHIP_FAMILY_RS400)) { +- radeon_output->MonType = MT_CRT; +- return XF86OutputStatusUnknown; +- } else if ((info->ChipFamily == CHIP_FAMILY_RS400) && +- radeon_output->type == OUTPUT_DVI_D) { +- radeon_output->MonType = MT_DFP; /* MT_LCD ??? */ +- return XF86OutputStatusUnknown; +- } +- } +-#endif +- + if (connected) + return XF86OutputStatusConnected; + else +@@ -1149,7 +1076,7 @@ radeon_set_backlight_level(xf86OutputPtr output, int level) + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char * RADEONMMIO = info->MMIO; +- CARD32 lvds_gen_cntl; ++ uint32_t lvds_gen_cntl; + + lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); + lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; +@@ -1168,6 +1095,7 @@ static Atom tmds_pll_atom; static Atom rmx_atom; static Atom monitor_type_atom; static Atom load_detection_atom; @@ -9023,7 +11548,7 @@ index 62cc5d4..907d824 100644 static Atom tv_hsize_atom; static Atom tv_hpos_atom; static Atom tv_vpos_atom; -@@ -1235,6 +1241,30 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1235,6 +1163,30 @@ radeon_create_resources(xf86OutputPtr output) } } @@ -9054,7 +11579,7 @@ index 62cc5d4..907d824 100644 if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) { tmds_pll_atom = MAKE_ATOM("tmds_pll"); -@@ -1413,6 +1443,26 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1413,6 +1365,26 @@ radeon_create_resources(xf86OutputPtr output) } static Bool @@ -9081,7 +11606,7 @@ index 62cc5d4..907d824 100644 radeon_set_property(xf86OutputPtr output, Atom property, RRPropertyValuePtr value) { -@@ -1451,22 +1501,47 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1451,22 +1423,47 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->load_detection = val; @@ -9133,7 +11658,7 @@ index 62cc5d4..907d824 100644 } else if (property == tmds_pll_atom) { const char *s; if (value->type != XA_STRING || value->format != 8) -@@ -1475,12 +1550,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1475,12 +1472,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, if (value->size == strlen("bios") && !strncmp("bios", s, strlen("bios"))) { if (!RADEONGetTMDSInfoFromBIOS(output)) RADEONGetTMDSInfoFromTable(output); @@ -9150,7 +11675,7 @@ index 62cc5d4..907d824 100644 } else if (property == monitor_type_atom) { const char *s; if (value->type != XA_STRING || value->format != 8) -@@ -1495,8 +1570,8 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1495,8 +1492,8 @@ radeon_set_property(xf86OutputPtr output, Atom property, } else if (value->size == strlen("digital") && !strncmp("digital", s, strlen("digital"))) { radeon_output->DVIType = DVI_DIGITAL; return TRUE; @@ -9161,7 +11686,7 @@ index 62cc5d4..907d824 100644 } else if (property == tv_hsize_atom) { if (value->type != XA_INTEGER || value->format != 32 || -@@ -1511,7 +1586,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1511,7 +1508,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->hSize = val; if (radeon_output->tv_on && !IS_AVIVO_VARIANT) RADEONUpdateHVPosition(output, &output->crtc->mode); @@ -9170,7 +11695,7 @@ index 62cc5d4..907d824 100644 } else if (property == tv_hpos_atom) { if (value->type != XA_INTEGER || value->format != 32 || -@@ -1526,7 +1601,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1526,7 +1523,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->hPos = val; if (radeon_output->tv_on && !IS_AVIVO_VARIANT) RADEONUpdateHVPosition(output, &output->crtc->mode); @@ -9179,7 +11704,7 @@ index 62cc5d4..907d824 100644 } else if (property == tv_vpos_atom) { if (value->type != XA_INTEGER || value->format != 32 || -@@ -1541,38 +1616,38 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1541,38 +1538,38 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->vPos = val; if (radeon_output->tv_on && !IS_AVIVO_VARIANT) RADEONUpdateHVPosition(output, &output->crtc->mode); @@ -9228,7 +11753,7 @@ index 62cc5d4..907d824 100644 } return TRUE; -@@ -1622,6 +1697,8 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output +@@ -1622,6 +1619,8 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output case CONNECTOR_HDMI_TYPE_A: case CONNECTOR_HDMI_TYPE_B: output = OUTPUT_HDMI; break; @@ -9237,7 +11762,64 @@ index 62cc5d4..907d824 100644 case CONNECTOR_DIGITAL: case CONNECTOR_NONE: case CONNECTOR_UNSUPPORTED: -@@ -2139,16 +2216,17 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -1653,7 +1652,7 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) + RADEONOutputPrivatePtr radeon_output = output->driver_private; + RADEONI2CBusPtr pRADEONI2CBus = radeon_output->pI2CBus->DriverPrivate.ptr; + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 temp; ++ uint32_t temp; + + temp = INREG(pRADEONI2CBus->mask_clk_reg); + if (lock_state == AVIVO_I2C_ENABLE) +@@ -1698,13 +1697,13 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) + unsigned char *RADEONMMIO = info->MMIO; + RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; + +- val = INREG(pRADEONI2CBus->put_clk_reg) & (CARD32)~(pRADEONI2CBus->put_clk_mask); ++ val = INREG(pRADEONI2CBus->put_clk_reg) & (uint32_t)~(pRADEONI2CBus->put_clk_mask); + val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask); + OUTREG(pRADEONI2CBus->put_clk_reg, val); + /* read back to improve reliability on some cards. */ + val = INREG(pRADEONI2CBus->put_clk_reg); + +- val = INREG(pRADEONI2CBus->put_data_reg) & (CARD32)~(pRADEONI2CBus->put_data_mask); ++ val = INREG(pRADEONI2CBus->put_data_reg) & (uint32_t)~(pRADEONI2CBus->put_data_mask); + val |= (data ? 0:pRADEONI2CBus->put_data_mask); + OUTREG(pRADEONI2CBus->put_data_reg, val); + /* read back to improve reliability on some cards. */ +@@ -1821,8 +1820,8 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); +- CARD32 fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); ++ uint32_t fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); ++ uint32_t fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); + + radeon_output->PanelPwrDly = 200; + if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { +@@ -1845,7 +1844,7 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) + + // move this to crtc function + if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { +- CARD32 ppll_div_sel, ppll_val; ++ uint32_t ppll_div_sel, ppll_val; + + ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; + RADEONPllErrataAfterIndex(info); +@@ -2067,9 +2066,8 @@ RADEONGetTMDSInfo(xf86OutputPtr output) + radeon_output->tmds_pll[i].freq = 0; + } + +- if (RADEONGetTMDSInfoFromBIOS(output)) return; +- +- RADEONGetTMDSInfoFromTable(output); ++ if (!RADEONGetTMDSInfoFromBIOS(output)) ++ RADEONGetTMDSInfoFromTable(output); + + } + +@@ -2139,16 +2137,17 @@ void RADEONInitConnector(xf86OutputPtr output) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -9260,17 +11842,96 @@ index 62cc5d4..907d824 100644 if (radeon_output->type == OUTPUT_LVDS) { radeon_output->rmx_type = RMX_FULL; -@@ -2189,6 +2267,9 @@ void RADEONInitConnector(xf86OutputPtr output) - RADEONGetTVDacAdjInfo(output); +@@ -2179,16 +2178,17 @@ void RADEONInitConnector(xf86OutputPtr output) + RADEONGetTMDSInfo(output); } -+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) -+ radeon_output->coherent_mode = TRUE; +- if (OUTPUT_IS_TV) { ++ if (OUTPUT_IS_TV) + RADEONGetTVInfo(output); +- RADEONGetTVDacAdjInfo(output); +- } + + if (radeon_output->DACType == DAC_TVDAC) { + radeon_output->tv_on = FALSE; + RADEONGetTVDacAdjInfo(output); + } + ++ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) ++ radeon_output->coherent_mode = TRUE; + if (radeon_output->ddc_i2c.valid) RADEONI2CInit(output, &radeon_output->pI2CBus, output->name, FALSE); -@@ -2729,11 +2810,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2393,7 +2393,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[0].valid = TRUE; + + /* IGP only has TVDAC */ +- if (info->ChipFamily == CHIP_FAMILY_RS400) ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); + else + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); +@@ -2421,7 +2422,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + } else { + /* Below is the most common setting, but may not be true */ + if (info->IsIGP) { +- if (info->ChipFamily == CHIP_FAMILY_RS400) ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); + else + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); +@@ -2595,10 +2597,47 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) + + #endif /* __powerpc__ */ + ++static int ++radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn); ++ int o; ++ int index_mask = 0; ++ ++ if (IS_DCE3_VARIANT) ++ return index_mask; ++ ++ /* LVDS is too wacky */ ++ if (radeon_output->type == OUTPUT_LVDS) ++ return index_mask; ++ ++ for (o = 0; o < config->num_output; o++) { ++ xf86OutputPtr clone = config->output[o]; ++ RADEONOutputPrivatePtr radeon_clone = clone->driver_private; ++ if (output == clone) /* don't clone yourself */ ++ continue; ++ else if (radeon_clone->type == OUTPUT_LVDS) /* LVDS */ ++ continue; ++ else if ((radeon_output->DACType != DAC_NONE) && ++ (radeon_output->DACType == radeon_clone->DACType)) /* shared dac */ ++ continue; ++ else if ((radeon_output->TMDSType != TMDS_NONE) && ++ (radeon_output->TMDSType == radeon_clone->TMDSType)) /* shared tmds */ ++ continue; ++ else ++ index_mask |= (1 << o); ++ } ++ ++ return index_mask; ++} ++ + /* + * initialise the static data sos we don't have to re-do at randr change */ + Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + { ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + xf86OutputPtr output; +@@ -2729,11 +2768,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) { if (info->BiosConnector[i].valid) { @@ -9284,7 +11945,7 @@ index 62cc5d4..907d824 100644 if (!radeon_output) { return FALSE; } -@@ -2742,6 +2824,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2742,6 +2782,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) radeon_output->devices = info->BiosConnector[i].devices; radeon_output->output_id = info->BiosConnector[i].output_id; radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c; @@ -9292,8 +11953,21 @@ index 62cc5d4..907d824 100644 if (radeon_output->ConnectorType == CONNECTOR_DVI_D) radeon_output->DACType = DAC_NONE; +@@ -2798,6 +2839,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + } + } + ++ for (i = 0; i < xf86_config->num_output; i++) { ++ xf86OutputPtr output = xf86_config->output[i]; ++ ++ output->possible_clones = radeon_output_clones(pScrn, output); ++ } ++ + return TRUE; + } + diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index ab6b62a..7bfae55 100644 +index ab6b62a..7e4cb17 100644 --- a/src/radeon_pci_chipset_gen.h +++ b/src/radeon_pci_chipset_gen.h @@ -201,9 +201,9 @@ PciChipsets RADEONPciChipsets[] = { @@ -9309,7 +11983,17 @@ index ab6b62a..7bfae55 100644 { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA }, { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA }, { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA }, -@@ -276,5 +276,24 @@ PciChipsets RADEONPciChipsets[] = { +@@ -235,6 +235,9 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, + { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA }, + { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA }, ++ { PCI_CHIP_RS600_793F, PCI_CHIP_RS600_793F, RES_SHARED_VGA }, ++ { PCI_CHIP_RS600_7941, PCI_CHIP_RS600_7941, RES_SHARED_VGA }, ++ { PCI_CHIP_RS600_7942, PCI_CHIP_RS600_7942, RES_SHARED_VGA }, + { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA }, + { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA }, + { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA }, +@@ -276,5 +279,24 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, @@ -9335,7 +12019,7 @@ index ab6b62a..7bfae55 100644 { -1, -1, RES_UNDEFINED } }; diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h -index 04393da..2a04f8d 100644 +index 04393da..72ff0d1 100644 --- a/src/radeon_pci_device_match_gen.h +++ b/src/radeon_pci_device_match_gen.h @@ -201,9 +201,9 @@ static const struct pci_id_match radeon_device_match[] = { @@ -9351,7 +12035,17 @@ index 04393da..2a04f8d 100644 ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ), -@@ -276,5 +276,24 @@ static const struct pci_id_match radeon_device_match[] = { +@@ -235,6 +235,9 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RS350_7835, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS690_791E, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS690_791F, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS600_793F, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS600_7941, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS600_7942, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS740_796C, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS740_796D, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS740_796E, 0 ), +@@ -276,5 +279,24 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ), @@ -9390,7 +12084,7 @@ index 4ec7485..5d2eb43 100644 /* Return the options for supported chipset 'n'; NULL otherwise */ static const OptionInfoRec * diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index 9c1bdc5..f03e997 100644 +index 9c1bdc5..24af52b 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -104,7 +104,8 @@ typedef enum @@ -9403,8 +12097,57 @@ index 9c1bdc5..f03e997 100644 } RADEONTmdsType; typedef enum -@@ -191,12 +192,8 @@ typedef struct _RADEONCrtcPrivateRec { - CARD8 lut_r[256], lut_g[256], lut_b[256]; +@@ -122,8 +123,8 @@ typedef enum + } RADEONRMXType; + + typedef struct { +- CARD32 freq; +- CARD32 value; ++ uint32_t freq; ++ uint32_t value; + }RADEONTMDSPll; + + typedef enum +@@ -163,18 +164,18 @@ typedef enum + typedef struct + { + Bool valid; +- CARD32 mask_clk_reg; +- CARD32 mask_data_reg; +- CARD32 put_clk_reg; +- CARD32 put_data_reg; +- CARD32 get_clk_reg; +- CARD32 get_data_reg; +- CARD32 mask_clk_mask; +- CARD32 mask_data_mask; +- CARD32 put_clk_mask; +- CARD32 put_data_mask; +- CARD32 get_clk_mask; +- CARD32 get_data_mask; ++ uint32_t mask_clk_reg; ++ uint32_t mask_data_reg; ++ uint32_t put_clk_reg; ++ uint32_t put_data_reg; ++ uint32_t get_clk_reg; ++ uint32_t get_data_reg; ++ uint32_t mask_clk_mask; ++ uint32_t mask_data_mask; ++ uint32_t put_clk_mask; ++ uint32_t put_data_mask; ++ uint32_t get_clk_mask; ++ uint32_t get_data_mask; + } RADEONI2CBusRec, *RADEONI2CBusPtr; + + typedef struct _RADEONCrtcPrivateRec { +@@ -186,17 +187,13 @@ typedef struct _RADEONCrtcPrivateRec { + #endif + int crtc_id; + int binding; +- CARD32 cursor_offset; ++ uint32_t cursor_offset; + /* Lookup table values to be set when the CRTC is enabled */ +- CARD8 lut_r[256], lut_g[256], lut_b[256]; ++ uint8_t lut_r[256], lut_g[256], lut_b[256]; uint32_t crtc_offset; - int h_total, h_blank, h_sync_wid, h_sync_pol; @@ -9418,7 +12161,7 @@ index 9c1bdc5..f03e997 100644 } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; typedef struct { -@@ -208,6 +205,7 @@ typedef struct { +@@ -208,13 +205,14 @@ typedef struct { int devices; int hpd_mask; RADEONI2CBusRec ddc_i2c; @@ -9426,7 +12169,28 @@ index 9c1bdc5..f03e997 100644 } RADEONBIOSConnector; typedef struct _RADEONOutputPrivateRec { -@@ -256,10 +254,15 @@ typedef struct _RADEONOutputPrivateRec { + int num; + RADEONOutputType type; + void *dev_priv; +- CARD32 ddc_line; ++ uint32_t ddc_line; + RADEONDacType DACType; + RADEONDviType DVIType; + RADEONTmdsType TMDSType; +@@ -224,9 +222,9 @@ typedef struct _RADEONOutputPrivateRec { + int DDCReg; + I2CBusPtr pI2CBus; + RADEONI2CBusRec ddc_i2c; +- CARD32 ps2_tvdac_adj; +- CARD32 pal_tvdac_adj; +- CARD32 ntsc_tvdac_adj; ++ uint32_t ps2_tvdac_adj; ++ uint32_t pal_tvdac_adj; ++ uint32_t ntsc_tvdac_adj; + /* panel stuff */ + int PanelXRes; + int PanelYRes; +@@ -256,95 +254,78 @@ typedef struct _RADEONOutputPrivateRec { int SupportedTVStds; Bool tv_on; int load_detection; @@ -9442,18 +12206,79 @@ index 9c1bdc5..f03e997 100644 } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; struct avivo_pll_state { -@@ -273,7 +276,6 @@ struct avivo_pll_state { - CARD32 int_ss_cntl; +- CARD32 ref_div_src; +- CARD32 ref_div; +- CARD32 fb_div; +- CARD32 post_div_src; +- CARD32 post_div; +- CARD32 ext_ppll_cntl; +- CARD32 pll_cntl; +- CARD32 int_ss_cntl; ++ uint32_t ref_div_src; ++ uint32_t ref_div; ++ uint32_t fb_div; ++ uint32_t post_div_src; ++ uint32_t post_div; ++ uint32_t ext_ppll_cntl; ++ uint32_t pll_cntl; ++ uint32_t int_ss_cntl; }; - struct avivo_crtc_state { - CARD32 pll_source; - CARD32 h_total; -@@ -310,24 +312,6 @@ struct avivo_grph_state { +- CARD32 pll_source; +- CARD32 h_total; +- CARD32 h_blank_start_end; +- CARD32 h_sync_a; +- CARD32 h_sync_a_cntl; +- CARD32 h_sync_b; +- CARD32 h_sync_b_cntl; +- CARD32 v_total; +- CARD32 v_blank_start_end; +- CARD32 v_sync_a; +- CARD32 v_sync_a_cntl; +- CARD32 v_sync_b; +- CARD32 v_sync_b_cntl; +- CARD32 control; +- CARD32 blank_control; +- CARD32 interlace_control; +- CARD32 stereo_control; +- CARD32 cursor_control; ++ uint32_t pll_source; ++ uint32_t h_total; ++ uint32_t h_blank_start_end; ++ uint32_t h_sync_a; ++ uint32_t h_sync_a_cntl; ++ uint32_t h_sync_b; ++ uint32_t h_sync_b_cntl; ++ uint32_t v_total; ++ uint32_t v_blank_start_end; ++ uint32_t v_sync_a; ++ uint32_t v_sync_a_cntl; ++ uint32_t v_sync_b; ++ uint32_t v_sync_b_cntl; ++ uint32_t control; ++ uint32_t blank_control; ++ uint32_t interlace_control; ++ uint32_t stereo_control; ++ uint32_t cursor_control; + }; - CARD32 viewport_start; - CARD32 viewport_size; + struct avivo_grph_state { +- CARD32 enable; +- CARD32 control; +- CARD32 prim_surf_addr; +- CARD32 sec_surf_addr; +- CARD32 pitch; +- CARD32 x_offset; +- CARD32 y_offset; +- CARD32 x_start; +- CARD32 y_start; +- CARD32 x_end; +- CARD32 y_end; +- +- CARD32 viewport_start; +- CARD32 viewport_size; - CARD32 scl_enable; - CARD32 scl_tap_control; -}; @@ -9472,19 +12297,48 @@ index 9c1bdc5..f03e997 100644 - CARD32 transmitter_enable; - CARD32 transmitter_cntl; - CARD32 source_select; ++ uint32_t enable; ++ uint32_t control; ++ uint32_t prim_surf_addr; ++ uint32_t sec_surf_addr; ++ uint32_t pitch; ++ uint32_t x_offset; ++ uint32_t y_offset; ++ uint32_t x_start; ++ uint32_t y_start; ++ uint32_t x_end; ++ uint32_t y_end; ++ ++ uint32_t viewport_start; ++ uint32_t viewport_size; }; struct avivo_state -@@ -343,9 +327,6 @@ struct avivo_state - CARD32 crtc_master_en; - CARD32 crtc_tv_control; - + { +- CARD32 hdp_fb_location; +- CARD32 mc_memory_map; +- CARD32 vga_memory_base; +- CARD32 vga_fb_start; ++ uint32_t hdp_fb_location; ++ uint32_t mc_memory_map; ++ uint32_t vga_memory_base; ++ uint32_t vga_fb_start; + +- CARD32 vga1_cntl; +- CARD32 vga2_cntl; ++ uint32_t vga1_cntl; ++ uint32_t vga2_cntl; + +- CARD32 crtc_master_en; +- CARD32 crtc_tv_control; +- - CARD32 lvtma_pwrseq_cntl; - CARD32 lvtma_pwrseq_state; -- ++ uint32_t crtc_master_en; ++ uint32_t crtc_tv_control; + struct avivo_pll_state pll1; struct avivo_pll_state pll2; - @@ -355,11 +336,41 @@ struct avivo_state struct avivo_grph_state grph1; struct avivo_grph_state grph2; @@ -9495,64 +12349,366 @@ index 9c1bdc5..f03e997 100644 - struct avivo_dig_state tmds1; - struct avivo_dig_state tmds2; + /* DDIA block on RS6xx chips */ -+ CARD32 ddia[37]; ++ uint32_t ddia[37]; + + /* scalers */ -+ CARD32 d1scl[40]; -+ CARD32 d2scl[40]; -+ CARD32 dxscl[6+2]; ++ uint32_t d1scl[40]; ++ uint32_t d2scl[40]; ++ uint32_t dxscl[6+2]; + + /* dac regs */ -+ CARD32 daca[26]; -+ CARD32 dacb[26]; ++ uint32_t daca[26]; ++ uint32_t dacb[26]; + + /* tmdsa */ -+ CARD32 tmdsa[31]; ++ uint32_t tmdsa[31]; + + /* lvtma */ -+ CARD32 lvtma[39]; ++ uint32_t lvtma[39]; + + /* dvoa */ -+ CARD32 dvoa[16]; ++ uint32_t dvoa[16]; + + /* DCE3 chips */ -+ CARD32 fmt1[18]; -+ CARD32 fmt2[18]; -+ CARD32 dig1[19]; -+ CARD32 dig2[19]; -+ CARD32 hdmi1[57]; -+ CARD32 hdmi2[57]; -+ CARD32 aux_cntl1[14]; -+ CARD32 aux_cntl2[14]; -+ CARD32 aux_cntl3[14]; -+ CARD32 aux_cntl4[14]; -+ CARD32 phy[10]; -+ CARD32 uniphy1[8]; -+ CARD32 uniphy2[8]; ++ uint32_t fmt1[18]; ++ uint32_t fmt2[18]; ++ uint32_t dig1[19]; ++ uint32_t dig2[19]; ++ uint32_t hdmi1[57]; ++ uint32_t hdmi2[57]; ++ uint32_t aux_cntl1[14]; ++ uint32_t aux_cntl2[14]; ++ uint32_t aux_cntl3[14]; ++ uint32_t aux_cntl4[14]; ++ uint32_t phy[10]; ++ uint32_t uniphy1[8]; ++ uint32_t uniphy2[8]; }; -@@ -495,10 +506,16 @@ typedef struct { - CARD32 palette[256]; - CARD32 palette2[256]; +@@ -373,100 +384,100 @@ typedef struct { + struct avivo_state avivo; + + /* Common registers */ +- CARD32 ovr_clr; +- CARD32 ovr_wid_left_right; +- CARD32 ovr_wid_top_bottom; +- CARD32 ov0_scale_cntl; +- CARD32 mpp_tb_config; +- CARD32 mpp_gp_config; +- CARD32 subpic_cntl; +- CARD32 viph_control; +- CARD32 i2c_cntl_1; +- CARD32 gen_int_cntl; +- CARD32 cap0_trig_cntl; +- CARD32 cap1_trig_cntl; +- CARD32 bus_cntl; +- +- CARD32 bios_0_scratch; +- CARD32 bios_1_scratch; +- CARD32 bios_2_scratch; +- CARD32 bios_3_scratch; +- CARD32 bios_4_scratch; +- CARD32 bios_5_scratch; +- CARD32 bios_6_scratch; +- CARD32 bios_7_scratch; +- +- CARD32 surface_cntl; +- CARD32 surfaces[8][3]; +- CARD32 mc_agp_location; +- CARD32 mc_agp_location_hi; +- CARD32 mc_fb_location; +- CARD32 display_base_addr; +- CARD32 display2_base_addr; +- CARD32 ov0_base_addr; ++ uint32_t ovr_clr; ++ uint32_t ovr_wid_left_right; ++ uint32_t ovr_wid_top_bottom; ++ uint32_t ov0_scale_cntl; ++ uint32_t mpp_tb_config; ++ uint32_t mpp_gp_config; ++ uint32_t subpic_cntl; ++ uint32_t viph_control; ++ uint32_t i2c_cntl_1; ++ uint32_t gen_int_cntl; ++ uint32_t cap0_trig_cntl; ++ uint32_t cap1_trig_cntl; ++ uint32_t bus_cntl; ++ ++ uint32_t bios_0_scratch; ++ uint32_t bios_1_scratch; ++ uint32_t bios_2_scratch; ++ uint32_t bios_3_scratch; ++ uint32_t bios_4_scratch; ++ uint32_t bios_5_scratch; ++ uint32_t bios_6_scratch; ++ uint32_t bios_7_scratch; ++ ++ uint32_t surface_cntl; ++ uint32_t surfaces[8][3]; ++ uint32_t mc_agp_location; ++ uint32_t mc_agp_location_hi; ++ uint32_t mc_fb_location; ++ uint32_t display_base_addr; ++ uint32_t display2_base_addr; ++ uint32_t ov0_base_addr; + + /* Other registers to save for VT switches */ +- CARD32 dp_datatype; +- CARD32 rbbm_soft_reset; +- CARD32 clock_cntl_index; +- CARD32 amcgpio_en_reg; +- CARD32 amcgpio_mask; ++ uint32_t dp_datatype; ++ uint32_t rbbm_soft_reset; ++ uint32_t clock_cntl_index; ++ uint32_t amcgpio_en_reg; ++ uint32_t amcgpio_mask; + + /* CRTC registers */ +- CARD32 crtc_gen_cntl; +- CARD32 crtc_ext_cntl; +- CARD32 dac_cntl; +- CARD32 crtc_h_total_disp; +- CARD32 crtc_h_sync_strt_wid; +- CARD32 crtc_v_total_disp; +- CARD32 crtc_v_sync_strt_wid; +- CARD32 crtc_offset; +- CARD32 crtc_offset_cntl; +- CARD32 crtc_pitch; +- CARD32 disp_merge_cntl; +- CARD32 grph_buffer_cntl; +- CARD32 crtc_more_cntl; +- CARD32 crtc_tile_x0_y0; ++ uint32_t crtc_gen_cntl; ++ uint32_t crtc_ext_cntl; ++ uint32_t dac_cntl; ++ uint32_t crtc_h_total_disp; ++ uint32_t crtc_h_sync_strt_wid; ++ uint32_t crtc_v_total_disp; ++ uint32_t crtc_v_sync_strt_wid; ++ uint32_t crtc_offset; ++ uint32_t crtc_offset_cntl; ++ uint32_t crtc_pitch; ++ uint32_t disp_merge_cntl; ++ uint32_t grph_buffer_cntl; ++ uint32_t crtc_more_cntl; ++ uint32_t crtc_tile_x0_y0; + + /* CRTC2 registers */ +- CARD32 crtc2_gen_cntl; +- CARD32 dac_macro_cntl; +- CARD32 dac2_cntl; +- CARD32 disp_output_cntl; +- CARD32 disp_tv_out_cntl; +- CARD32 disp_hw_debug; +- CARD32 disp2_merge_cntl; +- CARD32 grph2_buffer_cntl; +- CARD32 crtc2_h_total_disp; +- CARD32 crtc2_h_sync_strt_wid; +- CARD32 crtc2_v_total_disp; +- CARD32 crtc2_v_sync_strt_wid; +- CARD32 crtc2_offset; +- CARD32 crtc2_offset_cntl; +- CARD32 crtc2_pitch; +- CARD32 crtc2_tile_x0_y0; ++ uint32_t crtc2_gen_cntl; ++ uint32_t dac_macro_cntl; ++ uint32_t dac2_cntl; ++ uint32_t disp_output_cntl; ++ uint32_t disp_tv_out_cntl; ++ uint32_t disp_hw_debug; ++ uint32_t disp2_merge_cntl; ++ uint32_t grph2_buffer_cntl; ++ uint32_t crtc2_h_total_disp; ++ uint32_t crtc2_h_sync_strt_wid; ++ uint32_t crtc2_v_total_disp; ++ uint32_t crtc2_v_sync_strt_wid; ++ uint32_t crtc2_offset; ++ uint32_t crtc2_offset_cntl; ++ uint32_t crtc2_pitch; ++ uint32_t crtc2_tile_x0_y0; + + /* Flat panel registers */ +- CARD32 fp_crtc_h_total_disp; +- CARD32 fp_crtc_v_total_disp; +- CARD32 fp_gen_cntl; +- CARD32 fp2_gen_cntl; +- CARD32 fp_h_sync_strt_wid; +- CARD32 fp_h2_sync_strt_wid; +- CARD32 fp_horz_stretch; +- CARD32 fp_horz_vert_active; +- CARD32 fp_panel_cntl; +- CARD32 fp_v_sync_strt_wid; +- CARD32 fp_v2_sync_strt_wid; +- CARD32 fp_vert_stretch; +- CARD32 lvds_gen_cntl; +- CARD32 lvds_pll_cntl; +- CARD32 tmds_pll_cntl; +- CARD32 tmds_transmitter_cntl; ++ uint32_t fp_crtc_h_total_disp; ++ uint32_t fp_crtc_v_total_disp; ++ uint32_t fp_gen_cntl; ++ uint32_t fp2_gen_cntl; ++ uint32_t fp_h_sync_strt_wid; ++ uint32_t fp_h2_sync_strt_wid; ++ uint32_t fp_horz_stretch; ++ uint32_t fp_horz_vert_active; ++ uint32_t fp_panel_cntl; ++ uint32_t fp_v_sync_strt_wid; ++ uint32_t fp_v2_sync_strt_wid; ++ uint32_t fp_vert_stretch; ++ uint32_t lvds_gen_cntl; ++ uint32_t lvds_pll_cntl; ++ uint32_t tmds_pll_cntl; ++ uint32_t tmds_transmitter_cntl; + + /* Computed values for PLL */ +- CARD32 dot_clock_freq; +- CARD32 pll_output_freq; ++ uint32_t dot_clock_freq; ++ uint32_t pll_output_freq; + int feedback_div; + int reference_div; + int post_div; +@@ -474,75 +485,81 @@ typedef struct { + /* PLL registers */ + unsigned ppll_ref_div; + unsigned ppll_div_3; +- CARD32 htotal_cntl; +- CARD32 vclk_ecp_cntl; ++ uint32_t htotal_cntl; ++ uint32_t vclk_ecp_cntl; + + /* Computed values for PLL2 */ +- CARD32 dot_clock_freq_2; +- CARD32 pll_output_freq_2; ++ uint32_t dot_clock_freq_2; ++ uint32_t pll_output_freq_2; + int feedback_div_2; + int reference_div_2; + int post_div_2; + + /* PLL2 registers */ +- CARD32 p2pll_ref_div; +- CARD32 p2pll_div_0; +- CARD32 htotal_cntl2; +- CARD32 pixclks_cntl; ++ uint32_t p2pll_ref_div; ++ uint32_t p2pll_div_0; ++ uint32_t htotal_cntl2; ++ uint32_t pixclks_cntl; + + /* Pallet */ + Bool palette_valid; +- CARD32 palette[256]; +- CARD32 palette2[256]; ++ uint32_t palette[256]; ++ uint32_t palette2[256]; ++ ++ uint32_t disp2_req_cntl1; ++ uint32_t disp2_req_cntl2; ++ uint32_t dmif_mem_cntl1; ++ uint32_t disp1_req_cntl1; ++ ++ uint32_t fp_2nd_gen_cntl; ++ uint32_t fp2_2_gen_cntl; ++ uint32_t tmds2_cntl; ++ uint32_t tmds2_transmitter_cntl; - CARD32 rs480_unk_e30; - CARD32 rs480_unk_e34; - CARD32 rs480_unk_e38; - CARD32 rs480_unk_e3c; -+ CARD32 disp2_req_cntl1; -+ CARD32 disp2_req_cntl2; -+ CARD32 dmif_mem_cntl1; -+ CARD32 disp1_req_cntl1; -+ -+ CARD32 fp_2nd_gen_cntl; -+ CARD32 fp2_2_gen_cntl; -+ CARD32 tmds2_cntl; -+ CARD32 tmds2_transmitter_cntl; -+ /* TV out registers */ - CARD32 tv_master_cntl; +- CARD32 tv_master_cntl; +- CARD32 tv_htotal; +- CARD32 tv_hsize; +- CARD32 tv_hdisp; +- CARD32 tv_hstart; +- CARD32 tv_vtotal; +- CARD32 tv_vdisp; +- CARD32 tv_timing_cntl; +- CARD32 tv_vscaler_cntl1; +- CARD32 tv_vscaler_cntl2; +- CARD32 tv_sync_size; +- CARD32 tv_vrestart; +- CARD32 tv_hrestart; +- CARD32 tv_frestart; +- CARD32 tv_ftotal; +- CARD32 tv_clock_sel_cntl; +- CARD32 tv_clkout_cntl; +- CARD32 tv_data_delay_a; +- CARD32 tv_data_delay_b; +- CARD32 tv_dac_cntl; +- CARD32 tv_pll_cntl; +- CARD32 tv_pll_cntl1; +- CARD32 tv_pll_fine_cntl; +- CARD32 tv_modulator_cntl1; +- CARD32 tv_modulator_cntl2; +- CARD32 tv_frame_lock_cntl; +- CARD32 tv_pre_dac_mux_cntl; +- CARD32 tv_rgb_cntl; +- CARD32 tv_y_saw_tooth_cntl; +- CARD32 tv_y_rise_cntl; +- CARD32 tv_y_fall_cntl; +- CARD32 tv_uv_adr; +- CARD32 tv_upsamp_and_gain_cntl; +- CARD32 tv_gain_limit_settings; +- CARD32 tv_linear_gain_settings; +- CARD32 tv_crc_cntl; +- CARD32 tv_sync_cntl; +- CARD32 gpiopad_a; +- CARD32 pll_test_cntl; +- +- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; +- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; ++ uint32_t tv_master_cntl; ++ uint32_t tv_htotal; ++ uint32_t tv_hsize; ++ uint32_t tv_hdisp; ++ uint32_t tv_hstart; ++ uint32_t tv_vtotal; ++ uint32_t tv_vdisp; ++ uint32_t tv_timing_cntl; ++ uint32_t tv_vscaler_cntl1; ++ uint32_t tv_vscaler_cntl2; ++ uint32_t tv_sync_size; ++ uint32_t tv_vrestart; ++ uint32_t tv_hrestart; ++ uint32_t tv_frestart; ++ uint32_t tv_ftotal; ++ uint32_t tv_clock_sel_cntl; ++ uint32_t tv_clkout_cntl; ++ uint32_t tv_data_delay_a; ++ uint32_t tv_data_delay_b; ++ uint32_t tv_dac_cntl; ++ uint32_t tv_pll_cntl; ++ uint32_t tv_pll_cntl1; ++ uint32_t tv_pll_fine_cntl; ++ uint32_t tv_modulator_cntl1; ++ uint32_t tv_modulator_cntl2; ++ uint32_t tv_frame_lock_cntl; ++ uint32_t tv_pre_dac_mux_cntl; ++ uint32_t tv_rgb_cntl; ++ uint32_t tv_y_saw_tooth_cntl; ++ uint32_t tv_y_rise_cntl; ++ uint32_t tv_y_fall_cntl; ++ uint32_t tv_uv_adr; ++ uint32_t tv_upsamp_and_gain_cntl; ++ uint32_t tv_gain_limit_settings; ++ uint32_t tv_linear_gain_settings; ++ uint32_t tv_crc_cntl; ++ uint32_t tv_sync_cntl; ++ uint32_t gpiopad_a; ++ uint32_t pll_test_cntl; ++ ++ uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; ++ uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; + + } RADEONSaveRec, *RADEONSavePtr; + @@ -571,6 +588,7 @@ typedef struct RADEONSaveRec ModeReg; /* Current mode */ RADEONSaveRec SavedReg; /* Original (text) mode */ @@ -9562,13 +12718,16 @@ index 9c1bdc5..f03e997 100644 /* radeon_probe.c */ diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 046c52b..815bcaa 100644 +index 046c52b..c5ab0de 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h -@@ -887,6 +887,33 @@ +@@ -886,7 +886,35 @@ + # define RADEON_VERT_STRETCH_LINEREP (0 << 26) # define RADEON_VERT_STRETCH_BLEND (1 << 26) # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) - # define RADEON_VERT_STRETCH_RESERVED 0xf1000000 +-# define RADEON_VERT_STRETCH_RESERVED 0xf1000000 ++# define RADEON_VERT_AUTO_RATIO_INC (1 << 31) ++# define RADEON_VERT_STRETCH_RESERVED 0x71000000 +#define RS400_FP_2ND_GEN_CNTL 0x0384 +# define RS400_FP_2ND_ON (1 << 0) +# define RS400_FP_2ND_BLANK_EN (1 << 1) @@ -9599,7 +12758,7 @@ index 046c52b..815bcaa 100644 #define RADEON_GEN_INT_CNTL 0x0040 #define RADEON_GEN_INT_STATUS 0x0044 -@@ -1634,9 +1661,25 @@ +@@ -1634,9 +1662,25 @@ #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) @@ -9625,7 +12784,7 @@ index 046c52b..815bcaa 100644 #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ #define RADEON_XCLK_CNTL 0x000d /* PLL */ -@@ -3328,10 +3371,32 @@ +@@ -3328,10 +3372,32 @@ # define RADEON_TVPLL_TEST_DIS (1 << 31) # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) @@ -9662,7 +12821,26 @@ index 046c52b..815bcaa 100644 #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff -@@ -3475,6 +3540,8 @@ +@@ -3343,7 +3409,17 @@ + #define RS690_MC_AGP_LOCATION 0x101 + #define RS690_MC_AGP_BASE 0x102 + #define RS690_MC_STATUS 0x90 +-#define RS690_MC_STATUS_IDLE (1 << 0) ++#define RS690_MC_STATUS_IDLE (1 << 0) ++ ++#define RS600_MC_INDEX 0x78 ++# define RS600_MC_INDEX_MASK 0xff ++# define RS600_MC_INDEX_WR_EN (1 << 8) ++# define RS600_MC_INDEX_WR_ACK 0xff ++#define RS600_MC_DATA 0x7c ++ ++#define RS600_MC_FB_LOCATION 0xA ++#define RS600_MC_STATUS 0x0 ++#define RS600_MC_STATUS_IDLE (1 << 0) + + #define AVIVO_MC_INDEX 0x0070 + #define R520_MC_STATUS 0x00 +@@ -3475,6 +3551,8 @@ #define AVIVO_D1CUR_SIZE 0x6410 #define AVIVO_D1CUR_POSITION 0x6414 #define AVIVO_D1CUR_HOT_SPOT 0x6418 @@ -9671,7 +12849,7 @@ index 046c52b..815bcaa 100644 #define AVIVO_DC_LUT_RW_SELECT 0x6480 #define AVIVO_DC_LUT_RW_MODE 0x6484 -@@ -3555,6 +3622,8 @@ +@@ -3555,6 +3633,8 @@ #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 @@ -9680,7 +12858,7 @@ index 046c52b..815bcaa 100644 #define AVIVO_DACA_ENABLE 0x7800 # define AVIVO_DAC_ENABLE (1 << 0) #define AVIVO_DACA_SOURCE_SELECT 0x7804 -@@ -3745,6 +3814,8 @@ +@@ -3745,6 +3825,8 @@ # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 @@ -9689,7 +12867,7 @@ index 046c52b..815bcaa 100644 #define AVIVO_GPIO_0 0x7e30 #define AVIVO_GPIO_1 0x7e40 #define AVIVO_GPIO_2 0x7e50 -@@ -3832,6 +3903,7 @@ +@@ -3832,6 +3914,7 @@ #define R300_GB_SELECT 0x401c #define R300_GB_ENABLE 0x4008 #define R300_GB_AA_CONFIG 0x4020 @@ -9697,7 +12875,7 @@ index 046c52b..815bcaa 100644 #define R300_GB_MSPOS0 0x4010 # define R300_MS_X0_SHIFT 0 # define R300_MS_Y0_SHIFT 4 -@@ -3850,6 +3922,10 @@ +@@ -3850,6 +3933,10 @@ # define R300_MS_Y5_SHIFT 20 # define R300_MSBD1_SHIFT 24 @@ -9708,7 +12886,7 @@ index 046c52b..815bcaa 100644 #define R300_GA_POLY_MODE 0x4288 # define R300_FRONT_PTYPE_POINT (0 << 4) # define R300_FRONT_PTYPE_LINE (1 << 4) -@@ -3889,6 +3965,8 @@ +@@ -3889,6 +3976,8 @@ # define R300_ALPHA3_SHADING_GOURAUD (2 << 14) #define R300_GA_OFFSET 0x4290 @@ -9717,7 +12895,7 @@ index 046c52b..815bcaa 100644 #define R300_VAP_CNTL_STATUS 0x2140 # define R300_PVS_BYPASS (1 << 8) #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -@@ -3899,6 +3977,7 @@ +@@ -3899,6 +3988,7 @@ # define R300_VF_MAX_VTX_NUM_SHIFT 18 # define R300_GL_CLIP_SPACE_DEF (0 << 22) # define R300_DX_CLIP_SPACE_DEF (1 << 22) @@ -9725,7 +12903,7 @@ index 046c52b..815bcaa 100644 #define R300_VAP_VTE_CNTL 0x20B0 # define R300_VPORT_X_SCALE_ENA (1 << 0) # define R300_VPORT_X_OFFSET_ENA (1 << 1) -@@ -3909,6 +3988,7 @@ +@@ -3909,6 +3999,7 @@ # define R300_VTX_XY_FMT (1 << 8) # define R300_VTX_Z_FMT (1 << 9) # define R300_VTX_W0_FMT (1 << 10) @@ -9733,7 +12911,7 @@ index 046c52b..815bcaa 100644 #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 # define R300_DATA_TYPE_0_SHIFT 0 -@@ -3986,6 +4066,123 @@ +@@ -3986,6 +4077,123 @@ # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 @@ -9857,7 +13035,7 @@ index 046c52b..815bcaa 100644 #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC #define R300_VAP_OUT_VTX_FMT_0 0x2090 # define R300_VTX_POS_PRESENT (1 << 0) -@@ -4019,6 +4216,9 @@ +@@ -4019,6 +4227,9 @@ # define R300_CLIP_DISABLE (1 << 16) # define R300_UCP_CULL_ONLY_ENA (1 << 17) # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) @@ -9867,7 +13045,7 @@ index 046c52b..815bcaa 100644 #define R300_SU_TEX_WRAP 0x42a0 #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 -@@ -4036,6 +4236,7 @@ +@@ -4036,6 +4247,7 @@ # define R300_RS_COUNT_HIRES_EN (1 << 18) #define R300_RS_IP_0 0x4310 @@ -9875,7 +13053,7 @@ index 046c52b..815bcaa 100644 # define R300_RS_TEX_PTR(x) (x << 0) # define R300_RS_COL_PTR(x) (x << 6) # define R300_RS_COL_FMT(x) (x << 9) -@@ -4063,7 +4264,10 @@ +@@ -4063,7 +4275,10 @@ # define R300_RS_W_EN (1 << 4) # define R300_TX_OFFSET_RS(x) (x << 5) #define R300_RS_INST_0 0x4330 @@ -9886,7 +13064,7 @@ index 046c52b..815bcaa 100644 #define R300_TX_INVALTAGS 0x4100 #define R300_TX_FILTER0_0 0x4400 -@@ -4082,6 +4286,7 @@ +@@ -4082,6 +4297,7 @@ # define R300_TX_MIN_FILTER_NEAREST (1 << 11) # define R300_TX_MAG_FILTER_LINEAR (2 << 9) # define R300_TX_MIN_FILTER_LINEAR (2 << 11) @@ -9894,7 +13072,7 @@ index 046c52b..815bcaa 100644 #define R300_TX_FILTER1_0 0x4440 #define R300_TX_FORMAT0_0 0x4480 # define R300_TXWIDTH_SHIFT 0 -@@ -4164,11 +4369,16 @@ +@@ -4164,11 +4380,16 @@ # define R300_TX_FORMAT_SWAP_YUV (1 << 24) #define R300_TX_FORMAT2_0 0x4500 @@ -9912,7 +13090,7 @@ index 046c52b..815bcaa 100644 #define R300_TX_ENABLE 0x4104 # define R300_TEX_0_ENABLE (1 << 0) -@@ -4189,7 +4399,7 @@ +@@ -4189,7 +4410,7 @@ # define R300_OUT_FMT_C2_16_MPEG (7 << 0) # define R300_OUT_FMT_C2_4 (8 << 0) # define R300_OUT_FMT_C_3_3_2 (9 << 0) @@ -9921,7 +13099,7 @@ index 046c52b..815bcaa 100644 # define R300_OUT_FMT_C_11_11_10 (11 << 0) # define R300_OUT_FMT_C_10_11_11 (12 << 0) # define R300_OUT_FMT_C_2_10_10_10 (13 << 0) -@@ -4227,28 +4437,221 @@ +@@ -4227,28 +4448,221 @@ # define R300_TEX_CODE_OFFSET(x) (x << 13) # define R300_TEX_CODE_SIZE(x) (x << 18) #define R300_US_CODE_ADDR_0 0x4610 @@ -9954,7 +13132,7 @@ index 046c52b..815bcaa 100644 +# define R300_ALU_RGB_ADDR0(x) (x << 0) +# define R300_ALU_RGB_ADDR1(x) (x << 6) +# define R300_ALU_RGB_ADDR2(x) (x << 12) -+/* ADDRD - where on the pixle stack the result of this instruction ++/* ADDRD - where on the pixel stack the result of this instruction + will be written */ +# define R300_ALU_RGB_ADDRD(x) (x << 18) +# define R300_ALU_RGB_WMASK(x) (x << 23) @@ -10046,7 +13224,7 @@ index 046c52b..815bcaa 100644 +# define R300_ALU_ALPHA_ADDR0(x) (x << 0) +# define R300_ALU_ALPHA_ADDR1(x) (x << 6) +# define R300_ALU_ALPHA_ADDR2(x) (x << 12) -+/* ADDRD - where on the pixle stack the result of this instruction ++/* ADDRD - where on the pixel stack the result of this instruction + will be written */ +# define R300_ALU_ALPHA_ADDRD(x) (x << 18) +# define R300_ALU_ALPHA_WMASK(x) (x << 23) @@ -10146,7 +13324,7 @@ index 046c52b..815bcaa 100644 #define R300_RB3D_ZSTENCILCNTL 0x4f04 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 #define R300_RB3D_BW_CNTL 0x4f1c -@@ -4256,6 +4659,9 @@ +@@ -4256,6 +4670,9 @@ #define R300_RB3D_ZTOP 0x4f14 #define R300_RB3D_ROPCNTL 0x4e18 #define R300_RB3D_BLENDCNTL 0x4e04 @@ -10156,7 +13334,7 @@ index 046c52b..815bcaa 100644 #define R300_RB3D_ABLENDCNTL 0x4e08 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c #define R300_RB3D_COLOROFFSET0 0x4e28 -@@ -4387,7 +4793,7 @@ +@@ -4387,7 +4804,7 @@ # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) @@ -10165,7 +13343,7 @@ index 046c52b..815bcaa 100644 #define R500_US_ALU_RGBA_INST_0 0xb000 # define R500_ALU_RGBA_OP_MAD (0 << 0) # define R500_ALU_RGBA_OP_DP3 (1 << 0) -@@ -4540,7 +4946,7 @@ +@@ -4540,7 +4957,7 @@ # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) @@ -10174,7 +13352,7 @@ index 046c52b..815bcaa 100644 #define R500_US_CMN_INST_0 0xb800 # define R500_INST_TYPE_ALU (0 << 0) # define R500_INST_TYPE_OUT (1 << 0) -@@ -4779,17 +5185,18 @@ +@@ -4779,17 +5196,18 @@ #define R500_GA_US_VECTOR_DATA 0x4254 #define R500_RS_INST_0 0x4320 @@ -10204,7 +13382,7 @@ index 046c52b..815bcaa 100644 #define R500_US_FC_CTRL 0x4624 #define R500_US_CODE_ADDR 0x4630 -@@ -4797,16 +5204,18 @@ +@@ -4797,16 +5215,18 @@ #define R500_US_CODE_OFFSET 0x4638 #define R500_RS_IP_0 0x4074 @@ -10235,9 +13413,77 @@ index 046c52b..815bcaa 100644 #endif diff --git a/src/radeon_render.c b/src/radeon_render.c -index a80d136..950753c 100644 +index a80d136..dbd5b79 100644 --- a/src/radeon_render.c +++ b/src/radeon_render.c +@@ -46,7 +46,7 @@ + struct blendinfo { + Bool dst_alpha; + Bool src_alpha; +- CARD32 blend_cntl; ++ uint32_t blend_cntl; + }; + + /* The first part of blend_cntl corresponds to Fa from the render "protocol" +@@ -166,8 +166,8 @@ static CARD32 RADEONDstFormats[] = { + 0 + }; + +-static CARD32 +-RadeonGetTextureFormat(CARD32 format) ++static uint32_t ++RadeonGetTextureFormat(uint32_t format) + { + switch (format) { + case PICT_a8r8g8b8: +@@ -187,8 +187,8 @@ RadeonGetTextureFormat(CARD32 format) + } + } + +-static CARD32 +-RadeonGetColorFormat(CARD32 format) ++static uint32_t ++RadeonGetColorFormat(uint32_t format) + { + switch (format) { + case PICT_a8r8g8b8: +@@ -207,10 +207,10 @@ RadeonGetColorFormat(CARD32 format) + /* Returns a RADEON_RB3D_BLENDCNTL value, or 0 if the operation is not + * supported + */ +-static CARD32 +-RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) ++static uint32_t ++RadeonGetBlendCntl(uint8_t op, uint32_t dstFormat) + { +- CARD32 blend_cntl; ++ uint32_t blend_cntl; + + if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0) + return 0; +@@ -218,7 +218,7 @@ RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) + blend_cntl = RadeonBlendOp[op].blend_cntl; + + if (RadeonBlendOp[op].dst_alpha && !PICT_FORMAT_A(dstFormat)) { +- CARD32 srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; ++ uint32_t srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; + + /* If there's no destination alpha channel, we need to wire the blending + * to treat the alpha channel as always 1. +@@ -235,11 +235,11 @@ RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) + return blend_cntl; + } + +-static __inline__ CARD32 F_TO_DW(float val) ++static __inline__ uint32_t F_TO_DW(float val) + { + union { + float f; +- CARD32 l; ++ uint32_t l; + } tmp; + tmp.f = val; + return tmp.l; @@ -250,10 +250,17 @@ static __inline__ int ATILog2(int val) { @@ -10257,8 +13503,147 @@ index a80d136..950753c 100644 } static void +@@ -317,7 +324,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 swapper = info->ModeReg->surface_cntl; ++ uint32_t swapper = info->ModeReg->surface_cntl; + + swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP | + RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP); +@@ -373,22 +380,22 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info) + + static Bool FUNC_NAME(R100SetupTexture)( + ScrnInfoPtr pScrn, +- CARD32 format, +- CARD8 *src, ++ uint32_t format, ++ uint8_t *src, + int src_pitch, + unsigned int width, + unsigned int height, + int flags) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD8 *dst; +- CARD32 tex_size = 0, txformat; ++ uint8_t *dst; ++ uint32_t tex_size = 0, txformat; + int dst_pitch, offset, size, tex_bytepp; + #ifdef ACCEL_CP +- CARD32 buf_pitch, dst_pitch_off; ++ uint32_t buf_pitch, dst_pitch_off; + int x, y; + unsigned int hpass; +- CARD8 *tmp_dst; ++ uint8_t *tmp_dst; + #endif + ACCEL_PREAMBLE(); + +@@ -429,7 +436,7 @@ static Bool FUNC_NAME(R100SetupTexture)( + } + + offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; +- dst = (CARD8*)(info->FB + offset); ++ dst = (uint8_t*)(info->FB + offset); + + /* Upload texture to card. */ + +@@ -500,7 +507,7 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( + ) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 colorformat, srccolor, blend_cntl; ++ uint32_t colorformat, srccolor, blend_cntl; + ACCEL_PREAMBLE(); + + blend_cntl = RadeonGetBlendCntl(op, dstFormat); +@@ -551,7 +558,7 @@ FUNC_NAME(R100SetupForCPUToScreenTexture) ( + ) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 colorformat, blend_cntl; ++ uint32_t colorformat, blend_cntl; + ACCEL_PREAMBLE(); + + blend_cntl = RadeonGetBlendCntl(op, dstFormat); +@@ -598,7 +605,7 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) ( + { + RADEONInfoPtr info = RADEONPTR(pScrn); + int byteshift; +- CARD32 fboffset; ++ uint32_t fboffset; + float l, t, r, b, fl, fr, ft, fb; + + ACCEL_PREAMBLE(); +@@ -710,22 +717,22 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) ( + + static Bool FUNC_NAME(R200SetupTexture)( + ScrnInfoPtr pScrn, +- CARD32 format, +- CARD8 *src, ++ uint32_t format, ++ uint8_t *src, + int src_pitch, + unsigned int width, + unsigned int height, + int flags) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD8 *dst; +- CARD32 tex_size = 0, txformat; ++ uint8_t *dst; ++ uint32_t tex_size = 0, txformat; + int dst_pitch, offset, size, tex_bytepp; + #ifdef ACCEL_CP +- CARD32 buf_pitch, dst_pitch_off; ++ uint32_t buf_pitch, dst_pitch_off; + int x, y; + unsigned int hpass; +- CARD8 *tmp_dst; ++ uint8_t *tmp_dst; + #endif + ACCEL_PREAMBLE(); + +@@ -769,7 +776,7 @@ static Bool FUNC_NAME(R200SetupTexture)( + info->texH[0] = height; + + offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; +- dst = (CARD8*)(info->FB + offset); ++ dst = (uint8_t*)(info->FB + offset); + + /* Upload texture to card. */ + +@@ -841,7 +848,7 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( + ) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 colorformat, srccolor, blend_cntl; ++ uint32_t colorformat, srccolor, blend_cntl; + ACCEL_PREAMBLE(); + + blend_cntl = RadeonGetBlendCntl(op, dstFormat); +@@ -893,7 +900,7 @@ FUNC_NAME(R200SetupForCPUToScreenTexture) ( + ) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 colorformat, blend_cntl; ++ uint32_t colorformat, blend_cntl; + ACCEL_PREAMBLE(); + + blend_cntl = RadeonGetBlendCntl(op, dstFormat); +@@ -941,7 +948,7 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) ( + { + RADEONInfoPtr info = RADEONPTR(pScrn); + int byteshift; +- CARD32 fboffset; ++ uint32_t fboffset; + float l, t, r, b, fl, fr, ft, fb; + ACCEL_PREAMBLE(); + diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index 329a834..5d153e7 100644 +index 329a834..cfa349d 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -46,6 +46,9 @@ @@ -10271,7 +13656,7 @@ index 329a834..5d153e7 100644 static Bool RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) { -@@ -60,7 +63,7 @@ RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) +@@ -60,18 +63,18 @@ RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) } else #endif { @@ -10280,15 +13665,30 @@ index 329a834..5d153e7 100644 return TRUE; else return FALSE; -@@ -223,7 +226,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + } + } + +-static __inline__ CARD32 F_TO_DW(float val) ++static __inline__ uint32_t F_TO_DW(float val) + { + union { + float f; +- CARD32 l; ++ uint32_t l; + } tmp; + tmp.f = val; + return tmp.l; +@@ -223,8 +226,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, left = (x1 >> 16) & ~1; npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; - pPriv->src_offset = pPriv->video_offset + info->fbLocation; +- pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch)); + pPriv->src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset; - pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch)); ++ pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch)); pPriv->src_pitch = dstPitch; pPriv->size = size; + pPriv->pDraw = pDraw; @@ -300,6 +303,16 @@ static XF86VideoEncodingRec DummyEncoding[1] = } }; @@ -10328,12 +13728,23 @@ index 329a834..5d153e7 100644 adapt->pFormats = Formats; adapt->nPorts = num_texture_ports; diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index e0f3bba..b0286a6 100644 +index e0f3bba..d5d1b1c 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c -@@ -80,16 +80,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - CARD32 txenable, colorpitch; - CARD32 blendcntl; +@@ -74,22 +74,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + { + RADEONInfoPtr info = RADEONPTR(pScrn); + PixmapPtr pPixmap = pPriv->pPixmap; +- CARD32 txformat; +- CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; +- CARD32 dst_offset, dst_pitch, dst_format; +- CARD32 txenable, colorpitch; +- CARD32 blendcntl; ++ uint32_t txformat; ++ uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; ++ uint32_t dst_offset, dst_pitch, dst_format; ++ uint32_t txenable, colorpitch; ++ uint32_t blendcntl; int dstxoff, dstyoff, pixel_shift; - VIDEO_PREAMBLE(); - @@ -10381,7 +13792,7 @@ index e0f3bba..b0286a6 100644 - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); + if (IS_R300_3D || IS_R500_3D) { -+ CARD32 output_fmt; ++ uint32_t output_fmt; switch (pPixmap->drawable.bitsPerPixel) { case 16: @@ -10827,29 +14238,517 @@ index e0f3bba..b0286a6 100644 #ifdef ACCEL_CP ADVANCE_RING(); +diff --git a/src/radeon_tv.c b/src/radeon_tv.c +index d5d1e9e..90020b3 100644 +--- a/src/radeon_tv.c ++++ b/src/radeon_tv.c +@@ -34,22 +34,22 @@ + + typedef struct + { +- CARD16 horResolution; +- CARD16 verResolution; ++ uint16_t horResolution; ++ uint16_t verResolution; + TVStd standard; +- CARD16 horTotal; +- CARD16 verTotal; +- CARD16 horStart; +- CARD16 horSyncStart; +- CARD16 verSyncStart; ++ uint16_t horTotal; ++ uint16_t verTotal; ++ uint16_t horStart; ++ uint16_t horSyncStart; ++ uint16_t verSyncStart; + unsigned defRestart; +- CARD16 crtcPLL_N; +- CARD8 crtcPLL_M; +- CARD8 crtcPLL_postDiv; ++ uint16_t crtcPLL_N; ++ uint8_t crtcPLL_M; ++ uint8_t crtcPLL_postDiv; + unsigned pixToTV; + } TVModeConstants; + +-static const CARD16 hor_timing_NTSC[] = ++static const uint16_t hor_timing_NTSC[] = + { + 0x0007, + 0x003f, +@@ -71,7 +71,7 @@ static const CARD16 hor_timing_NTSC[] = + 0 + }; + +-static const CARD16 vert_timing_NTSC[] = ++static const uint16_t vert_timing_NTSC[] = + { + 0x2001, + 0x200d, +@@ -89,7 +89,7 @@ static const CARD16 vert_timing_NTSC[] = + 0 + }; + +-static const CARD16 hor_timing_PAL[] = ++static const uint16_t hor_timing_PAL[] = + { + 0x0007, + 0x0058, +@@ -111,7 +111,7 @@ static const CARD16 hor_timing_PAL[] = + 0 + }; + +-static const CARD16 vert_timing_PAL[] = ++static const uint16_t vert_timing_PAL[] = + { + 0x2001, + 0x200c, +@@ -186,7 +186,7 @@ RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 savePLLTest; ++ uint32_t savePLLTest; + unsigned i; + unsigned j; + +@@ -215,12 +215,12 @@ RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, + + /* Write to TV FIFO RAM */ + static void +-RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr, +- CARD32 value) ++RADEONWriteTVFIFO(ScrnInfoPtr pScrn, uint16_t addr, ++ uint32_t value) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 tmp; ++ uint32_t tmp; + int i = 0; + + OUTREG(RADEON_TV_HOST_WRITE_DATA, value); +@@ -241,12 +241,12 @@ RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr, + } + + /* Read from TV FIFO RAM */ +-static CARD32 +-RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr) ++static uint32_t ++RADEONReadTVFIFO(ScrnInfoPtr pScrn, uint16_t addr) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 tmp; ++ uint32_t tmp; + int i = 0; + + OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr); +@@ -269,10 +269,10 @@ RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr) + /* Get FIFO addresses of horizontal & vertical code timing tables from + * settings of uv_adr register. + */ +-static CARD16 +-RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr) ++static uint16_t ++RADEONGetHTimingTablesAddr(uint32_t tv_uv_adr) + { +- CARD16 hTable; ++ uint16_t hTable; + + switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { + case 0: +@@ -292,10 +292,10 @@ RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr) + return hTable; + } + +-static CARD16 +-RADEONGetVTimingTablesAddr(CARD32 tv_uv_adr) ++static uint16_t ++RADEONGetVTimingTablesAddr(uint32_t tv_uv_adr) + { +- CARD16 vTable; ++ uint16_t vTable; + + switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { + case 0: +@@ -321,9 +321,9 @@ RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD16 hTable; +- CARD16 vTable; +- CARD32 tmp; ++ uint16_t hTable; ++ uint16_t vTable; ++ uint32_t tmp; + unsigned i; + + OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr); +@@ -331,14 +331,14 @@ RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) + vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr); + + for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) { +- tmp = ((CARD32)restore->h_code_timing[ i ] << 14) | ((CARD32)restore->h_code_timing[ i + 1 ]); ++ tmp = ((uint32_t)restore->h_code_timing[ i ] << 14) | ((uint32_t)restore->h_code_timing[ i + 1 ]); + RADEONWriteTVFIFO(pScrn, hTable, tmp); + if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0) + break; + } + + for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, vTable++) { +- tmp = ((CARD32)restore->v_code_timing[ i + 1 ] << 14) | ((CARD32)restore->v_code_timing[ i ]); ++ tmp = ((uint32_t)restore->v_code_timing[ i + 1 ] << 14) | ((uint32_t)restore->v_code_timing[ i ]); + RADEONWriteTVFIFO(pScrn, vTable, tmp); + if (restore->v_code_timing[ i ] == 0 || restore->v_code_timing[ i + 1 ] == 0) + break; +@@ -485,9 +485,9 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD16 hTable; +- CARD16 vTable; +- CARD32 tmp; ++ uint16_t hTable; ++ uint16_t vTable; ++ uint32_t tmp; + unsigned i; + + save->tv_uv_adr = INREG(RADEON_TV_UV_ADR); +@@ -511,8 +511,8 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) + + for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2) { + tmp = RADEONReadTVFIFO(pScrn, hTable--); +- save->h_code_timing[ i ] = (CARD16)((tmp >> 14) & 0x3fff); +- save->h_code_timing[ i + 1 ] = (CARD16)(tmp & 0x3fff); ++ save->h_code_timing[ i ] = (uint16_t)((tmp >> 14) & 0x3fff); ++ save->h_code_timing[ i + 1 ] = (uint16_t)(tmp & 0x3fff); + + if (save->h_code_timing[ i ] == 0 || save->h_code_timing[ i + 1 ] == 0) + break; +@@ -520,8 +520,8 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) + + for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2) { + tmp = RADEONReadTVFIFO(pScrn, vTable++); +- save->v_code_timing[ i ] = (CARD16)(tmp & 0x3fff); +- save->v_code_timing[ i + 1 ] = (CARD16)((tmp >> 14) & 0x3fff); ++ save->v_code_timing[ i ] = (uint16_t)(tmp & 0x3fff); ++ save->v_code_timing[ i + 1 ] = (uint16_t)((tmp >> 14) & 0x3fff); + + if (save->v_code_timing[ i ] == 0 || save->v_code_timing[ i + 1 ] == 0) + break; +@@ -588,10 +588,10 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, + unsigned fTotal; + int vOffset; + int hOffset; +- CARD16 p1; +- CARD16 p2; ++ uint16_t p1; ++ uint16_t p2; + Bool hChanged; +- CARD16 hInc; ++ uint16_t hInc; + const TVModeConstants *constPtr; + + /* FIXME: need to revisit this when we add more modes */ +@@ -629,8 +629,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, + } + + +- p1 = (CARD16)((int)p1 + hOffset); +- p2 = (CARD16)((int)p2 - hOffset); ++ p1 = (uint16_t)((int)p1 + hOffset); ++ p2 = (uint16_t)((int)p2 - hOffset); + + hChanged = (p1 != save->h_code_timing[ H_TABLE_POS1 ] || + p2 != save->h_code_timing[ H_TABLE_POS2 ]); +@@ -675,14 +675,14 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || + radeon_output->tvStd == TV_STD_PAL_M) +- hInc = (CARD16)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / ++ hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / + (radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); + else +- hInc = (CARD16)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / ++ hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / + (radeon_output->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); + + save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) | +- ((CARD32)hInc << RADEON_H_INC_SHIFT); ++ ((uint32_t)hInc << RADEON_H_INC_SHIFT); + + ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , radeon_output->hSize , hInc); + +@@ -698,10 +698,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned i; + unsigned long vert_space, flicker_removal; +- CARD32 tmp; ++ uint32_t tmp; + const TVModeConstants *constPtr; +- const CARD16 *hor_timing; +- const CARD16 *vert_timing; ++ const uint16_t *hor_timing; ++ const uint16_t *vert_timing; + + + /* FIXME: need to revisit this when we add more modes */ diff --git a/src/radeon_video.c b/src/radeon_video.c -index 7502e1e..216cd65 100644 +index 7502e1e..4a5d6e8 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c -@@ -285,14 +285,15 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -285,14 +285,22 @@ void RADEONInitVideo(ScreenPtr pScreen) RADEONInitOffscreenImages(pScreen); } - if (info->ChipFamily != CHIP_FAMILY_RS400) { +- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); +- if (texturedAdaptor != NULL) { +- adaptors[num_adaptors++] = texturedAdaptor; +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); + if (info->ChipFamily != CHIP_FAMILY_RV250) { - texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); - if (texturedAdaptor != NULL) { - adaptors[num_adaptors++] = texturedAdaptor; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); ++ if ((info->ChipFamily < CHIP_FAMILY_RS400) ++#ifdef XF86DRI ++ || (info->directRenderingEnabled) ++#endif ++ ) { ++ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); ++ if (texturedAdaptor != NULL) { ++ adaptors[num_adaptors++] = texturedAdaptor; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); ++ } else ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); } else - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); - } ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/IGP\n"); + } else + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n"); if(num_adaptors) xf86XVScreenInit(pScreen, adaptors, num_adaptors); -@@ -2159,6 +2160,13 @@ RADEONCopyData( +@@ -550,59 +558,59 @@ static REF_TRANSFORM trans[2] = + /* Gamma curve definition for preset gammas */ + typedef struct tagGAMMA_CURVE_R100 + { +- CARD32 GAMMA_0_F_SLOPE; +- CARD32 GAMMA_0_F_OFFSET; +- CARD32 GAMMA_10_1F_SLOPE; +- CARD32 GAMMA_10_1F_OFFSET; +- CARD32 GAMMA_20_3F_SLOPE; +- CARD32 GAMMA_20_3F_OFFSET; +- CARD32 GAMMA_40_7F_SLOPE; +- CARD32 GAMMA_40_7F_OFFSET; +- CARD32 GAMMA_380_3BF_SLOPE; +- CARD32 GAMMA_380_3BF_OFFSET; +- CARD32 GAMMA_3C0_3FF_SLOPE; +- CARD32 GAMMA_3C0_3FF_OFFSET; ++ uint32_t GAMMA_0_F_SLOPE; ++ uint32_t GAMMA_0_F_OFFSET; ++ uint32_t GAMMA_10_1F_SLOPE; ++ uint32_t GAMMA_10_1F_OFFSET; ++ uint32_t GAMMA_20_3F_SLOPE; ++ uint32_t GAMMA_20_3F_OFFSET; ++ uint32_t GAMMA_40_7F_SLOPE; ++ uint32_t GAMMA_40_7F_OFFSET; ++ uint32_t GAMMA_380_3BF_SLOPE; ++ uint32_t GAMMA_380_3BF_OFFSET; ++ uint32_t GAMMA_3C0_3FF_SLOPE; ++ uint32_t GAMMA_3C0_3FF_OFFSET; + float OvGammaCont; + } GAMMA_CURVE_R100; + + typedef struct tagGAMMA_CURVE_R200 + { +- CARD32 GAMMA_0_F_SLOPE; +- CARD32 GAMMA_0_F_OFFSET; +- CARD32 GAMMA_10_1F_SLOPE; +- CARD32 GAMMA_10_1F_OFFSET; +- CARD32 GAMMA_20_3F_SLOPE; +- CARD32 GAMMA_20_3F_OFFSET; +- CARD32 GAMMA_40_7F_SLOPE; +- CARD32 GAMMA_40_7F_OFFSET; +- CARD32 GAMMA_80_BF_SLOPE; +- CARD32 GAMMA_80_BF_OFFSET; +- CARD32 GAMMA_C0_FF_SLOPE; +- CARD32 GAMMA_C0_FF_OFFSET; +- CARD32 GAMMA_100_13F_SLOPE; +- CARD32 GAMMA_100_13F_OFFSET; +- CARD32 GAMMA_140_17F_SLOPE; +- CARD32 GAMMA_140_17F_OFFSET; +- CARD32 GAMMA_180_1BF_SLOPE; +- CARD32 GAMMA_180_1BF_OFFSET; +- CARD32 GAMMA_1C0_1FF_SLOPE; +- CARD32 GAMMA_1C0_1FF_OFFSET; +- CARD32 GAMMA_200_23F_SLOPE; +- CARD32 GAMMA_200_23F_OFFSET; +- CARD32 GAMMA_240_27F_SLOPE; +- CARD32 GAMMA_240_27F_OFFSET; +- CARD32 GAMMA_280_2BF_SLOPE; +- CARD32 GAMMA_280_2BF_OFFSET; +- CARD32 GAMMA_2C0_2FF_SLOPE; +- CARD32 GAMMA_2C0_2FF_OFFSET; +- CARD32 GAMMA_300_33F_SLOPE; +- CARD32 GAMMA_300_33F_OFFSET; +- CARD32 GAMMA_340_37F_SLOPE; +- CARD32 GAMMA_340_37F_OFFSET; +- CARD32 GAMMA_380_3BF_SLOPE; +- CARD32 GAMMA_380_3BF_OFFSET; +- CARD32 GAMMA_3C0_3FF_SLOPE; +- CARD32 GAMMA_3C0_3FF_OFFSET; ++ uint32_t GAMMA_0_F_SLOPE; ++ uint32_t GAMMA_0_F_OFFSET; ++ uint32_t GAMMA_10_1F_SLOPE; ++ uint32_t GAMMA_10_1F_OFFSET; ++ uint32_t GAMMA_20_3F_SLOPE; ++ uint32_t GAMMA_20_3F_OFFSET; ++ uint32_t GAMMA_40_7F_SLOPE; ++ uint32_t GAMMA_40_7F_OFFSET; ++ uint32_t GAMMA_80_BF_SLOPE; ++ uint32_t GAMMA_80_BF_OFFSET; ++ uint32_t GAMMA_C0_FF_SLOPE; ++ uint32_t GAMMA_C0_FF_OFFSET; ++ uint32_t GAMMA_100_13F_SLOPE; ++ uint32_t GAMMA_100_13F_OFFSET; ++ uint32_t GAMMA_140_17F_SLOPE; ++ uint32_t GAMMA_140_17F_OFFSET; ++ uint32_t GAMMA_180_1BF_SLOPE; ++ uint32_t GAMMA_180_1BF_OFFSET; ++ uint32_t GAMMA_1C0_1FF_SLOPE; ++ uint32_t GAMMA_1C0_1FF_OFFSET; ++ uint32_t GAMMA_200_23F_SLOPE; ++ uint32_t GAMMA_200_23F_OFFSET; ++ uint32_t GAMMA_240_27F_SLOPE; ++ uint32_t GAMMA_240_27F_OFFSET; ++ uint32_t GAMMA_280_2BF_SLOPE; ++ uint32_t GAMMA_280_2BF_OFFSET; ++ uint32_t GAMMA_2C0_2FF_SLOPE; ++ uint32_t GAMMA_2C0_2FF_OFFSET; ++ uint32_t GAMMA_300_33F_SLOPE; ++ uint32_t GAMMA_300_33F_OFFSET; ++ uint32_t GAMMA_340_37F_SLOPE; ++ uint32_t GAMMA_340_37F_OFFSET; ++ uint32_t GAMMA_380_3BF_SLOPE; ++ uint32_t GAMMA_380_3BF_OFFSET; ++ uint32_t GAMMA_3C0_3FF_SLOPE; ++ uint32_t GAMMA_3C0_3FF_OFFSET; + float OvGammaCont; + } GAMMA_CURVE_R200; + +@@ -679,9 +687,9 @@ static GAMMA_CURVE_R100 gamma_curve_r100[8] = + static GAMMA_CURVE_R200 gamma_curve_r200[8] = + { + /* Gamma 1.0 */ +- {0x00000040, 0x00000000, +- 0x00000040, 0x00000020, +- 0x00000080, 0x00000040, ++ {0x00000100, 0x00000000, ++ 0x00000100, 0x00000020, ++ 0x00000100, 0x00000040, + 0x00000100, 0x00000080, + 0x00000100, 0x00000100, + 0x00000100, 0x00000100, +@@ -841,16 +849,19 @@ static GAMMA_CURVE_R200 gamma_curve_r200[8] = + }; + + static void +-RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 gamma) ++RADEONSetOverlayGamma(ScrnInfoPtr pScrn, uint32_t gamma) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 ov0_scale_cntl; ++ uint32_t ov0_scale_cntl; + + /* Set gamma */ + RADEONWaitForIdleMMIO(pScrn); + ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; +- OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 0x00000005)); ++ if (info->ChipFamily < CHIP_FAMILY_R200) ++ OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 5)); ++ else ++ OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl); + + /* Load gamma curve adjustments */ + if (info->ChipFamily >= CHIP_FAMILY_R200) { +@@ -957,8 +968,8 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, + float red_intensity, + float green_intensity, + float blue_intensity, +- CARD32 ref, +- CARD32 user_gamma) ++ uint32_t ref, ++ uint32_t user_gamma) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +@@ -975,11 +986,11 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, + float Loff = 64.0; + float Coff = 512.0f; + +- CARD32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; +- CARD32 dwOvRCb, dwOvRCr; +- CARD32 dwOvGCb, dwOvGCr; +- CARD32 dwOvBCb, dwOvBCr; +- CARD32 gamma = 0; ++ uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; ++ uint32_t dwOvRCb, dwOvRCr; ++ uint32_t dwOvGCb, dwOvGCr; ++ uint32_t dwOvBCb, dwOvBCr; ++ uint32_t gamma = 0; + + if (ref >= 2) + return; +@@ -1143,16 +1154,16 @@ static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, + /* not yet supported */ + } + +-static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) ++static void RADEONSetColorKey(ScrnInfoPtr pScrn, uint32_t colorKey) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 min, max; +- CARD8 r, g, b; ++ uint32_t min, max; ++ uint8_t r, g, b; + + if (info->CurrentLayout.depth > 8) + { +- CARD32 rbits, gbits, bbits; ++ uint32_t rbits, gbits, bbits; + + rbits = (colorKey & pScrn->mask.red) >> pScrn->offset.red; + gbits = (colorKey & pScrn->mask.green) >> pScrn->offset.green; +@@ -1164,7 +1175,7 @@ static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) + } + else + { +- CARD32 bits; ++ uint32_t bits; + + bits = colorKey & ((1 << info->CurrentLayout.depth) - 1); + r = bits; +@@ -1307,7 +1318,7 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) + RADEONPLLPtr pll = &(info->pll); + TheatrePtr t; + +- CARD8 a; ++ uint8_t a; + int i; + + pPriv->theatre = NULL; +@@ -1401,7 +1412,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) + XF86VideoAdaptorPtr adapt; + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONPortPrivPtr pPriv; +- CARD32 dot_clock; ++ uint32_t dot_clock; + int ecp; + + if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn))) +@@ -2159,22 +2170,22 @@ RADEONCopyData( unsigned int bpp ){ RADEONInfoPtr info = RADEONPTR(pScrn); @@ -10863,7 +14762,11 @@ index 7502e1e..216cd65 100644 #ifdef XF86DRI if ( info->directRenderingEnabled && info->DMAForXv ) -@@ -2168,13 +2176,6 @@ RADEONCopyData( + { +- CARD8 *buf; +- CARD32 bufPitch, dstPitchOff; ++ uint8_t *buf; ++ uint32_t bufPitch, dstPitchOff; int x, y; unsigned int hpass; @@ -10877,38 +14780,627 @@ index 7502e1e..216cd65 100644 RADEONHostDataParams( pScrn, dst, dstPitch, bpp, &dstPitchOff, &x, &y ); while ( (buf = RADEONHostDataBlit( pScrn, bpp, w, dstPitchOff, &bufPitch, +@@ -2235,21 +2246,21 @@ RADEONCopyRGB24Data( + unsigned int h, + unsigned int w + ){ +- CARD32 *dptr; +- CARD8 *sptr; ++ uint32_t *dptr; ++ uint8_t *sptr; + int i,j; + RADEONInfoPtr info = RADEONPTR(pScrn); + #ifdef XF86DRI + + if ( info->directRenderingEnabled && info->DMAForXv ) + { +- CARD32 bufPitch, dstPitchOff; ++ uint32_t bufPitch, dstPitchOff; + int x, y; + unsigned int hpass; + + RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y ); + +- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, ++ while ( (dptr = ( uint32_t* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, + &bufPitch, x, &y, &h, + &hpass )) ) + { +@@ -2282,7 +2293,7 @@ RADEONCopyRGB24Data( + #endif + + for (j = 0; j < h; j++) { +- dptr = (CARD32 *)(dst + j * dstPitch); ++ dptr = (uint32_t *)(dst + j * dstPitch); + sptr = src + j * srcPitch; + + for (i = 0; i < w; i++, sptr += 3) { +@@ -2333,8 +2344,8 @@ RADEONCopyMungedData( + + if ( info->directRenderingEnabled && info->DMAForXv ) + { +- CARD8 *buf; +- CARD32 y = 0, bufPitch, dstPitchOff; ++ uint8_t *buf; ++ uint32_t y = 0, bufPitch, dstPitchOff; + int blitX, blitY; + unsigned int hpass; + +@@ -2365,8 +2376,8 @@ RADEONCopyMungedData( + else + #endif /* XF86DRI */ + { +- CARD32 *dst; +- CARD8 *s1, *s2, *s3; ++ uint32_t *dst; ++ uint8_t *s1, *s2, *s3; + int i, j; + + #if X_BYTE_ORDER == X_BIG_ENDIAN +@@ -2420,7 +2431,7 @@ RADEONCopyMungedData( + * is measured in bytes, and the offset from the beginning of card space is + * returned. + */ +-CARD32 ++uint32_t + RADEONAllocateMemory( + ScrnInfoPtr pScrn, + void **mem_struct, +@@ -2542,7 +2553,7 @@ RADEONDisplayVideo( + RADEONInfoPtr info = RADEONPTR(pScrn); + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; ++ uint32_t v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; + double h_inc_d; + int p1_h_accum_init, p23_h_accum_init; + int p1_v_accum_init, p23_v_accum_init; +@@ -2552,12 +2563,12 @@ RADEONDisplayVideo( + int y_mult; + int x_off; + int y_off; +- CARD32 scaler_src; +- CARD32 dot_clock; ++ uint32_t scaler_src; ++ uint32_t dot_clock; + int is_rgb; + int is_planar; + int i; +- CARD32 scale_cntl; ++ uint32_t scale_cntl; + double dsr; + int tap_set; + int predownscale=0; +@@ -2873,7 +2884,7 @@ RADEONDisplayVideo( + + + static void +-RADEONFillKeyHelper(DrawablePtr pDraw, CARD32 colorKey, RegionPtr clipBoxes) ++RADEONFillKeyHelper(DrawablePtr pDraw, uint32_t colorKey, RegionPtr clipBoxes) + { + #if HAVE_XV_DRAWABLE_HELPER + xf86XVFillKeyHelperDrawable(pDraw, colorKey, clipBoxes); +@@ -2906,7 +2917,7 @@ RADEONPutImage( + int top, left, npixels, nlines, bpp; + int idconv = id; + BoxRec dstBox; +- CARD32 tmp; ++ uint32_t tmp; + xf86CrtcPtr crtc; + + /* +@@ -2979,7 +2990,8 @@ RADEONPutImage( + case FOURCC_I420: + /* it seems rs4xx chips (all of them???) either can't handle planar + yuv at all or would need some unknown different setup. */ +- if (info->ChipFamily != CHIP_FAMILY_RS400) { ++ if ((info->ChipFamily != CHIP_FAMILY_RS400) && ++ (info->ChipFamily != CHIP_FAMILY_RS480)) { + /* need 16bytes alignment for u,v plane, so 2 times that for width + but blitter needs 64bytes alignment. 128byte is a waste but dstpitch + for uv planes needs to be dstpitch yplane >> 1 for now. */ +@@ -3462,7 +3474,7 @@ RADEONPutVideo( + int srcPitch, srcPitch2, dstPitch; + int bpp; + BoxRec dstBox; +- CARD32 id, display_base; ++ uint32_t id, display_base; + int width, height; + int mult; + int vbi_line_width, vbi_start, vbi_end; +diff --git a/src/radeon_video.h b/src/radeon_video.h +index f897e07..096de37 100644 +--- a/src/radeon_video.h ++++ b/src/radeon_video.h +@@ -15,8 +15,8 @@ + + /* Xvideo port struct */ + typedef struct { +- CARD32 transform_index; +- CARD32 gamma; /* gamma value x 1000 */ ++ uint32_t transform_index; ++ uint32_t gamma; /* gamma value x 1000 */ + int brightness; + int saturation; + int hue; +@@ -32,17 +32,17 @@ typedef struct { + + /* i2c bus and devices */ + I2CBusPtr i2c; +- CARD32 radeon_i2c_timing; +- CARD32 radeon_M; +- CARD32 radeon_N; +- CARD32 i2c_status; +- CARD32 i2c_cntl; ++ uint32_t radeon_i2c_timing; ++ uint32_t radeon_M; ++ uint32_t radeon_N; ++ uint32_t i2c_status; ++ uint32_t i2c_cntl; + + FI1236Ptr fi1236; +- CARD8 tuner_type; ++ uint8_t tuner_type; + MSP3430Ptr msp3430; + TDA9885Ptr tda9885; +- UDA1380Ptr uda1380; ++ UDA1380Ptr uda1380; + + /* VIP bus and devices */ + GENERIC_BUS_Ptr VIP; +@@ -50,12 +50,12 @@ typedef struct { + + Bool video_stream_active; + int encoding; +- CARD32 frequency; ++ uint32_t frequency; + int volume; + Bool mute; + int sap_channel; + int v; +- CARD32 adjustment; /* general purpose variable */ ++ uint32_t adjustment; /* general purpose variable */ + + #define METHOD_BOB 0 + #define METHOD_SINGLE 1 +@@ -74,14 +74,14 @@ typedef struct { + Bool doubleBuffer; + unsigned char currentBuffer; + RegionRec clip; +- CARD32 colorKey; +- CARD32 videoStatus; ++ uint32_t colorKey; ++ uint32_t videoStatus; + Time offTime; + Time freeTime; + Bool autopaint_colorkey; + xf86CrtcPtr desired_crtc; + +- int size; ++ int size; + #ifdef USE_EXA + ExaOffscreenArea *off_screen; + #endif +@@ -96,9 +96,9 @@ typedef struct { + DrawablePtr pDraw; + PixmapPtr pPixmap; + +- CARD32 src_offset; +- CARD32 src_pitch; +- CARD8 *src_addr; ++ uint32_t src_offset; ++ uint32_t src_pitch; ++ uint8_t *src_addr; + + int id; + int src_w, src_h, dst_w, dst_h; +@@ -113,7 +113,7 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); + void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); + void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); + +-CARD32 ++uint32_t + RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size); + void + RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct); +diff --git a/src/radeon_vip.c b/src/radeon_vip.c +index 7ee4ab5..05b90f1 100644 +--- a/src/radeon_vip.c ++++ b/src/radeon_vip.c +@@ -46,13 +46,13 @@ static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2 + } + } + +-static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b) ++static uint32_t RADEONVIP_idle(GENERIC_BUS_Ptr b) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- CARD32 timeout; ++ uint32_t timeout; + + RADEONWaitForIdleMMIO(pScrn); + timeout = INREG(RADEON_VIPH_TIMEOUT_STAT); +@@ -67,13 +67,13 @@ static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b) + return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ; + } + +-static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel) ++static uint32_t RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, uint8_t channel) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- CARD32 timeout; ++ uint32_t timeout; + + RADEONWaitForIdleMMIO(pScrn); + timeout = INREG(VIPH_TIMEOUT_STAT); +@@ -105,12 +105,12 @@ static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel) + } \ + } + +-static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) ++static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 status,tmp; ++ uint32_t status,tmp; + + if((count!=1) && (count!=2) && (count!=4)) + { +@@ -152,13 +152,13 @@ static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD + RADEONWaitForIdleMMIO(pScrn); + switch(count){ + case 1: +- *buffer=(CARD8)(INREG(RADEON_VIPH_REG_DATA) & 0xff); ++ *buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DATA) & 0xff); + break; + case 2: +- *(CARD16 *)buffer=(CARD16) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); ++ *(uint16_t *)buffer=(uint16_t) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); + break; + case 4: +- *(CARD32 *)buffer=(CARD32) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); ++ *(uint32_t *)buffer=(uint32_t) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); + break; + } + VIP_WAIT_FOR_IDLE(); +@@ -171,12 +171,12 @@ static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD + return TRUE; + } + +-static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) ++static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 status,tmp; ++ uint32_t status,tmp; + + if(count!=1) + { +@@ -222,13 +222,13 @@ static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, + RADEONWaitForIdleMMIO(pScrn); + switch(count){ + case 1: +- *buffer=(CARD8)(INREG(VIPH_REG_DATA) & 0xff); ++ *buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff); + break; + case 2: +- *(CARD16 *)buffer=(CARD16) (INREG(VIPH_REG_DATA) & 0xffff); ++ *(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff); + break; + case 4: +- *(CARD32 *)buffer=(CARD32) ( INREG(VIPH_REG_DATA) & 0xffffffff); ++ *(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff); + break; + } + while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff))); +@@ -245,13 +245,13 @@ static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, + } + + +-static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) ++static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- CARD32 status; ++ uint32_t status; + + + if((count!=4)) +@@ -269,7 +269,7 @@ static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CAR + RADEONWaitForFifo(pScrn, 2); + switch(count){ + case 4: +- OUTREG(RADEON_VIPH_REG_DATA, *(CARD32 *)buffer); ++ OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer); + break; + } + write_mem_barrier(); +@@ -278,14 +278,14 @@ static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CAR + return TRUE; + } + +-static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) ++static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- CARD32 status; +- CARD32 i; ++ uint32_t status; ++ uint32_t i; + + RADEONWaitForFifo(pScrn, 2); + OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000); +@@ -300,7 +300,7 @@ static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count + RADEONWaitForFifo(pScrn, 2); + for (i = 0; i < count; i+=4) + { +- OUTREG(VIPH_REG_DATA, *(CARD32*)(buffer + i)); ++ OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i)); + write_mem_barrier(); + while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f))); + if(VIP_IDLE != status) diff --git a/src/theatre.c b/src/theatre.c -index a5aadfb..a4d3c10 100644 +index a5aadfb..ad055c5 100644 --- a/src/theatre.c +++ b/src/theatre.c -@@ -28,6 +28,8 @@ static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) +@@ -12,29 +12,31 @@ + #undef write + #undef ioctl + +-static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) ++static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); ++ return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); + } + +-static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) ++static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); ++ return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); + } + + #define RT_regr(reg,data) theatre_read(t,(reg),(data)) #define RT_regw(reg,data) theatre_write(t,(reg),(data)) #define VIP_TYPE "ATI VIP BUS" -+static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard); -+static void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector); ++static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard); ++static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector); #if 0 TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) -@@ -793,7 +795,7 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) + { + TheatrePtr t; +- CARD32 i; +- CARD32 val; ++ uint32_t i; ++ uint32_t val; + char s[20]; + + b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); +@@ -49,10 +51,10 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) + t->theatre_num = -1; + t->mode=MODE_UNINITIALIZED; + +- b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val); ++ b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); + for(i=0;i<4;i++) + { +- if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) ++ if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) + { + if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n",i,val); + if(t->theatre_num>=0)continue; /* already found one instance */ +@@ -171,7 +173,7 @@ fld_V_INT_LENGTH, + fld_CRDR_ACTIVE_GAIN, + fld_CBDB_ACTIVE_GAIN, + fld_DVS_DIRECTION, +-fld_DVS_VBI_CARD8_SWAP, ++fld_DVS_VBI_UINT8_SWAP, + fld_DVS_CLK_SELECT, + fld_CONTINUOUS_STREAM, + fld_DVSOUT_CLK_DRV, +@@ -253,17 +255,17 @@ regRT_MAX_REGS + + + typedef struct { +- CARD8 size; +- CARD32 fld_id; +- CARD32 dwRegAddrLSBs; +- CARD32 dwFldOffsetLSBs; +- CARD32 dwMaskLSBs; +- CARD32 addr2; +- CARD32 offs2; +- CARD32 mask2; +- CARD32 dwCurrValue; +- CARD32 rw; +- } RTREGMAP; ++ uint8_t size; ++ uint32_t fld_id; ++ uint32_t dwRegAddrLSBs; ++ uint32_t dwFldOffsetLSBs; ++ uint32_t dwMaskLSBs; ++ uint32_t addr2; ++ uint32_t offs2; ++ uint32_t mask2; ++ uint32_t dwCurrValue; ++ uint32_t rw; ++} RTREGMAP; + + #define READONLY 1 + #define WRITEONLY 2 +@@ -350,7 +352,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ + {10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, + {10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, + {1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, +-{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE }, ++{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, + {1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, + {1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, + {1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, +@@ -429,7 +431,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ + }; + + /* Rage Theatre's register fields default values: */ +-CARD32 RT_RegDef[regRT_MAX_REGS]= ++uint32_t RT_RegDef[regRT_MAX_REGS]= + { + fld_tmpReg1_def, + fld_tmpReg2_def, +@@ -507,7 +509,7 @@ fld_V_INT_LENGTH_def, + fld_CRDR_ACTIVE_GAIN_def, + fld_CBDB_ACTIVE_GAIN_def, + fld_DVS_DIRECTION_def, +-fld_DVS_VBI_CARD8_SWAP_def, ++fld_DVS_VBI_UINT8_SWAP_def, + fld_DVS_CLK_SELECT_def, + fld_CONTINUOUS_STREAM_def, + fld_DVSOUT_CLK_DRV_def, +@@ -586,16 +588,16 @@ fld_GPIO_6_OUT_def, + }; + + /**************************************************************************** +- * WriteRT_fld (CARD32 dwReg, CARD32 dwData) * ++ * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * + * Function: Writes a register field within Rage Theatre * +- * Inputs: CARD32 dwReg = register field to be written * +- * CARD32 dwData = data that will be written to the reg field * ++ * Inputs: uint32_t dwReg = register field to be written * ++ * uint32_t dwData = data that will be written to the reg field * + * Outputs: NONE * + ****************************************************************************/ +-static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) ++static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) + { +- CARD32 dwResult=0; +- CARD32 dwValue=0; ++ uint32_t dwResult=0; ++ uint32_t dwValue=0; + + if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) + { +@@ -615,14 +617,14 @@ static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) + } /* WriteRT_fld ()... */ + + /**************************************************************************** +- * ReadRT_fld (CARD32 dwReg) * ++ * ReadRT_fld (uint32_t dwReg) * + * Function: Reads a register field within Rage Theatre * +- * Inputs: CARD32 dwReg = register field to be read * +- * Outputs: CARD32 - value read from register field * ++ * Inputs: uint32_t dwReg = register field to be read * ++ * Outputs: uint32_t - value read from register field * + ****************************************************************************/ +-static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) ++static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) + { +- CARD32 dwResult=0; ++ uint32_t dwResult=0; + + if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) + { +@@ -641,15 +643,15 @@ static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) + #define ReadRT_fld(a) ReadRT_fld1(t,(a)) + + /**************************************************************************** +- * RT_SetVINClock (CARD16 wStandard) * ++ * RT_SetVINClock (uint16_t wStandard) * + * Function: to set the VIN clock for the selected standard * +- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * + * Outputs: NONE * + ****************************************************************************/ +-static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) ++static void RT_SetVINClock(TheatrePtr t, uint16_t wStandard) + { +- CARD32 dwM0=0, dwN0=0, dwP=0; +- CARD8 ref_freq; ++ uint32_t dwM0=0, dwN0=0, dwP=0; ++ uint8_t ref_freq; + + /* Determine the reference frequency first. This can be obtained + from the MMTABLE.video_decoder_type field (bits 4:7) +@@ -657,9 +659,9 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) + 27 or 29.49 MHz. */ + /* + R128ReadBIOS(0x48, +- (CARD8 *)&bios_header, sizeof(bios_header)); ++ (uint8_t *)&bios_header, sizeof(bios_header)); + R128ReadBIOS(bios_header + 0x30, +- (CARD8 *)&pll_info_block, sizeof(pll_info_block)); ++ (uint8_t *)&pll_info_block, sizeof(pll_info_block)); + + R128ReadBIOS(pll_info_block+0x07, &video_decoder_type, sizeof(video_decoder_type)); + */ +@@ -793,9 +795,9 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) * Inputs: int hue - the hue value to be set. * * Outputs: NONE * ****************************************************************************/ -void RT_SetTint (TheatrePtr t, int hue) +_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) { - CARD32 nhue = 0; - -@@ -846,7 +848,7 @@ void RT_SetTint (TheatrePtr t, int hue) +- CARD32 nhue = 0; ++ uint32_t nhue = 0; + + t->iHue=hue; + /* Scale hue value from -1000<->1000 to -180<->180 */ +@@ -822,11 +824,11 @@ void RT_SetTint (TheatrePtr t, int hue) + case (DEC_SECAM): + if (hue >= 0) + { +- nhue = (CARD32) (256 * hue)/360; ++ nhue = (uint32_t) (256 * hue)/360; + } + else + { +- nhue = (CARD32) (256 * (hue + 360))/360; ++ nhue = (uint32_t) (256 * (hue + 360))/360; + } + break; + +@@ -846,9 +848,9 @@ void RT_SetTint (TheatrePtr t, int hue) * Inputs: int Saturation - the saturation value to be set. * * Outputs: NONE * ****************************************************************************/ -void RT_SetSaturation (TheatrePtr t, int Saturation) +_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) { - CARD16 wSaturation_V, wSaturation_U; +- CARD16 wSaturation_V, wSaturation_U; ++ uint16_t wSaturation_V, wSaturation_U; double dbSaturation = 0, dbCrGain = 0, dbCbGain = 0; -@@ -893,7 +895,7 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) + + /* VALIDATE SATURATION LEVEL */ +@@ -873,8 +875,8 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) + + CalculateCrCbGain (t, &dbCrGain, &dbCbGain, t->wStandard); + +- wSaturation_U = (CARD16) ((dbCrGain * dbSaturation * 128.0) + 0.5); +- wSaturation_V = (CARD16) ((dbCbGain * dbSaturation * 128.0) + 0.5); ++ wSaturation_U = (uint16_t) ((dbCrGain * dbSaturation * 128.0) + 0.5); ++ wSaturation_V = (uint16_t) ((dbCbGain * dbSaturation * 128.0) + 0.5); + + /* SET SATURATION LEVEL */ + WriteRT_fld (fld_CRDR_ACTIVE_GAIN, wSaturation_U); +@@ -893,14 +895,14 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) * Inputs: int Brightness - the brightness value to be set. * * Outputs: NONE * ****************************************************************************/ @@ -10917,16 +15409,40 @@ index a5aadfb..a4d3c10 100644 { double dbSynctipRef0=0, dbContrast=1; -@@ -967,7 +969,7 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) - * Inputs: CARD16 wSharpness - the sharpness value to be set. * + double dbYgain=0; + double dbBrightness=0; + double dbSetup=0; +- CARD16 wBrightness=0; ++ uint16_t wBrightness=0; + + /* VALIDATE BRIGHTNESS LEVEL */ + if (Brightness < -1000) +@@ -950,7 +952,7 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) + break; + } + +- wBrightness = (CARD16) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); ++ wBrightness = (uint16_t) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); + + WriteRT_fld (fld_LP_BRIGHTNESS, wBrightness); + +@@ -962,12 +964,12 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) + + + /**************************************************************************** +- * RT_SetSharpness (CARD16 wSharpness) * ++ * RT_SetSharpness (uint16_t wSharpness) * + * Function: sets the sharpness level for the Rage Theatre video in * +- * Inputs: CARD16 wSharpness - the sharpness value to be set. * ++ * Inputs: uint16_t wSharpness - the sharpness value to be set. * * Outputs: NONE * ****************************************************************************/ -void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) -+_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) ++_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) { switch (wSharpness) { -@@ -993,7 +995,7 @@ void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) +@@ -993,11 +995,11 @@ void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) * Inputs: int Contrast - the contrast value to be set. * * Outputs: NONE * ****************************************************************************/ @@ -10935,60 +15451,418 @@ index a5aadfb..a4d3c10 100644 { double dbSynctipRef0=0, dbContrast=0; double dbYgain=0; -@@ -1052,7 +1054,7 @@ void RT_SetContrast (TheatrePtr t, int Contrast) - * Inputs: CARD8 bInterlace * +- CARD8 bTempContrast=0; ++ uint8_t bTempContrast=0; + + /* VALIDATE CONTRAST LEVEL */ + if (Contrast < -1000) +@@ -1035,9 +1037,9 @@ void RT_SetContrast (TheatrePtr t, int Contrast) + break; + } + +- bTempContrast = (CARD8) ((dbContrast * dbYgain * 64) + 0.5); ++ bTempContrast = (uint8_t) ((dbContrast * dbYgain * 64) + 0.5); + +- WriteRT_fld (fld_LP_CONTRAST, (CARD32)bTempContrast); ++ WriteRT_fld (fld_LP_CONTRAST, (uint32_t)bTempContrast); + + /* Save value for future modification */ + t->dbContrast = dbContrast; +@@ -1047,23 +1049,23 @@ void RT_SetContrast (TheatrePtr t, int Contrast) + } /* RT_SetContrast ()... */ + + /**************************************************************************** +- * RT_SetInterlace (CARD8 bInterlace) * ++ * RT_SetInterlace (uint8_t bInterlace) * + * Function: to set the interlacing pattern for the Rage Theatre video in * +- * Inputs: CARD8 bInterlace * ++ * Inputs: uint8_t bInterlace * * Outputs: NONE * ****************************************************************************/ -void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) -+_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) ++_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) { switch(bInterlace) -@@ -1142,7 +1144,7 @@ static void GetStandardConstants (double *LPeriod, double *FPeriod, - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + { + case (TRUE): /*DEC_INTERLACE */ + WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); +- t->wInterlaced = (CARD16) RT_DECINTERLACED; ++ t->wInterlaced = (uint16_t) RT_DECINTERLACED; + break; + case (FALSE): /*DEC_NONINTERLACE */ + WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); +- t->wInterlaced = (CARD16) RT_DECNONINTERLACED; ++ t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; + break; + default: + break; +@@ -1075,16 +1077,16 @@ void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) + + /**************************************************************************** + * GetStandardConstants (double *LPeriod, double *FPeriod, * +- * double *Fsamp, CARD16 wStandard) * ++ * double *Fsamp, uint16_t wStandard) * + * Function: return timing values for a given standard * + * Inputs: double *LPeriod - + * double *FPeriod - + * double *Fsamp - sampling frequency used for a given standard * +- * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * + * Outputs: NONE * + ****************************************************************************/ + static void GetStandardConstants (double *LPeriod, double *FPeriod, +- double *Fsamp, CARD16 wStandard) ++ double *Fsamp, uint16_t wStandard) + { + *LPeriod = 0.0; + *FPeriod = 0.0; +@@ -1137,15 +1139,15 @@ static void GetStandardConstants (double *LPeriod, double *FPeriod, + + + /**************************************************************************** +- * RT_SetStandard (CARD16 wStandard) * ++ * RT_SetStandard (uint16_t wStandard) * + * Function: to set the input standard for the Rage Theatre video in * +- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -void RT_SetStandard (TheatrePtr t, CARD16 wStandard) -+_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) ++_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) { double dbFsamp=0, dbLPeriod=0, dbFPeriod=0; - CARD16 wFrameTotal = 0; -@@ -1427,7 +1429,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - * CARD16 wConnector - COMPOSITE, SVIDEO * +- CARD16 wFrameTotal = 0; ++ uint16_t wFrameTotal = 0; + double dbSPPeriod = 4.70; + + xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", +@@ -1155,7 +1157,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + /* Get the constants for the given standard. */ + GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); + +- wFrameTotal = (CARD16) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); ++ wFrameTotal = (uint16_t) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); + + /* Procedures before setting the standards: */ + WriteRT_fld (fld_VIN_CLK_SEL, RT_REF_CLK); +@@ -1207,10 +1209,10 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); + WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); + +- WriteRT_fld (fld_UV_INT_START, (CARD8)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); ++ WriteRT_fld (fld_UV_INT_START, (uint8_t)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); + +- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_NTSCM_VSYNC_INT_TRIGGER); +- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_NTSCM_VSYNC_INT_HOLD); ++ WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_NTSCM_VSYNC_INT_TRIGGER); ++ WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_NTSCM_VSYNC_INT_HOLD); + + switch (wStandard & 0xFF00) + { +@@ -1283,7 +1285,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + + WriteRT_fld (fld_VERT_LOCKOUT_START, RT_PAL_VERT_LOCKOUT_START); + WriteRT_fld (fld_VERT_LOCKOUT_END, RT_PAL_VERT_LOCKOUT_END); +- WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START); ++ WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); + + WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); + +@@ -1300,11 +1302,11 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); + + /* Magic 0.10 is correct - according to Ivo. Also see SECAM code below */ +-/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ +- WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); ++/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ ++ WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); + +- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER); +- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD); ++ WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); ++ WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); + + break; + case (DEC_SECAM): /*PAL GROUP*/ +@@ -1343,7 +1345,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + WriteRT_fld (fld_VERT_LOCKOUT_START, RT_SECAM_VERT_LOCKOUT_START); /*Might not need */ + WriteRT_fld (fld_VERT_LOCKOUT_END, RT_SECAM_VERT_LOCKOUT_END); /* Might not need */ + +- WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START); ++ WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); + WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); + + WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); +@@ -1358,11 +1360,11 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); + WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); + +- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER); +- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD); ++ WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); ++ WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); + +-/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ +- WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); ++/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ ++ WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); + + break; + default: +@@ -1381,37 +1383,37 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + } + + /* Set the following values according to the formulas */ +- WriteRT_fld (fld_HS_LINE_TOTAL, (CARD16)((dbLPeriod * dbFsamp / 2.0) +0.5)); ++ WriteRT_fld (fld_HS_LINE_TOTAL, (uint16_t)((dbLPeriod * dbFsamp / 2.0) +0.5)); + /* According to Ivo PAL/SECAM needs different treatment */ + switch(wStandard & 0x00FF) + { + case DEC_PAL: + case DEC_SECAM: +- WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.5 * dbSPPeriod * dbFsamp/2.0)); +- WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.5 * dbSPPeriod * dbFsamp/2.0)); +- WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); +- WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(2.39 * dbSPPeriod * dbFsamp / 2.0)); +- /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)RT_PAL_FIELD_IDLOCATION); */ ++ WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.5 * dbSPPeriod * dbFsamp/2.0)); ++ WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.5 * dbSPPeriod * dbFsamp/2.0)); ++ WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); ++ WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(2.39 * dbSPPeriod * dbFsamp / 2.0)); ++ /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)RT_PAL_FIELD_IDLOCATION); */ + /* According to docs the following value will work right, though the resulting stream deviates + slightly from CCIR..., in particular the value that was before will do nuts to VCRs in + pause/rewind state. */ +- WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01); ++ WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); + WriteRT_fld (fld_HS_PLL_SGAIN, 2); + break; + case DEC_NTSC: +- WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.75 * dbSPPeriod * dbFsamp/2.0)); +- WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.25 * dbSPPeriod * dbFsamp/2.0)); +- WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); +- WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(1.15 * dbSPPeriod * dbFsamp / 2.0)); +- /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)fld_VS_FIELD_IDLOCATION_def);*/ ++ WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.75 * dbSPPeriod * dbFsamp/2.0)); ++ WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.25 * dbSPPeriod * dbFsamp/2.0)); ++ WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); ++ WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(1.15 * dbSPPeriod * dbFsamp / 2.0)); ++ /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)fld_VS_FIELD_IDLOCATION_def);*/ + /* I think the default value was the same as the one here.. does not hurt to hardcode it */ +- WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01); ++ WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); + + } + +- WriteRT_fld (fld_VS_FRAME_TOTAL, (CARD16)(wFrameTotal) + 10); +- WriteRT_fld (fld_BLACK_INT_START, (CARD8)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); +- WriteRT_fld (fld_SYNC_TIP_START, (CARD16)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); ++ WriteRT_fld (fld_VS_FRAME_TOTAL, (uint16_t)(wFrameTotal) + 10); ++ WriteRT_fld (fld_BLACK_INT_START, (uint8_t)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); ++ WriteRT_fld (fld_SYNC_TIP_START, (uint16_t)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); + + return; + +@@ -1420,19 +1422,19 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + + + /**************************************************************************** +- * RT_SetCombFilter (CARD16 wStandard, CARD16 wConnector) * ++ * RT_SetCombFilter (uint16_t wStandard, uint16_t wConnector) * + * Function: sets the input comb filter based on the standard and * + * connector being used (composite vs. svideo) * +- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * +- * CARD16 wConnector - COMPOSITE, SVIDEO * ++ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * ++ * uint16_t wConnector - COMPOSITE, SVIDEO * * Outputs: NONE * ****************************************************************************/ -void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) -+static void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) ++static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector) { - CARD32 dwComb_Cntl0=0; - CARD32 dwComb_Cntl1=0; -@@ -1567,7 +1569,7 @@ void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) - * CARD8 fVBI_Cap_On - enable VBI capture * +- CARD32 dwComb_Cntl0=0; +- CARD32 dwComb_Cntl1=0; +- CARD32 dwComb_Cntl2=0; +- CARD32 dwComb_Line_Length=0; ++ uint32_t dwComb_Cntl0=0; ++ uint32_t dwComb_Cntl1=0; ++ uint32_t dwComb_Cntl2=0; ++ uint32_t dwComb_Line_Length=0; + + switch (wConnector) + { +@@ -1558,28 +1560,28 @@ void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) + + + /**************************************************************************** +- * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, * +- * CARD8 fCC_On, CARD8 fVBICap_On) * ++ * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * ++ * uint8_t fCC_On, uint8_t fVBICap_On) * + * Function: sets the output video size for the Rage Theatre video in * +- * Inputs: CARD16 wHorzSize - width of output in pixels * +- * CARD16 wVertSize - height of output in pixels (lines) * +- * CARD8 fCC_On - enable CC output * +- * CARD8 fVBI_Cap_On - enable VBI capture * ++ * Inputs: uint16_t wHorzSize - width of output in pixels * ++ * uint16_t wVertSize - height of output in pixels (lines) * ++ * uint8_t fCC_On - enable CC output * ++ * uint8_t fVBI_Cap_On - enable VBI capture * * Outputs: NONE * ****************************************************************************/ -void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) -+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) ++_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) { - CARD32 dwHwinStart=0; - CARD32 dwHScaleRatio=0; -@@ -1723,7 +1725,7 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA - * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * +- CARD32 dwHwinStart=0; +- CARD32 dwHScaleRatio=0; +- CARD32 dwHActiveLength=0; +- CARD32 dwVwinStart=0; +- CARD32 dwVScaleRatio=0; +- CARD32 dwVActiveLength=0; +- CARD32 dwTempRatio=0; +- CARD32 dwEvenFieldOffset=0; +- CARD32 dwOddFieldOffset=0; +- CARD32 dwXin=0; +- CARD32 dwYin=0; ++ uint32_t dwHwinStart=0; ++ uint32_t dwHScaleRatio=0; ++ uint32_t dwHActiveLength=0; ++ uint32_t dwVwinStart=0; ++ uint32_t dwVScaleRatio=0; ++ uint32_t dwVActiveLength=0; ++ uint32_t dwTempRatio=0; ++ uint32_t dwEvenFieldOffset=0; ++ uint32_t dwOddFieldOffset=0; ++ uint32_t dwXin=0; ++ uint32_t dwYin=0; + + if (fVBICap_On) + { +@@ -1626,21 +1628,21 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA + dwHwinStart = RT_NTSCM_H_IN_START; + dwXin = (ReadRT_fld (fld_H_ACTIVE_END) - ReadRT_fld (fld_H_ACTIVE_START)); /*tempscaler*/ + dwXin = RT_NTSC_H_ACTIVE_SIZE; +- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); ++ dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); + dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ + dwHActiveLength = wHorzSize; + break; + case (DEC_PAL): + dwHwinStart = RT_PAL_H_IN_START; + dwXin = RT_PAL_H_ACTIVE_SIZE; +- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); ++ dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); + dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ + dwHActiveLength = wHorzSize; + break; + case (DEC_SECAM): + dwHwinStart = RT_SECAM_H_IN_START; + dwXin = RT_SECAM_H_ACTIVE_SIZE; +- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); ++ dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); + dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ + dwHActiveLength = wHorzSize; + break; +@@ -1655,24 +1657,24 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA + dwVwinStart = RT_NTSCM_V_IN_START; + /* dwYin = (ReadRT_fld (fld_V_ACTIVE_END) - ReadRT_fld (fld_V_ACTIVE_START)); */ /*tempscaler*/ + dwYin = RT_NTSCM_V_ACTIVE_SIZE; +- dwTempRatio = (CARD32)((long) wVertSize / dwYin); +- dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin); ++ dwTempRatio = (uint32_t)((long) wVertSize / dwYin); ++ dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); + dwVScaleRatio = dwVScaleRatio & 0x00000FFF; + dwVActiveLength = wVertSize/2; + break; + case (DEC_PAL): + dwVwinStart = RT_PAL_V_IN_START; + dwYin = RT_PAL_V_ACTIVE_SIZE; +- dwTempRatio = (CARD32)(wVertSize/dwYin); +- dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin); ++ dwTempRatio = (uint32_t)(wVertSize/dwYin); ++ dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); + dwVScaleRatio = dwVScaleRatio & 0x00000FFF; + dwVActiveLength = wVertSize/2; + break; + case (DEC_SECAM): + dwVwinStart = RT_SECAM_V_IN_START; + dwYin = RT_SECAM_V_ACTIVE_SIZE; +- dwTempRatio = (CARD32) (wVertSize / dwYin); +- dwVScaleRatio = (CARD32) ((long) wVertSize * 2048L / dwYin); ++ dwTempRatio = (uint32_t) (wVertSize / dwYin); ++ dwVScaleRatio = (uint32_t) ((long) wVertSize * 2048L / dwYin); + dwVScaleRatio = dwVScaleRatio & 0x00000FFF; + dwVActiveLength = wVertSize/2; + break; +@@ -1683,14 +1685,14 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA + /*4. Set up offset based on if interlaced or not:*/ + if (t->wInterlaced == RT_DECINTERLACED) + { +- dwEvenFieldOffset = (CARD32) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); ++ dwEvenFieldOffset = (uint32_t) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); + dwOddFieldOffset = dwEvenFieldOffset; + WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); + } + else + { +- dwEvenFieldOffset = (CARD32)(dwTempRatio * 512.0); +- dwOddFieldOffset = (CARD32)(2048 - dwEvenFieldOffset); ++ dwEvenFieldOffset = (uint32_t)(dwTempRatio * 512.0); ++ dwOddFieldOffset = (uint32_t)(2048 - dwEvenFieldOffset); + WriteRT_fld (fld_V_DEINTERLACE_ON, 0x0); + } + +@@ -1716,14 +1718,14 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA + + + /**************************************************************************** +- * CalculateCrCbGain (double *CrGain, double *CbGain, CARD16 wStandard) * ++ * CalculateCrCbGain (double *CrGain, double *CbGain, uint16_t wStandard) * + * Function: * + * Inputs: double *CrGain - + * double *CbGain - +- * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard) -+static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard) ++static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard) { #define UVFLTGAIN 1.5 #define FRMAX 280000.0 -@@ -1864,7 +1866,7 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) +@@ -1773,15 +1775,15 @@ void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wSt + + + /**************************************************************************** +- * RT_SetConnector (CARD16 wStandard, int tunerFlag) * ++ * RT_SetConnector (uint16_t wStandard, int tunerFlag) * + * Function: +- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * + * int tunerFlag + * Outputs: NONE * + ****************************************************************************/ +-void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) ++void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) + { +- CARD32 dwTempContrast=0; ++ uint32_t dwTempContrast=0; + int i; + long counter; + +@@ -1864,9 +1866,9 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) } /* RT_SetConnector ()...*/ -void InitTheatre(TheatrePtr t) +_X_EXPORT void InitTheatre(TheatrePtr t) { - CARD32 data; +- CARD32 data; ++ uint32_t data; + + /* 0 reset Rage Theatre */ @@ -1929,7 +1931,7 @@ void InitTheatre(TheatrePtr t) } @@ -10998,7 +15872,7 @@ index a5aadfb..a4d3c10 100644 { WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); WriteRT_fld (fld_VINRST , RT_VINRST_RESET); -@@ -1938,7 +1940,7 @@ void ShutdownTheatre(TheatrePtr t) +@@ -1938,10 +1940,10 @@ void ShutdownTheatre(TheatrePtr t) t->mode=MODE_UNINITIALIZED; } @@ -11006,7 +15880,20 @@ index a5aadfb..a4d3c10 100644 +_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) { int i; - CARD32 data; +- CARD32 data; ++ uint32_t data; + + for(i=0;i<0x900;i+=4) + { +@@ -1955,7 +1957,7 @@ void DumpRageTheatreRegs(TheatrePtr t) + void DumpRageTheatreRegsByName(TheatrePtr t) + { + int i; +- CARD32 data; ++ uint32_t data; + struct { char *name; long addr; } rt_reg_list[]={ + { "ADC_CNTL ", 0x0400 }, + { "ADC_DEBUG ", 0x0404 }, @@ -2159,7 +2161,7 @@ void DumpRageTheatreRegsByName(TheatrePtr t) } @@ -11026,10 +15913,60 @@ index a5aadfb..a4d3c10 100644 /* RT_regw(VIP_HW_DEBUG, 0x200); */ /* RT_regw(VIP_INT_CNTL, 0x0); diff --git a/src/theatre.h b/src/theatre.h -index 958b443..36d6e05 100644 +index 958b443..c70a0e0 100644 --- a/src/theatre.h +++ b/src/theatre.h -@@ -35,45 +35,37 @@ typedef struct { +@@ -8,72 +8,64 @@ + typedef struct { + GENERIC_BUS_Ptr VIP; + +- int theatre_num; +- CARD32 theatre_id; +- int mode; +- char* microc_path; +- char* microc_type; ++ int theatre_num; ++ uint32_t theatre_id; ++ int mode; ++ char* microc_path; ++ char* microc_type; + +- CARD16 video_decoder_type; +- CARD32 wStandard; +- CARD32 wConnector; +- int iHue; +- int iSaturation; +- CARD32 wSaturation_U; +- CARD32 wSaturation_V; +- int iBrightness; +- int dbBrightnessRatio; +- CARD32 wSharpness; +- int iContrast; +- int dbContrast; +- CARD32 wInterlaced; +- CARD32 wTunerConnector; +- CARD32 wComp0Connector; +- CARD32 wSVideo0Connector; +- CARD32 dwHorzScalingRatio; +- CARD32 dwVertScalingRatio; ++ uint16_t video_decoder_type; ++ uint32_t wStandard; ++ uint32_t wConnector; ++ int iHue; ++ int iSaturation; ++ uint32_t wSaturation_U; ++ uint32_t wSaturation_V; ++ int iBrightness; ++ int dbBrightnessRatio; ++ uint32_t wSharpness; ++ int iContrast; ++ int dbContrast; ++ uint32_t wInterlaced; ++ uint32_t wTunerConnector; ++ uint32_t wComp0Connector; ++ uint32_t wSVideo0Connector; ++ uint32_t dwHorzScalingRatio; ++ uint32_t dwVertScalingRatio; } TheatreRec, * TheatrePtr; @@ -11083,17 +16020,17 @@ index 958b443..36d6e05 100644 +#define xf86_RT_SetBrightness RT_SetBrightness +_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness); +#define xf86_RT_SetSharpness RT_SetSharpness -+_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness); ++_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness); +#define xf86_RT_SetContrast RT_SetContrast +_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast); +#define xf86_RT_SetInterlace RT_SetInterlace -+_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace); ++_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace); +#define xf86_RT_SetStandard RT_SetStandard -+_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard); ++_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard); +#define xf86_RT_SetOutputVideoSize RT_SetOutputVideoSize -+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On); ++_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On); +#define xf86_RT_SetConnector RT_SetConnector -+_X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag); ++_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag); +#define xf86_ResetTheatreRegsForNoTVout ResetTheatreRegsForNoTVout +_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t); +#define xf86_ResetTheatreRegsForTVout ResetTheatreRegsForTVout @@ -11107,9 +16044,546 @@ index 958b443..36d6e05 100644 #endif diff --git a/src/theatre200.c b/src/theatre200.c -index 672f01e..0341c6e 100644 +index 672f01e..c150ed4 100644 --- a/src/theatre200.c +++ b/src/theatre200.c +@@ -71,51 +71,51 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen); + static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap); + static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap); + +-static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0); +-static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector); +-//static CARD32 dsp_reset(TheatrePtr t); +-static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate); +-static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard); +-static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format); +-static CARD32 dsp_video_standard_detection(TheatrePtr t); +-//static CARD32 dsp_get_signallockstatus(TheatrePtr t); +-//static CARD32 dsp_get_signallinenumber(TheatrePtr t); +- +-static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness); +-static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast); +-//static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness); +-static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint); +-static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation); +-static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end); +-static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end); +-static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right); +-static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute); +-//static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option); +-static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode); +-static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state); +- +-static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) ++static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0); ++static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector); ++//static uint32_t dsp_reset(TheatrePtr t); ++static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate); ++static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard); ++static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format); ++static uint32_t dsp_video_standard_detection(TheatrePtr t); ++//static uint32_t dsp_get_signallockstatus(TheatrePtr t); ++//static uint32_t dsp_get_signallinenumber(TheatrePtr t); ++ ++static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness); ++static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast); ++//static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness); ++static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint); ++static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation); ++static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end); ++static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end); ++static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right); ++static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute); ++//static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option); ++static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode); ++static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state); ++ ++static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); ++ return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); + } + +-static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) ++static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); ++ return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); + } + +-static Bool theatre_fifo_read(TheatrePtr t,CARD32 fifo, CARD8 *data) ++static Bool theatre_fifo_read(TheatrePtr t,uint32_t fifo, uint8_t *data) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (CARD8 *) data); ++ return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (uint8_t *) data); + } + +-static Bool theatre_fifo_write(TheatrePtr t,CARD32 fifo, CARD32 count, CARD8* buffer) ++static Bool theatre_fifo_write(TheatrePtr t,uint32_t fifo, uint32_t count, uint8_t* buffer) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (CARD8 *)buffer); ++ return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (uint8_t *)buffer); + } + + #define RT_regr(reg,data) theatre_read(t,(reg),(data)) +@@ -344,7 +344,7 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen) + + static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) + { +- CARD32 data; ++ uint32_t data; + int i = 0; + int screen = t->VIP->scrnIndex; + +@@ -369,12 +369,12 @@ static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) + static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) + { + struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; +- CARD8 data8; +- CARD32 data, fb_scratch0, fb_scratch1; +- CARD32 i; +- CARD32 tries = 0; +- CARD32 result = 0; +- CARD32 seg_id = 0; ++ uint8_t data8; ++ uint32_t data, fb_scratch0, fb_scratch1; ++ uint32_t i; ++ uint32_t tries = 0; ++ uint32_t result = 0; ++ uint32_t seg_id = 0; + int screen = t->VIP->scrnIndex; + + DEBUG("Microcode: before everything: %x\n", data8); +@@ -564,9 +564,9 @@ static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) + return 0; + } + +-static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0) ++static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0) + { +- CARD32 data; ++ uint32_t data; + int i; + + /* +@@ -611,10 +611,10 @@ static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scrat + return fb_scratch0; + } + +-static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector) ++static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector) + { +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff); +@@ -627,10 +627,10 @@ static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector) + } + + #if 0 +-static CARD32 dsp_reset(TheatrePtr t) ++static uint32_t dsp_reset(TheatrePtr t) + { +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff); +@@ -643,10 +643,10 @@ static CARD32 dsp_reset(TheatrePtr t) + } + #endif + +-static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate) ++static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate) + { +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff); +@@ -657,10 +657,10 @@ static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate) + + return result; + } +-static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard) ++static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard) + { +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff); +@@ -672,10 +672,10 @@ static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard) + return result; + } + +-static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format) ++static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format) + { +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff); +@@ -687,10 +687,10 @@ static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format) + return result; + } + +-static CARD32 dsp_video_standard_detection(TheatrePtr t) ++static uint32_t dsp_video_standard_detection(TheatrePtr t) + { +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = 0 | (54 & 0xff); +@@ -703,11 +703,11 @@ static CARD32 dsp_video_standard_detection(TheatrePtr t) + } + + #if 0 +-static CARD32 dsp_get_signallockstatus(TheatrePtr t) ++static uint32_t dsp_get_signallockstatus(TheatrePtr t) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = 0 | (77 & 0xff); +@@ -720,11 +720,11 @@ static CARD32 dsp_get_signallockstatus(TheatrePtr t) + return result; + } + +-static CARD32 dsp_get_signallinenumber(TheatrePtr t) ++static uint32_t dsp_get_signallinenumber(TheatrePtr t) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = 0 | (78 & 0xff); +@@ -738,11 +738,11 @@ static CARD32 dsp_get_signallinenumber(TheatrePtr t) + } + #endif + +-static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness) ++static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff); +@@ -754,11 +754,11 @@ static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness) + return result; + } + +-static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast) ++static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff); +@@ -771,11 +771,11 @@ static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast) + } + + #if 0 +-static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness) ++static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = 0 | (73 & 0xff); +@@ -788,11 +788,11 @@ static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness) + } + #endif + +-static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint) ++static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff); +@@ -804,11 +804,11 @@ static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint) + return result; + } + +-static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation) ++static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff); +@@ -820,11 +820,11 @@ static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation) + return result; + } + +-static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end) ++static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff); +@@ -837,11 +837,11 @@ static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, + return result; + } + +-static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end) ++static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff); +@@ -854,11 +854,11 @@ static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, + return result; + } + +-static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right) ++static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff); +@@ -870,11 +870,11 @@ static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right) + return result; + } + +-static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute) ++static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff); +@@ -887,11 +887,11 @@ static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 + } + + #if 0 +-static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option) ++static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff); +@@ -904,11 +904,11 @@ static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option) + } + #endif + +-static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode) ++static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff); +@@ -920,11 +920,11 @@ static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, + return result; + } + +-static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state) ++static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state) + { +- CARD32 fb_scratch1 = 0; +- CARD32 fb_scratch0 = 0; +- CARD32 result; ++ uint32_t fb_scratch1 = 0; ++ uint32_t fb_scratch0 = 0; ++ uint32_t result; + int screen = t->VIP->scrnIndex; + + fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff); +@@ -1014,7 +1014,7 @@ fld_V_INT_LENGTH, + fld_CRDR_ACTIVE_GAIN, + fld_CBDB_ACTIVE_GAIN, + fld_DVS_DIRECTION, +-fld_DVS_VBI_CARD8_SWAP, ++fld_DVS_VBI_UINT8_SWAP, + fld_DVS_CLK_SELECT, + fld_CONTINUOUS_STREAM, + fld_DVSOUT_CLK_DRV, +@@ -1096,16 +1096,16 @@ regRT_MAX_REGS + + + typedef struct { +- CARD8 size; +- CARD32 fld_id; +- CARD32 dwRegAddrLSBs; +- CARD32 dwFldOffsetLSBs; +- CARD32 dwMaskLSBs; +- CARD32 addr2; +- CARD32 offs2; +- CARD32 mask2; +- CARD32 dwCurrValue; +- CARD32 rw; ++ uint8_t size; ++ uint32_t fld_id; ++ uint32_t dwRegAddrLSBs; ++ uint32_t dwFldOffsetLSBs; ++ uint32_t dwMaskLSBs; ++ uint32_t addr2; ++ uint32_t offs2; ++ uint32_t mask2; ++ uint32_t dwCurrValue; ++ uint32_t rw; + } RTREGMAP; + + #define READONLY 1 +@@ -1193,7 +1193,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ + {10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, + {10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, + {1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, +-{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE }, ++{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, + {1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, + {1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, + {1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, +@@ -1272,7 +1272,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ + }; + + /* Rage Theatre's register fields default values: */ +-CARD32 RT_RegDef[regRT_MAX_REGS]= ++uint32_t RT_RegDef[regRT_MAX_REGS]= + { + fld_tmpReg1_def, + fld_tmpReg2_def, +@@ -1350,7 +1350,7 @@ fld_V_INT_LENGTH_def, + fld_CRDR_ACTIVE_GAIN_def, + fld_CBDB_ACTIVE_GAIN_def, + fld_DVS_DIRECTION_def, +-fld_DVS_VBI_CARD8_SWAP_def, ++fld_DVS_VBI_UINT8_SWAP_def, + fld_DVS_CLK_SELECT_def, + fld_CONTINUOUS_STREAM_def, + fld_DVSOUT_CLK_DRV_def, +@@ -1429,16 +1429,16 @@ fld_GPIO_6_OUT_def, + }; + + /**************************************************************************** +- * WriteRT_fld (CARD32 dwReg, CARD32 dwData) * ++ * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * + * Function: Writes a register field within Rage Theatre * +- * Inputs: CARD32 dwReg = register field to be written * +- * CARD32 dwData = data that will be written to the reg field * ++ * Inputs: uint32_t dwReg = register field to be written * ++ * uint32_t dwData = data that will be written to the reg field * + * Outputs: NONE * + ****************************************************************************/ +-static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) ++static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) + { +- CARD32 dwResult=0; +- CARD32 dwValue=0; ++ uint32_t dwResult=0; ++ uint32_t dwValue=0; + + if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) + { +@@ -1458,14 +1458,14 @@ static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) + + #if 0 + /**************************************************************************** +- * ReadRT_fld (CARD32 dwReg) * ++ * ReadRT_fld (uint32_t dwReg) * + * Function: Reads a register field within Rage Theatre * +- * Inputs: CARD32 dwReg = register field to be read * +- * Outputs: CARD32 - value read from register field * ++ * Inputs: uint32_t dwReg = register field to be read * ++ * Outputs: uint32_t - value read from register field * + ****************************************************************************/ +-static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) ++static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) + { +- CARD32 dwResult=0; ++ uint32_t dwResult=0; + + if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) + { @@ -1492,7 +1492,7 @@ static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) * Inputs: int hue - the hue value to be set. * * Outputs: NONE * @@ -11119,6 +16593,15 @@ index 672f01e..0341c6e 100644 { /* Validate Hue level */ if (hue < -1000) +@@ -1506,7 +1506,7 @@ void RT_SetTint (TheatrePtr t, int hue) + + t->iHue=hue; + +- dsp_set_tint(t, (CARD8)((hue*255)/2000 + 128)); ++ dsp_set_tint(t, (uint8_t)((hue*255)/2000 + 128)); + + } /* RT_SetTint ()... */ + @@ -1517,7 +1517,7 @@ void RT_SetTint (TheatrePtr t, int hue) * Inputs: int Saturation - the saturation value to be set. * * Outputs: NONE * @@ -11128,6 +16611,15 @@ index 672f01e..0341c6e 100644 { /* VALIDATE SATURATION LEVEL */ if (Saturation < -1000L) +@@ -1532,7 +1532,7 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) + t->iSaturation = Saturation; + + /* RT200 has saturation in range 0 to 255 with nominal value 128 */ +- dsp_set_saturation(t, (CARD8)((Saturation*255)/2000 + 128)); ++ dsp_set_saturation(t, (uint8_t)((Saturation*255)/2000 + 128)); + + return; + } /* RT_SetSaturation ()...*/ @@ -1543,7 +1543,7 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) * Inputs: int Brightness - the brightness value to be set. * * Outputs: NONE * @@ -11137,12 +16629,27 @@ index 672f01e..0341c6e 100644 { /* VALIDATE BRIGHTNESS LEVEL */ if (Brightness < -1000) -@@ -1572,7 +1572,7 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) - * Inputs: CARD16 wSharpness - the sharpness value to be set. * +@@ -1560,19 +1560,19 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) + t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; + + /* RT200 is having brightness level from 0 to 255 with 128 nominal value */ +- dsp_set_brightness(t, (CARD8)((Brightness*255)/2000 + 128)); ++ dsp_set_brightness(t, (uint8_t)((Brightness*255)/2000 + 128)); + + return; + } /* RT_SetBrightness ()... */ + + + /**************************************************************************** +- * RT_SetSharpness (CARD16 wSharpness) * ++ * RT_SetSharpness (uint16_t wSharpness) * + * Function: sets the sharpness level for the Rage Theatre video in * +- * Inputs: CARD16 wSharpness - the sharpness value to be set. * ++ * Inputs: uint16_t wSharpness - the sharpness value to be set. * * Outputs: NONE * ****************************************************************************/ -void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) -+_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) ++_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) { switch (wSharpness) { @@ -11155,51 +16662,115 @@ index 672f01e..0341c6e 100644 { /* VALIDATE CONTRAST LEVEL */ if (Contrast < -1000) -@@ -1626,7 +1626,7 @@ void RT_SetContrast (TheatrePtr t, int Contrast) - * Inputs: CARD8 bInterlace * +@@ -1615,28 +1615,28 @@ void RT_SetContrast (TheatrePtr t, int Contrast) + t->dbContrast = (double) (Contrast+1000.0) / 1000.0; + + /* RT200 has contrast values between 0 to 255 with nominal value at 128 */ +- dsp_set_contrast(t, (CARD8)((Contrast*255)/2000 + 128)); ++ dsp_set_contrast(t, (uint8_t)((Contrast*255)/2000 + 128)); + return; + + } /* RT_SetContrast ()... */ + + /**************************************************************************** +- * RT_SetInterlace (CARD8 bInterlace) * ++ * RT_SetInterlace (uint8_t bInterlace) * + * Function: to set the interlacing pattern for the Rage Theatre video in * +- * Inputs: CARD8 bInterlace * ++ * Inputs: uint8_t bInterlace * * Outputs: NONE * ****************************************************************************/ -void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) -+_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) ++_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) { switch(bInterlace) { -@@ -1653,7 +1653,7 @@ void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) - * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * + case (TRUE): /*DEC_INTERLACE */ + WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); +- t->wInterlaced = (CARD16) RT_DECINTERLACED; ++ t->wInterlaced = (uint16_t) RT_DECINTERLACED; + break; + case (FALSE): /*DEC_NONINTERLACE */ + WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); +- t->wInterlaced = (CARD16) RT_DECNONINTERLACED; ++ t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; + break; + default: + break; +@@ -1648,12 +1648,12 @@ void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) + + + /**************************************************************************** +- * RT_SetStandard (CARD16 wStandard) * ++ * RT_SetStandard (uint16_t wStandard) * + * Function: to set the input standard for the Rage Theatre video in * +- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * Outputs: NONE * ****************************************************************************/ -void RT_SetStandard (TheatrePtr t, CARD16 wStandard) -+_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard) ++_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) { xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", wStandard); -@@ -1772,7 +1772,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - * CARD8 fVBI_Cap_On - enable VBI capture * +@@ -1763,16 +1763,16 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) + + + /**************************************************************************** +- * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, * +- * CARD8 fCC_On, CARD8 fVBICap_On) * ++ * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * ++ * uint8_t fCC_On, uint8_t fVBICap_On) * + * Function: sets the output video size for the Rage Theatre video in * +- * Inputs: CARD16 wHorzSize - width of output in pixels * +- * CARD16 wVertSize - height of output in pixels (lines) * +- * CARD8 fCC_On - enable CC output * +- * CARD8 fVBI_Cap_On - enable VBI capture * ++ * Inputs: uint16_t wHorzSize - width of output in pixels * ++ * uint16_t wVertSize - height of output in pixels (lines) * ++ * uint8_t fCC_On - enable CC output * ++ * uint8_t fVBI_Cap_On - enable VBI capture * * Outputs: NONE * ****************************************************************************/ -void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) -+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) ++_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) { /* VBI is ignored now */ -@@ -1792,7 +1792,7 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA +@@ -1786,15 +1786,15 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA + + + /**************************************************************************** +- * RT_SetConnector (CARD16 wStandard, int tunerFlag) * ++ * RT_SetConnector (uint16_t wStandard, int tunerFlag) * + * Function: +- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * ++ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * * int tunerFlag * Outputs: NONE * ****************************************************************************/ -void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) -+_X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) ++_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) { - CARD32 data; +- CARD32 data; ++ uint32_t data; -@@ -1871,7 +1871,7 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) + t->wConnector = wConnector; + +@@ -1871,10 +1871,10 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) } /* RT_SetConnector ()...*/ -void InitTheatre(TheatrePtr t) +_X_EXPORT void InitTheatre(TheatrePtr t) { - CARD32 data; - CARD32 M, N, P; +- CARD32 data; +- CARD32 M, N, P; ++ uint32_t data; ++ uint32_t M, N, P; + + /* this will give 108Mhz at 27Mhz reference */ + M = 28; @@ -1992,7 +1992,7 @@ err_exit: } @@ -11209,7 +16780,7 @@ index 672f01e..0341c6e 100644 { #if 0 WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); -@@ -2003,7 +2003,7 @@ void ShutdownTheatre(TheatrePtr t) +@@ -2003,10 +2003,10 @@ void ShutdownTheatre(TheatrePtr t) t->mode=MODE_UNINITIALIZED; } @@ -11217,7 +16788,20 @@ index 672f01e..0341c6e 100644 +_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) { int i; - CARD32 data; +- CARD32 data; ++ uint32_t data; + + for(i=0;i<0x900;i+=4) + { +@@ -2020,7 +2020,7 @@ void DumpRageTheatreRegs(TheatrePtr t) + void DumpRageTheatreRegsByName(TheatrePtr t) + { + int i; +- CARD32 data; ++ uint32_t data; + struct { char *name; long addr; } rt_reg_list[]={ + { "ADC_CNTL ", 0x0400 }, + { "ADC_DEBUG ", 0x0404 }, @@ -2224,7 +2224,7 @@ void DumpRageTheatreRegsByName(TheatrePtr t) } @@ -11237,18 +16821,35 @@ index 672f01e..0341c6e 100644 /* RT_regw(VIP_HW_DEBUG, 0x200); */ /* RT_regw(VIP_INT_CNTL, 0x0); diff --git a/src/theatre_detect.c b/src/theatre_detect.c -index 8770911..79dcfe4 100644 +index 8770911..7e7f813 100644 --- a/src/theatre_detect.c +++ b/src/theatre_detect.c -@@ -43,6 +43,7 @@ +@@ -43,19 +43,20 @@ #include "generic_bus.h" #include "theatre.h" #include "theatre_reg.h" +#include "theatre_detect.h" - static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) +-static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) ++static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) { -@@ -64,7 +65,7 @@ static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) + if(t->theatre_num<0)return FALSE; +- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); ++ return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); + } + + /* Unused code - reference */ + #if 0 +-static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) ++static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) + { + if(t->theatre_num<0)return FALSE; +- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); ++ return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); + } + #define RT_regw(reg,data) theatre_write(t,(reg),(data)) + #endif +@@ -64,11 +65,11 @@ static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) #define VIP_TYPE "ATI VIP BUS" @@ -11257,6 +16858,24 @@ index 8770911..79dcfe4 100644 { TheatrePtr t; int i; +- CARD32 val; ++ uint32_t val; + char s[20]; + + b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); +@@ -83,10 +84,10 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) + t->theatre_num = -1; + t->mode=MODE_UNINITIALIZED; + +- b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val); ++ b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); + for(i=0;i<4;i++) + { +- if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) ++ if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) + { + if(val)xf86DrvMsg(b->scrnIndex, X_INFO, + "Device %d on VIP bus ids as 0x%08x\n", i, diff --git a/src/theatre_detect.h b/src/theatre_detect.h index 5fed160..53d8d11 100644 --- a/src/theatre_detect.h @@ -11273,3 +16892,376 @@ index 5fed160..53d8d11 100644 -#define xf86_DetectTheatre ((TheatrePtr (*)(GENERIC_BUS_Ptr))LoaderSymbol("DetectTheatre")) #endif +diff --git a/src/theatre_reg.h b/src/theatre_reg.h +index c681001..30fafe7 100644 +--- a/src/theatre_reg.h ++++ b/src/theatre_reg.h +@@ -661,215 +661,215 @@ + #define DEC_SHARP 1 + + /* RT Register Field Defaults: */ +-#define fld_tmpReg1_def (CARD32) 0x00000000 +-#define fld_tmpReg2_def (CARD32) 0x00000001 +-#define fld_tmpReg3_def (CARD32) 0x00000002 ++#define fld_tmpReg1_def (uint32_t) 0x00000000 ++#define fld_tmpReg2_def (uint32_t) 0x00000001 ++#define fld_tmpReg3_def (uint32_t) 0x00000002 + +-#define fld_LP_CONTRAST_def (CARD32) 0x0000006e +-#define fld_LP_BRIGHTNESS_def (CARD32) 0x00003ff0 +-#define fld_CP_HUE_CNTL_def (CARD32) 0x00000000 +-#define fld_LUMA_FILTER_def (CARD32) 0x00000001 +-#define fld_H_SCALE_RATIO_def (CARD32) 0x00010000 +-#define fld_H_SHARPNESS_def (CARD32) 0x00000000 ++#define fld_LP_CONTRAST_def (uint32_t) 0x0000006e ++#define fld_LP_BRIGHTNESS_def (uint32_t) 0x00003ff0 ++#define fld_CP_HUE_CNTL_def (uint32_t) 0x00000000 ++#define fld_LUMA_FILTER_def (uint32_t) 0x00000001 ++#define fld_H_SCALE_RATIO_def (uint32_t) 0x00010000 ++#define fld_H_SHARPNESS_def (uint32_t) 0x00000000 + +-#define fld_V_SCALE_RATIO_def (CARD32) 0x00000800 +-#define fld_V_DEINTERLACE_ON_def (CARD32) 0x00000001 +-#define fld_V_BYPSS_def (CARD32) 0x00000000 +-#define fld_V_DITHER_ON_def (CARD32) 0x00000001 +-#define fld_EVENF_OFFSET_def (CARD32) 0x00000000 +-#define fld_ODDF_OFFSET_def (CARD32) 0x00000000 ++#define fld_V_SCALE_RATIO_def (uint32_t) 0x00000800 ++#define fld_V_DEINTERLACE_ON_def (uint32_t) 0x00000001 ++#define fld_V_BYPSS_def (uint32_t) 0x00000000 ++#define fld_V_DITHER_ON_def (uint32_t) 0x00000001 ++#define fld_EVENF_OFFSET_def (uint32_t) 0x00000000 ++#define fld_ODDF_OFFSET_def (uint32_t) 0x00000000 + +-#define fld_INTERLACE_DETECTED_def (CARD32) 0x00000000 ++#define fld_INTERLACE_DETECTED_def (uint32_t) 0x00000000 + +-#define fld_VS_LINE_COUNT_def (CARD32) 0x00000000 +-#define fld_VS_DETECTED_LINES_def (CARD32) 0x00000000 +-#define fld_VS_ITU656_VB_def (CARD32) 0x00000000 ++#define fld_VS_LINE_COUNT_def (uint32_t) 0x00000000 ++#define fld_VS_DETECTED_LINES_def (uint32_t) 0x00000000 ++#define fld_VS_ITU656_VB_def (uint32_t) 0x00000000 + +-#define fld_VBI_CC_DATA_def (CARD32) 0x00000000 +-#define fld_VBI_CC_WT_def (CARD32) 0x00000000 +-#define fld_VBI_CC_WT_ACK_def (CARD32) 0x00000000 +-#define fld_VBI_CC_HOLD_def (CARD32) 0x00000000 +-#define fld_VBI_DECODE_EN_def (CARD32) 0x00000000 ++#define fld_VBI_CC_DATA_def (uint32_t) 0x00000000 ++#define fld_VBI_CC_WT_def (uint32_t) 0x00000000 ++#define fld_VBI_CC_WT_ACK_def (uint32_t) 0x00000000 ++#define fld_VBI_CC_HOLD_def (uint32_t) 0x00000000 ++#define fld_VBI_DECODE_EN_def (uint32_t) 0x00000000 + +-#define fld_VBI_CC_DTO_P_def (CARD32) 0x00001802 +-#define fld_VBI_20BIT_DTO_P_def (CARD32) 0x0000155c ++#define fld_VBI_CC_DTO_P_def (uint32_t) 0x00001802 ++#define fld_VBI_20BIT_DTO_P_def (uint32_t) 0x0000155c + +-#define fld_VBI_CC_LEVEL_def (CARD32) 0x0000003f +-#define fld_VBI_20BIT_LEVEL_def (CARD32) 0x00000059 +-#define fld_VBI_CLK_RUNIN_GAIN_def (CARD32) 0x0000010f ++#define fld_VBI_CC_LEVEL_def (uint32_t) 0x0000003f ++#define fld_VBI_20BIT_LEVEL_def (uint32_t) 0x00000059 ++#define fld_VBI_CLK_RUNIN_GAIN_def (uint32_t) 0x0000010f + +-#define fld_H_VBI_WIND_START_def (CARD32) 0x00000041 +-#define fld_H_VBI_WIND_END_def (CARD32) 0x00000366 ++#define fld_H_VBI_WIND_START_def (uint32_t) 0x00000041 ++#define fld_H_VBI_WIND_END_def (uint32_t) 0x00000366 + +-#define fld_V_VBI_WIND_START_def (CARD32) 0x0B /* instead of 0x0D - V.D. */ +-#define fld_V_VBI_WIND_END_def (CARD32) 0x24 ++#define fld_V_VBI_WIND_START_def (uint32_t) 0x0B /* instead of 0x0D - V.D. */ ++#define fld_V_VBI_WIND_END_def (uint32_t) 0x24 + +-#define fld_VBI_20BIT_DATA0_def (CARD32) 0x00000000 +-#define fld_VBI_20BIT_DATA1_def (CARD32) 0x00000000 +-#define fld_VBI_20BIT_WT_def (CARD32) 0x00000000 +-#define fld_VBI_20BIT_WT_ACK_def (CARD32) 0x00000000 +-#define fld_VBI_20BIT_HOLD_def (CARD32) 0x00000000 ++#define fld_VBI_20BIT_DATA0_def (uint32_t) 0x00000000 ++#define fld_VBI_20BIT_DATA1_def (uint32_t) 0x00000000 ++#define fld_VBI_20BIT_WT_def (uint32_t) 0x00000000 ++#define fld_VBI_20BIT_WT_ACK_def (uint32_t) 0x00000000 ++#define fld_VBI_20BIT_HOLD_def (uint32_t) 0x00000000 + +-#define fld_VBI_CAPTURE_ENABLE_def (CARD32) 0x00000000 ++#define fld_VBI_CAPTURE_ENABLE_def (uint32_t) 0x00000000 + +-#define fld_VBI_EDS_DATA_def (CARD32) 0x00000000 +-#define fld_VBI_EDS_WT_def (CARD32) 0x00000000 +-#define fld_VBI_EDS_WT_ACK_def (CARD32) 0x00000000 +-#define fld_VBI_EDS_HOLD_def (CARD32) 0x00000000 ++#define fld_VBI_EDS_DATA_def (uint32_t) 0x00000000 ++#define fld_VBI_EDS_WT_def (uint32_t) 0x00000000 ++#define fld_VBI_EDS_WT_ACK_def (uint32_t) 0x00000000 ++#define fld_VBI_EDS_HOLD_def (uint32_t) 0x00000000 + +-#define fld_VBI_SCALING_RATIO_def (CARD32) 0x00010000 +-#define fld_VBI_ALIGNER_ENABLE_def (CARD32) 0x00000000 ++#define fld_VBI_SCALING_RATIO_def (uint32_t) 0x00010000 ++#define fld_VBI_ALIGNER_ENABLE_def (uint32_t) 0x00000000 + +-#define fld_H_ACTIVE_START_def (CARD32) 0x00000070 +-#define fld_H_ACTIVE_END_def (CARD32) 0x000002f0 ++#define fld_H_ACTIVE_START_def (uint32_t) 0x00000070 ++#define fld_H_ACTIVE_END_def (uint32_t) 0x000002f0 + +-#define fld_V_ACTIVE_START_def (CARD32) ((22-4)*2+1) +-#define fld_V_ACTIVE_END_def (CARD32) ((22+240-4)*2+2) ++#define fld_V_ACTIVE_START_def (uint32_t) ((22-4)*2+1) ++#define fld_V_ACTIVE_END_def (uint32_t) ((22+240-4)*2+2) + +-#define fld_CH_HEIGHT_def (CARD32) 0x000000CD +-#define fld_CH_KILL_LEVEL_def (CARD32) 0x000000C0 +-#define fld_CH_AGC_ERROR_LIM_def (CARD32) 0x00000002 +-#define fld_CH_AGC_FILTER_EN_def (CARD32) 0x00000000 +-#define fld_CH_AGC_LOOP_SPEED_def (CARD32) 0x00000000 ++#define fld_CH_HEIGHT_def (uint32_t) 0x000000CD ++#define fld_CH_KILL_LEVEL_def (uint32_t) 0x000000C0 ++#define fld_CH_AGC_ERROR_LIM_def (uint32_t) 0x00000002 ++#define fld_CH_AGC_FILTER_EN_def (uint32_t) 0x00000000 ++#define fld_CH_AGC_LOOP_SPEED_def (uint32_t) 0x00000000 + +-#define fld_HUE_ADJ_def (CARD32) 0x00000000 ++#define fld_HUE_ADJ_def (uint32_t) 0x00000000 + +-#define fld_STANDARD_SEL_def (CARD32) 0x00000000 +-#define fld_STANDARD_YC_def (CARD32) 0x00000000 ++#define fld_STANDARD_SEL_def (uint32_t) 0x00000000 ++#define fld_STANDARD_YC_def (uint32_t) 0x00000000 + +-#define fld_ADC_PDWN_def (CARD32) 0x00000001 +-#define fld_INPUT_SELECT_def (CARD32) 0x00000000 ++#define fld_ADC_PDWN_def (uint32_t) 0x00000001 ++#define fld_INPUT_SELECT_def (uint32_t) 0x00000000 + +-#define fld_ADC_PREFLO_def (CARD32) 0x00000003 +-#define fld_H_SYNC_PULSE_WIDTH_def (CARD32) 0x00000000 +-#define fld_HS_GENLOCKED_def (CARD32) 0x00000000 +-#define fld_HS_SYNC_IN_WIN_def (CARD32) 0x00000000 ++#define fld_ADC_PREFLO_def (uint32_t) 0x00000003 ++#define fld_H_SYNC_PULSE_WIDTH_def (uint32_t) 0x00000000 ++#define fld_HS_GENLOCKED_def (uint32_t) 0x00000000 ++#define fld_HS_SYNC_IN_WIN_def (uint32_t) 0x00000000 + +-#define fld_VIN_ASYNC_RST_def (CARD32) 0x00000001 +-#define fld_DVS_ASYNC_RST_def (CARD32) 0x00000001 ++#define fld_VIN_ASYNC_RST_def (uint32_t) 0x00000001 ++#define fld_DVS_ASYNC_RST_def (uint32_t) 0x00000001 + + /* Vendor IDs: */ +-#define fld_VIP_VENDOR_ID_def (CARD32) 0x00001002 +-#define fld_VIP_DEVICE_ID_def (CARD32) 0x00004d54 +-#define fld_VIP_REVISION_ID_def (CARD32) 0x00000001 ++#define fld_VIP_VENDOR_ID_def (uint32_t) 0x00001002 ++#define fld_VIP_DEVICE_ID_def (uint32_t) 0x00004d54 ++#define fld_VIP_REVISION_ID_def (uint32_t) 0x00000001 + + /* AGC Delay Register */ +-#define fld_BLACK_INT_START_def (CARD32) 0x00000031 +-#define fld_BLACK_INT_LENGTH_def (CARD32) 0x0000000f ++#define fld_BLACK_INT_START_def (uint32_t) 0x00000031 ++#define fld_BLACK_INT_LENGTH_def (uint32_t) 0x0000000f + +-#define fld_UV_INT_START_def (CARD32) 0x0000003b +-#define fld_U_INT_LENGTH_def (CARD32) 0x0000000f +-#define fld_V_INT_LENGTH_def (CARD32) 0x0000000f +-#define fld_CRDR_ACTIVE_GAIN_def (CARD32) 0x0000007a +-#define fld_CBDB_ACTIVE_GAIN_def (CARD32) 0x000000ac ++#define fld_UV_INT_START_def (uint32_t) 0x0000003b ++#define fld_U_INT_LENGTH_def (uint32_t) 0x0000000f ++#define fld_V_INT_LENGTH_def (uint32_t) 0x0000000f ++#define fld_CRDR_ACTIVE_GAIN_def (uint32_t) 0x0000007a ++#define fld_CBDB_ACTIVE_GAIN_def (uint32_t) 0x000000ac + +-#define fld_DVS_DIRECTION_def (CARD32) 0x00000000 +-#define fld_DVS_VBI_CARD8_SWAP_def (CARD32) 0x00000000 +-#define fld_DVS_CLK_SELECT_def (CARD32) 0x00000000 +-#define fld_CONTINUOUS_STREAM_def (CARD32) 0x00000000 +-#define fld_DVSOUT_CLK_DRV_def (CARD32) 0x00000001 +-#define fld_DVSOUT_DATA_DRV_def (CARD32) 0x00000001 ++#define fld_DVS_DIRECTION_def (uint32_t) 0x00000000 ++#define fld_DVS_VBI_UINT8_SWAP_def (uint32_t) 0x00000000 ++#define fld_DVS_CLK_SELECT_def (uint32_t) 0x00000000 ++#define fld_CONTINUOUS_STREAM_def (uint32_t) 0x00000000 ++#define fld_DVSOUT_CLK_DRV_def (uint32_t) 0x00000001 ++#define fld_DVSOUT_DATA_DRV_def (uint32_t) 0x00000001 + +-#define fld_COMB_CNTL0_def (CARD32) 0x09438090 +-#define fld_COMB_CNTL1_def (CARD32) 0x00000010 ++#define fld_COMB_CNTL0_def (uint32_t) 0x09438090 ++#define fld_COMB_CNTL1_def (uint32_t) 0x00000010 + +-#define fld_COMB_CNTL2_def (CARD32) 0x16161010 +-#define fld_COMB_LENGTH_def (CARD32) 0x0718038A ++#define fld_COMB_CNTL2_def (uint32_t) 0x16161010 ++#define fld_COMB_LENGTH_def (uint32_t) 0x0718038A + +-#define fld_SYNCTIP_REF0_def (CARD32) 0x00000037 +-#define fld_SYNCTIP_REF1_def (CARD32) 0x00000029 +-#define fld_CLAMP_REF_def (CARD32) 0x0000003B +-#define fld_AGC_PEAKWHITE_def (CARD32) 0x000000FF +-#define fld_VBI_PEAKWHITE_def (CARD32) 0x000000D2 ++#define fld_SYNCTIP_REF0_def (uint32_t) 0x00000037 ++#define fld_SYNCTIP_REF1_def (uint32_t) 0x00000029 ++#define fld_CLAMP_REF_def (uint32_t) 0x0000003B ++#define fld_AGC_PEAKWHITE_def (uint32_t) 0x000000FF ++#define fld_VBI_PEAKWHITE_def (uint32_t) 0x000000D2 + +-#define fld_WPA_THRESHOLD_def (CARD32) 0x000003B0 ++#define fld_WPA_THRESHOLD_def (uint32_t) 0x000003B0 + +-#define fld_WPA_TRIGGER_LO_def (CARD32) 0x000000B4 +-#define fld_WPA_TRIGGER_HIGH_def (CARD32) 0x0000021C ++#define fld_WPA_TRIGGER_LO_def (uint32_t) 0x000000B4 ++#define fld_WPA_TRIGGER_HIGH_def (uint32_t) 0x0000021C + +-#define fld_LOCKOUT_START_def (CARD32) 0x00000206 +-#define fld_LOCKOUT_END_def (CARD32) 0x00000021 ++#define fld_LOCKOUT_START_def (uint32_t) 0x00000206 ++#define fld_LOCKOUT_END_def (uint32_t) 0x00000021 + +-#define fld_CH_DTO_INC_def (CARD32) 0x00400000 +-#define fld_PLL_SGAIN_def (CARD32) 0x00000001 +-#define fld_PLL_FGAIN_def (CARD32) 0x00000002 ++#define fld_CH_DTO_INC_def (uint32_t) 0x00400000 ++#define fld_PLL_SGAIN_def (uint32_t) 0x00000001 ++#define fld_PLL_FGAIN_def (uint32_t) 0x00000002 + +-#define fld_CR_BURST_GAIN_def (CARD32) 0x0000007a +-#define fld_CB_BURST_GAIN_def (CARD32) 0x000000ac ++#define fld_CR_BURST_GAIN_def (uint32_t) 0x0000007a ++#define fld_CB_BURST_GAIN_def (uint32_t) 0x000000ac + +-#define fld_VERT_LOCKOUT_START_def (CARD32) 0x00000207 +-#define fld_VERT_LOCKOUT_END_def (CARD32) 0x0000000E ++#define fld_VERT_LOCKOUT_START_def (uint32_t) 0x00000207 ++#define fld_VERT_LOCKOUT_END_def (uint32_t) 0x0000000E + +-#define fld_H_IN_WIND_START_def (CARD32) 0x00000070 +-#define fld_V_IN_WIND_START_def (CARD32) 0x00000027 ++#define fld_H_IN_WIND_START_def (uint32_t) 0x00000070 ++#define fld_V_IN_WIND_START_def (uint32_t) 0x00000027 + +-#define fld_H_OUT_WIND_WIDTH_def (CARD32) 0x000002f4 ++#define fld_H_OUT_WIND_WIDTH_def (uint32_t) 0x000002f4 + +-#define fld_V_OUT_WIND_WIDTH_def (CARD32) 0x000000f0 ++#define fld_V_OUT_WIND_WIDTH_def (uint32_t) 0x000000f0 + +-#define fld_HS_LINE_TOTAL_def (CARD32) 0x0000038E ++#define fld_HS_LINE_TOTAL_def (uint32_t) 0x0000038E + +-#define fld_MIN_PULSE_WIDTH_def (CARD32) 0x0000002F +-#define fld_MAX_PULSE_WIDTH_def (CARD32) 0x00000046 ++#define fld_MIN_PULSE_WIDTH_def (uint32_t) 0x0000002F ++#define fld_MAX_PULSE_WIDTH_def (uint32_t) 0x00000046 + +-#define fld_WIN_CLOSE_LIMIT_def (CARD32) 0x0000004D +-#define fld_WIN_OPEN_LIMIT_def (CARD32) 0x000001B7 ++#define fld_WIN_CLOSE_LIMIT_def (uint32_t) 0x0000004D ++#define fld_WIN_OPEN_LIMIT_def (uint32_t) 0x000001B7 + +-#define fld_VSYNC_INT_TRIGGER_def (CARD32) 0x000002AA ++#define fld_VSYNC_INT_TRIGGER_def (uint32_t) 0x000002AA + +-#define fld_VSYNC_INT_HOLD_def (CARD32) 0x0000001D ++#define fld_VSYNC_INT_HOLD_def (uint32_t) 0x0000001D + +-#define fld_VIN_M0_def (CARD32) 0x00000039 +-#define fld_VIN_N0_def (CARD32) 0x0000014c +-#define fld_MNFLIP_EN_def (CARD32) 0x00000000 +-#define fld_VIN_P_def (CARD32) 0x00000006 +-#define fld_REG_CLK_SEL_def (CARD32) 0x00000000 ++#define fld_VIN_M0_def (uint32_t) 0x00000039 ++#define fld_VIN_N0_def (uint32_t) 0x0000014c ++#define fld_MNFLIP_EN_def (uint32_t) 0x00000000 ++#define fld_VIN_P_def (uint32_t) 0x00000006 ++#define fld_REG_CLK_SEL_def (uint32_t) 0x00000000 + +-#define fld_VIN_M1_def (CARD32) 0x00000000 +-#define fld_VIN_N1_def (CARD32) 0x00000000 +-#define fld_VIN_DRIVER_SEL_def (CARD32) 0x00000000 +-#define fld_VIN_MNFLIP_REQ_def (CARD32) 0x00000000 +-#define fld_VIN_MNFLIP_DONE_def (CARD32) 0x00000000 +-#define fld_TV_LOCK_TO_VIN_def (CARD32) 0x00000000 +-#define fld_TV_P_FOR_WINCLK_def (CARD32) 0x00000004 ++#define fld_VIN_M1_def (uint32_t) 0x00000000 ++#define fld_VIN_N1_def (uint32_t) 0x00000000 ++#define fld_VIN_DRIVER_SEL_def (uint32_t) 0x00000000 ++#define fld_VIN_MNFLIP_REQ_def (uint32_t) 0x00000000 ++#define fld_VIN_MNFLIP_DONE_def (uint32_t) 0x00000000 ++#define fld_TV_LOCK_TO_VIN_def (uint32_t) 0x00000000 ++#define fld_TV_P_FOR_WINCLK_def (uint32_t) 0x00000004 + +-#define fld_VINRST_def (CARD32) 0x00000001 +-#define fld_VIN_CLK_SEL_def (CARD32) 0x00000000 ++#define fld_VINRST_def (uint32_t) 0x00000001 ++#define fld_VIN_CLK_SEL_def (uint32_t) 0x00000000 + +-#define fld_VS_FIELD_BLANK_START_def (CARD32) 0x00000206 ++#define fld_VS_FIELD_BLANK_START_def (uint32_t) 0x00000206 + +-#define fld_VS_FIELD_BLANK_END_def (CARD32) 0x0000000A ++#define fld_VS_FIELD_BLANK_END_def (uint32_t) 0x0000000A + +-/*#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000105 */ +-#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000001 +-#define fld_VS_FRAME_TOTAL_def (CARD32) 0x00000217 ++/*#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000105 */ ++#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000001 ++#define fld_VS_FRAME_TOTAL_def (uint32_t) 0x00000217 + +-#define fld_SYNC_TIP_START_def (CARD32) 0x00000372 +-#define fld_SYNC_TIP_LENGTH_def (CARD32) 0x0000000F ++#define fld_SYNC_TIP_START_def (uint32_t) 0x00000372 ++#define fld_SYNC_TIP_LENGTH_def (uint32_t) 0x0000000F + +-#define fld_GAIN_FORCE_DATA_def (CARD32) 0x00000000 +-#define fld_GAIN_FORCE_EN_def (CARD32) 0x00000000 +-#define fld_I_CLAMP_SEL_def (CARD32) 0x00000003 +-#define fld_I_AGC_SEL_def (CARD32) 0x00000001 +-#define fld_EXT_CLAMP_CAP_def (CARD32) 0x00000001 +-#define fld_EXT_AGC_CAP_def (CARD32) 0x00000001 +-#define fld_DECI_DITHER_EN_def (CARD32) 0x00000001 +-#define fld_ADC_PREFHI_def (CARD32) 0x00000000 +-#define fld_ADC_CH_GAIN_SEL_def (CARD32) 0x00000001 ++#define fld_GAIN_FORCE_DATA_def (uint32_t) 0x00000000 ++#define fld_GAIN_FORCE_EN_def (uint32_t) 0x00000000 ++#define fld_I_CLAMP_SEL_def (uint32_t) 0x00000003 ++#define fld_I_AGC_SEL_def (uint32_t) 0x00000001 ++#define fld_EXT_CLAMP_CAP_def (uint32_t) 0x00000001 ++#define fld_EXT_AGC_CAP_def (uint32_t) 0x00000001 ++#define fld_DECI_DITHER_EN_def (uint32_t) 0x00000001 ++#define fld_ADC_PREFHI_def (uint32_t) 0x00000000 ++#define fld_ADC_CH_GAIN_SEL_def (uint32_t) 0x00000001 + +-#define fld_HS_PLL_SGAIN_def (CARD32) 0x00000003 ++#define fld_HS_PLL_SGAIN_def (uint32_t) 0x00000003 + +-#define fld_NREn_def (CARD32) 0x00000000 +-#define fld_NRGainCntl_def (CARD32) 0x00000000 +-#define fld_NRBWTresh_def (CARD32) 0x00000000 +-#define fld_NRGCTresh_def (CARD32) 0x00000000 +-#define fld_NRCoefDespeclMode_def (CARD32) 0x00000000 ++#define fld_NREn_def (uint32_t) 0x00000000 ++#define fld_NRGainCntl_def (uint32_t) 0x00000000 ++#define fld_NRBWTresh_def (uint32_t) 0x00000000 ++#define fld_NRGCTresh_def (uint32_t) 0x00000000 ++#define fld_NRCoefDespeclMode_def (uint32_t) 0x00000000 + +-#define fld_GPIO_5_OE_def (CARD32) 0x00000000 +-#define fld_GPIO_6_OE_def (CARD32) 0x00000000 ++#define fld_GPIO_5_OE_def (uint32_t) 0x00000000 ++#define fld_GPIO_6_OE_def (uint32_t) 0x00000000 + +-#define fld_GPIO_5_OUT_def (CARD32) 0x00000000 +-#define fld_GPIO_6_OUT_def (CARD32) 0x00000000 ++#define fld_GPIO_5_OUT_def (uint32_t) 0x00000000 ++#define fld_GPIO_6_OUT_def (uint32_t) 0x00000000 + + /* End of field default values. */ + diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 236d2de..9e3c57a 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.8.0 -Release: 15%{?dist} +Release: 16%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -20,8 +20,6 @@ Source3: radeon.xinf Patch1: radeon-git-upstream-fixes.patch Patch2: radeon-git-upstream-fixes2.patch Patch4: radeon-6.7.196-faster-ddc.patch -Patch5: radeon-initial-cloning.patch -Patch6: radeon-rs482-sucks.patch # Rage 128 patches (100-199) Patch100: r128-bios-size.patch @@ -51,8 +49,6 @@ X.Org X11 ati video driver. %patch1 -p1 -b .git %patch2 -p1 -b .git2 #patch4 -p1 -b .ddc -%patch5 -p1 -b .clone -%patch6 -p1 -b .you-suck %patch100 -p1 -b .r128-bios %patch200 -p1 -b .mach64-ia64 @@ -95,6 +91,10 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Sat May 24 2008 Dave Airlie 6.8.0-16 +- Fix PLL on r600 LVDS (#444542) +- update to other upstream fixes + * Mon May 12 2008 Dave Airlie 6.8.0-15 - The RS482 sucks - same pci id, mobile and non-mobile parts.