diff --git a/radeon-git-upstream-fixes.patch b/radeon-git-upstream-fixes.patch index 6217c37..c2704b6 100644 --- a/radeon-git-upstream-fixes.patch +++ b/radeon-git-upstream-fixes.patch @@ -1,3 +1,83 @@ +commit 7f4db96123fdcba9874226352802d702c2a498bd +Author: Dave Airlie +Date: Fri Feb 8 10:47:10 2008 +1000 + + add rv670 pciids + +commit e8899b9978291c62a65f468c92f340f65ad5479d +Author: Alex Deucher +Date: Thu Feb 7 19:27:38 2008 -0500 + + R6xx: fix ddc after my i2c rework + + Seems r6xx does something different for its i2c table, + revert to the old behavior for now. + +commit 435de6c4e46ff2bebd4cee58888a66b936cd3fdf +Author: Alex Deucher +Date: Thu Feb 7 19:14:13 2008 -0500 + + RADEON: sync up with latest upstream versions + + atombios.h + ObjectID.h + +commit 692789a293970f70b88ccb6adcf0676d8b495ae2 +Author: George Sapountzis +Date: Thu Feb 7 18:03:37 2008 +0200 + + mach64: factor out BIOS multimedia parsing + +commit 933328ffd6d1d872a18d3de8624c4df845a64588 +Author: George Sapountzis +Date: Thu Feb 7 18:03:03 2008 +0200 + + mach64: complement hint for sparc + +commit 956c8c81f3ff434930a0cb17b027b2f8e4eeabb2 +Author: George Sapountzis +Date: Thu Feb 7 18:02:31 2008 +0200 + + mach64: consolidate refclk #2 + +commit dce4cc26a8e2bf53805ec63763243f3ff6b4a6d3 +Author: George Sapountzis +Date: Thu Feb 7 18:02:17 2008 +0200 + + mach64: consolidate refclk #1 + +commit f7ed807f0d82a7446ebc4acdd4e94df44a675f19 +Author: George Sapountzis +Date: Thu Feb 7 18:01:59 2008 +0200 + + mach64: cosmetic + +commit cda1cd198f33c26ef1b51532a2126468369743b8 +Author: George Sapountzis +Date: Thu Feb 7 18:01:33 2008 +0200 + + mach64: factor out BIOS clock parsing + +commit 73ff279469be9c7cbf9f533b85fcb553694ff413 +Author: George Sapountzis +Date: Thu Feb 7 18:00:55 2008 +0200 + + mach64: BIOSBase is no longer used + +commit caea326cc6f1932bb299f451be013651a5749ea7 +Author: Dave Airlie +Date: Wed Feb 6 06:36:13 2008 +1000 + + r300: move fragprog setup code to prepare composite for now + +commit 470cd6a401c6a3e8fea981a8fe97c28be3cfb81d +Author: Dave Airlie +Date: Wed Feb 6 06:04:13 2008 +1000 + + r300: remove r300 specific vertex emission + + Set the vertex and fragment engine to expect the mask coords. + commit f65e8dfac23adfa199026765fe3a1ea08cf4da67 Author: Alex Deucher Date: Sun Feb 3 00:09:59 2008 -0500 @@ -4763,10 +4843,10 @@ index 0000000..24c25fc +// EOF diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h new file mode 100644 -index 0000000..a630c69 +index 0000000..e6d41fe --- /dev/null +++ b/src/AtomBios/includes/ObjectID.h -@@ -0,0 +1,448 @@ +@@ -0,0 +1,484 @@ +/* +* Copyright 2006-2007 Advanced Micro Devices, Inc. +* @@ -4845,6 +4925,8 @@ index 0000000..a630c69 +#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B +#define ENCODER_OBJECT_ID_DP_AN9801 0x1C +#define ENCODER_OBJECT_ID_DP_DP501 0x1D ++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F + +/****************************************************/ +/* Connector Object ID Definition */ @@ -4941,6 +5023,10 @@ index 0000000..a630c69 +#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 +#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 +#define ENCODER_VT1625_ENUM_ID1 0x211A ++#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B ++#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C ++#define ENCODER_DP_DP501_ENUM_ID1 0x211D ++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E +*/ +#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -5073,6 +5159,19 @@ index 0000000..a630c69 +#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) ++ +/****************************************************/ +/* Connector Object ID definition - Shared with BIOS */ +/****************************************************/ @@ -5118,6 +5217,10 @@ index 0000000..a630c69 + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + ++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) ++ +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) @@ -5126,6 +5229,10 @@ index 0000000..a630c69 + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) + ++#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) ++ +#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) @@ -5166,6 +5273,10 @@ index 0000000..a630c69 + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) + ++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) ++ +#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) @@ -5186,6 +5297,11 @@ index 0000000..a630c69 +#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) ++ +/****************************************************/ +/* Router Object ID definition - Shared with BIOS */ +/****************************************************/ @@ -5217,10 +5333,10 @@ index 0000000..a630c69 + diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h new file mode 100644 -index 0000000..863de2e +index 0000000..16fcf2d --- /dev/null +++ b/src/AtomBios/includes/atombios.h -@@ -0,0 +1,4306 @@ +@@ -0,0 +1,4436 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * @@ -5434,8 +5550,8 @@ index 0000000..863de2e + USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 + USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON + USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init -+ USHORT VRAM_BlockVenderDetection; -+ USHORT SetClocksRatio; ++ USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios ++ USHORT DIGxEncoderControl; //Only used by Bios + USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 + USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed @@ -5485,7 +5601,7 @@ index 0000000..863de2e + USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT VRAM_BlockDetectionByStrap; + USHORT MemoryCleanUp; //Atomic Table, only used by Bios -+ USHORT ReadEDIDFromHWAssistedI2C; //Function Table,only used by Bios ++ USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios + USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components + USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components + USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init @@ -5513,6 +5629,8 @@ index 0000000..863de2e + USHORT DPEncoderService; //Function Table,only used by Bios +}ATOM_MASTER_LIST_OF_COMMAND_TABLES; + ++#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction ++ +#define UNIPHYTransmitterControl DIG1TransmitterControl +#define LVTMATransmitterControl DIG2TransmitterControl +#define SetCRTC_DPM_State GetConditionalGoldenSetting @@ -5650,10 +5768,10 @@ index 0000000..863de2e +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient -+ UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx -+ // 1: PS2 ++ UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder ++ // 7: ATOM_ENCODER_INIT Initialize DAC +}DAC_ENCODER_CONTROL_PARAMETERS; + +#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS @@ -5670,25 +5788,22 @@ index 0000000..863de2e +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucConfig; -+ // [2] Link Select: -+ // =0: PHY linkA if bfLane<3 -+ // =1: PHY linkB if bfLanes<3 -+ // =0: PHY linkA+B if bfLanes=3 -+ // [3] Transmitter Sel -+ // =0: UNIPHY or PCIEPHY -+ // =1: LVTMA -+ UCHAR ucAction; // =0: turn off encoder -+ // =1: turn on encoder -+ union{ ++ // [2] Link Select: ++ // =0: PHY linkA if bfLane<3 ++ // =1: PHY linkB if bfLanes<3 ++ // =0: PHY linkA+B if bfLanes=3 ++ // [3] Transmitter Sel ++ // =0: UNIPHY or PCIEPHY ++ // =1: LVTMA ++ UCHAR ucAction; // =0: turn off encoder ++ // =1: turn on encoder + UCHAR ucEncoderMode; -+ // =0: DP encoder -+ // =1: LVDS encoder -+ // =2: DVI encoder -+ // =3: HDMI encoder -+ // =4: SDVO encoder -+ UCHAR ucEncoderType; -+ }; -+ UCHAR ucLaneNum; // how many lanes to enable ++ // =0: DP encoder ++ // =1: LVDS encoder ++ // =2: DVI encoder ++ // =3: HDMI encoder ++ // =4: SDVO encoder ++ UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucReserved[2]; +}DIG_ENCODER_CONTROL_PARAMETERS; +#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS @@ -5696,10 +5811,14 @@ index 0000000..863de2e +#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION + +//ucConfig ++#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 ++#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 ++#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA ++#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB +#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 +#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 +#define ATOM_ENCODER_CONFIG_LVTMA 0x08 @@ -5720,12 +5839,19 @@ index 0000000..863de2e +#define ATOM_ENCODER_MODE_CV 14 +#define ATOM_ENCODER_MODE_CRT 15 + ++typedef struct _ATOM_DP_VS_MODE ++{ ++ UCHAR ucLaneSel; ++ UCHAR ucLaneSet; ++}ATOM_DP_VS_MODE; ++ +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h ++ ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; + UCHAR ucConfig; + // [0]=0: 4 lane Link, @@ -5757,7 +5883,13 @@ index 0000000..863de2e +#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 -+#define ATOM_TRANSMITTER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA ++#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 ++#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 ++ ++#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE ++#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE ++#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE ++ +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 @@ -5779,10 +5911,10 @@ index 0000000..863de2e +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 +#define ATOM_TRANSMITTER_ACTION_INIT 7 -+#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 8 -+#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 9 ++#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 ++#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 +#define ATOM_TRANSMITTER_ACTION_SETUP 10 -+ ++#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 + +/****************************Device Output Control Command Table Definitions**********************/ +typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS @@ -5949,12 +6081,22 @@ index 0000000..863de2e +//ATOM_ENCODER_MODE_CV 14 +//ATOM_ENCODER_MODE_CRT 15 + ++//ucDVOConfig ++//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 ++//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 ++//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 ++//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c ++//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 ++//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 ++//#define DVO_ENCODER_CONFIG_24BIT 0x08 ++ +//ucMiscInfo: also changed, see below +#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 +#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 +#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 +#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 ++#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 + +typedef struct _PIXEL_CLOCK_PARAMETERS_V3 +{ @@ -5966,8 +6108,13 @@ index 0000000..863de2e + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h ++ union ++ { + UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ ++ UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit ++ }; + UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel ++ // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source +}PIXEL_CLOCK_PARAMETERS_V3; + +#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 @@ -5986,6 +6133,8 @@ index 0000000..863de2e + UCHAR ucReserved[3]; +}ADJUST_DISPLAY_PLL_PARAMETERS; + ++#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 ++ +#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS + +typedef struct _ENABLE_YUV_PARAMETERS @@ -6701,25 +6850,41 @@ index 0000000..863de2e + ULONG ulReserved1[2]; //must be 0x0 for the reserved + ULONG ulBootUpUMAClock; //in 10kHz unit + ULONG ulBootUpSidePortClock; //in 10kHz unit -+ ULONG ulReserved2[8]; //must be 0x0 for the reserved ++ ULONG ulMinSidePortClock; //in 10kHz unit ++ ULONG ulReserved2[6]; //must be 0x0 for the reserved ++ ULONG ulSystemConfig; //see explanation below + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulDDISlot1Config; + ULONG ulDDISlot2Config; -+ UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved -+ UCHAR ucReserved; //must be 0x0 for the reserved ++ UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved ++ UCHAR ucUMAChannelNumber; + UCHAR ucDockingPinBit; + UCHAR ucDockingPinPolarity; + ULONG ulDockingPinCFGInfo; -+ ULONG ulCPUCapInfo; -+ ULONG ulReserved3[107]; //must be 0x0 ++ ULONG ulCPUCapInfo; ++ USHORT usNumberOfCyclesInPeriod; ++ USHORT usMaxNBVoltage; ++ USHORT usMinNBVoltage; ++ USHORT usBootUpNBVoltage; ++ ULONG ulHTLinkFreq; //in 10Khz ++ USHORT usMinHTLinkWidth; ++ USHORT usMaxHTLinkWidth; ++ USHORT usUMASyncStartDelay; ++ USHORT usUMADataReturnTime; ++ USHORT usLinkStatusZeroTime; ++ USHORT usReserved; ++ ULONG ulReserved3[101]; //must be 0x0 +}ATOM_INTEGRATED_SYSTEM_INFO_V2; + +/* +ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; +ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present -+ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present ++ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock + ++ulSystemConfig: ++Bit[0]: =1 PowerExpress mode =0 Non-PowerExpress mode; ++Bit[1]=1: system is running at overdrived engine clock =0:system is not running at overdrived engine clock + +ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. + @@ -6730,18 +6895,62 @@ index 0000000..863de2e + [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) + [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) + [15:8] - Lane configuration attribute; -+ [31:16]- Reserved ++ [23:16]- Connector type, possible value: ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D ++ CONNECTOR_OBJECT_ID_HDMI_TYPE_A ++ CONNECTOR_OBJECT_ID_DISPLAYPORT ++ [31:24]- Reserved ++ ++ulDDISlot2Config: Same as Slot1. ++ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. ++For IGP, Hypermemory is the only memory type showed in CCC. + -+ulDDISlot2Config: Same as Slot1 ++ucUMAChannelNumber: how many channels for the UMA; + +ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin +ucDockingPinBit: which bit in this register to read the pin status; +ucDockingPinPolarity:Polarity of the pin when docked; + -+ulCPUCapInfo: TBD -+ ++ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 ++ ++usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. ++usMaxNBVoltage:Voltage regulator dependent PWM value.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ++usMinNBVoltage:Voltage regulator dependent PWM value.Set this one to 0x00 if VC without PWM or no VC at all. ++usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. ++ ++ ++ulHTLinkFreq: Current HT link Frequency in 10Khz. ++usMinHTLinkWidth: ++usMaxHTLinkWidth: ++usUMASyncStartDelay: Memory access latency, required for watermark calculation ++usUMADataReturnTime: Memory access latency, required for watermark calculation ++usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us ++for Griffin or Greyhound. SBIOS needs to convert to actual time by: ++ if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) ++ if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) ++ if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) ++ if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) +*/ + ++#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 ++#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 ++ ++#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF ++ ++#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F ++#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 ++#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 ++#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 ++#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 ++#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 ++ ++#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 ++#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 ++#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 ++ ++#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 ++ +#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 +#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 +#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 @@ -6780,7 +6989,7 @@ index 0000000..863de2e +#define ATOM_DEVICE_TV2_INDEX 0x00000006 +#define ATOM_DEVICE_DFP2_INDEX 0x00000007 +#define ATOM_DEVICE_CV_INDEX 0x00000008 -+#define ATOM_DEVICE_DFP3_INDEX 0x00000009 ++#define ATOM_DEVICE_DFP3_INDEX 0x00000009 +#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A +#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B +#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C @@ -7063,8 +7272,8 @@ index 0000000..863de2e + UCHAR ucHBorder; + UCHAR ucVBorder; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; -+ UCHAR ucReserved1; -+ UCHAR ucReserved2; ++ UCHAR ucInternalModeNumber; ++ UCHAR ucRefreshRate; +}ATOM_DTD_FORMAT; + +#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 @@ -7236,6 +7445,7 @@ index 0000000..863de2e + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; ++ /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ + ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; +}ATOM_ANALOG_TV_INFO; + @@ -7260,8 +7470,8 @@ index 0000000..863de2e +#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) +#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) +#define DFP_ENCODER_TYPE_OFFSET 0x80 -+#define DP_ENCODER_LANE_NUMBER 0x84 -+#define DP_ENCODER_LINK_RATE 0x88 ++#define DP_ENCODER_LANE_NUM_OFFSET 0x84 ++#define DP_ENCODER_LINK_RATE_OFFSET 0x88 + +#define ATOM_HWICON1_SURFACE_ADDR 0 +#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) @@ -8049,6 +8259,9 @@ index 0000000..863de2e + +#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL + ++#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L ++#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L ++ +#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L +#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L +#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L @@ -8355,7 +8568,8 @@ index 0000000..863de2e +{ + UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 + UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION -+ UCHAR ucPadding[2]; ++ UCHAR ucTVStandard; // ++ UCHAR ucPadding[1]; +}ENABLE_SCALER_PARAMETERS; +#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS + @@ -8388,6 +8602,15 @@ index 0000000..863de2e + UCHAR ucPadding[3]; +}ENABLE_GRAPH_SURFACE_PARAMETERS; + ++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 ++{ ++ USHORT usHight; // Image Hight ++ USHORT usWidth; // Image Width ++ UCHAR ucSurface; // Surface 1 or 2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[2]; ++}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; ++ +typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION +{ + ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; @@ -8421,6 +8644,7 @@ index 0000000..863de2e +#define INDIRECT_IO_MC 2 +#define INDIRECT_IO_PCIE 3 +#define INDIRECT_IO_PCIEP 4 ++#define INDIRECT_IO_NBMISC 5 + +#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ +#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE @@ -8430,6 +8654,8 @@ index 0000000..863de2e +#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE +#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ +#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE ++#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ ++#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE + +typedef struct _ATOM_OEM_INFO +{ @@ -8558,6 +8784,9 @@ index 0000000..863de2e +#define _16Mx16 0x22 +#define _16Mx32 0x23 +#define _32Mx16 0x32 ++#define _32Mx32 0x33 ++#define _64Mx8 0x41 ++#define _64Mx16 0x42 + +#define SAMSUNG 0x1 +#define INFINEON 0x2 @@ -8568,7 +8797,10 @@ index 0000000..863de2e +#define MOSEL 0x7 +#define WINBOND 0x8 +#define ESMT 0x9 -+#define MICRO 0xF ++#define MICRON 0xF ++ ++#define QIMONDA INFINEON ++#define PROMOS MOSEL + +#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 + @@ -8684,12 +8916,6 @@ index 0000000..863de2e + ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec +}ATOM_VRAM_MODULE_V3; + -+//ATOM_VRAM_MODULE_V3.ucFlag -+#define Mx_FLAG_RDBI_ENABLE 0x01 -+#define Mx_FLAG_WDBI_ENABLE 0x02 -+#define Mx_FLAG_DQ_QS_AUTO_CALI 0x04 -+#define Mx_FLAG_STROBE_SINGLE_END 0x08 -+#define Mx_FLAG_DIS_MEM_TRAINING 0x10 + +//ATOM_VRAM_MODULE_V3.ucNPL_RT +#define NPL_RT_MASK 0x0f @@ -9049,6 +9275,28 @@ index 0000000..863de2e +#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) + + ++typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS ++{ ++ UCHAR ucI2CSpeed; ++ union ++ { ++ UCHAR ucRegIndex; ++ UCHAR ucStatus; ++ }; ++ USHORT lpI2CDataOut; ++ UCHAR ucFlag; ++ UCHAR ucTransBytes; ++ UCHAR ucSlaveAddr; ++ UCHAR ucLineNumber; ++}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; ++ ++#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS ++ ++//ucFlag ++#define HW_I2C_WRITE 1 ++#define HW_I2C_READ 0 ++ ++ +/****************************************************************************/ +//Portion VI: Definitinos being oboselete +/****************************************************************************/ @@ -9427,17 +9675,6 @@ index 0000000..863de2e +#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE +#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE + -+#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L -+#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L -+#define ATOM_S6_REQ_SCALER2_H 0x00004000L -+#define ATOM_S6_REQ_SCALER2_V 0x00008000L -+ -+#define ATOM_S3_SCALER1_ACTIVE_H 0x00001000L -+#define ATOM_S3_SCALER1_ACTIVE_V 0x00002000L -+ -+#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL -+#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO -+ +//New device naming, remove them when both DAL/VBIOS is ready +#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS +#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS @@ -9521,7 +9758,16 @@ index 0000000..863de2e +#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL + +/*********************************************************************************/ -+ ++#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L ++#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L ++#define ATOM_S6_REQ_SCALER2_H 0x00004000L ++#define ATOM_S6_REQ_SCALER2_V 0x00008000L ++ ++#define ATOM_S3_SCALER1_ACTIVE_H ATOM_S3_LCD_FULLEXPANSION_ACTIVE ++#define ATOM_S3_SCALER1_ACTIVE_V ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE ++ ++#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL ++#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO +//========================================================================================== + +#pragma pack() // BIOS data must use byte aligment @@ -10619,7 +10865,7 @@ index 48ab1cd..e86e50c 100644 #endif /* ___ATI_H___ */ diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index ad54f64..26d2f09 100644 +index ad54f64..330d1a9 100644 --- a/src/ati_pciids_gen.h +++ b/src/ati_pciids_gen.h @@ -195,6 +195,7 @@ @@ -10630,7 +10876,7 @@ index ad54f64..26d2f09 100644 #define PCI_CHIP_RV370_5B64 0x5B64 #define PCI_CHIP_RV370_5B65 0x5B65 #define PCI_CHIP_RV280_5C61 0x5C61 -@@ -215,5 +216,137 @@ +@@ -215,5 +216,143 @@ #define PCI_CHIP_RV410_5E4C 0x5E4C #define PCI_CHIP_RV410_5E4D 0x5E4D #define PCI_CHIP_RV410_5E4F 0x5E4F @@ -10756,6 +11002,12 @@ index ad54f64..26d2f09 100644 +#define PCI_CHIP_RV610_94C9 0x94C9 +#define PCI_CHIP_RV610_94CB 0x94CB +#define PCI_CHIP_RV610_94CC 0x94CC ++#define PCI_CHIP_RV670_9500 0x9500 ++#define PCI_CHIP_RV670_9501 0x9501 ++#define PCI_CHIP_RV670_9505 0x9505 ++#define PCI_CHIP_RV670_9507 0x9507 ++#define PCI_CHIP_RV670_950F 0x950F ++#define PCI_CHIP_RV670_9511 0x9511 +#define PCI_CHIP_RV630_9580 0x9580 +#define PCI_CHIP_RV630_9581 0x9581 +#define PCI_CHIP_RV630_9583 0x9583 @@ -10844,26 +11096,61 @@ index 44cd188..e59d6eb 100644 */ typedef enum diff --git a/src/aticlock.c b/src/aticlock.c -index 2aa65c4..8dd79d4 100644 +index 2aa65c4..f4de77f 100644 --- a/src/aticlock.c +++ b/src/aticlock.c -@@ -139,6 +139,16 @@ ATIClockPreInit +@@ -139,6 +139,17 @@ ATIClockPreInit (double)pATI->ReferenceNumerator / ((double)pATI->ReferenceDenominator * 1000.0)); +#if defined(__sparc__) -+ if (pATI->ReferenceNumerator != 315000 && -+ pATI->ReferenceDenominator != 11) ++ if ((pATI->refclk / 100000) != 286 && ++ (pATI->refclk / 100000) != 295) + { + xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, + "If modes do not work on Ultra 5/10 or Blade 100/150,\n" -+ "set option \"reference_clock\" to \"28.636 MHz\"\n"); ++ "\tset option \"reference_clock\" to \"28.636 MHz\"" ++ " or \"29.5 MHz\"\n"); + } +#endif + if (pATI->ProgrammableClock == ATI_CLOCK_CH8398) { /* First two are fixed */ pScreenInfo->numClocks = 2; +diff --git a/src/aticonfig.c b/src/aticonfig.c +index 1e119e0..9102497 100644 +--- a/src/aticonfig.c ++++ b/src/aticonfig.c +@@ -471,28 +471,7 @@ ATIProcessOptions + pATI->Cursor = ATI_CURSOR_HARDWARE; + } + +- /* Only set the reference clock if it hasn't already been determined */ +- if (!pATI->ReferenceNumerator || !pATI->ReferenceDenominator) +- { +- switch ((int)(ReferenceClock / ((double)100000.0))) +- { +- case 143: +- pATI->ReferenceNumerator = 157500; +- pATI->ReferenceDenominator = 11; +- break; +- +- case 286: +- pATI->ReferenceNumerator = 315000; +- pATI->ReferenceDenominator = 11; +- break; +- +- default: +- pATI->ReferenceNumerator = +- (int)(ReferenceClock / ((double)1000.0)); +- pATI->ReferenceDenominator = 1; +- break; +- } +- } ++ pATI->refclk = (int)ReferenceClock; + + pATI->useEXA = FALSE; + if (pATI->OptionAccel) diff --git a/src/aticonsole.c b/src/aticonsole.c index bd5ec9c..8efe897 100644 --- a/src/aticonsole.c @@ -11757,10 +12044,280 @@ index f24f8fb..2953964 100644 #define PCI_CHIP_AMD761 0x700E diff --git a/src/atipreinit.c b/src/atipreinit.c -index 8114f51..2420b9f 100644 +index 8114f51..8c67932 100644 --- a/src/atipreinit.c +++ b/src/atipreinit.c -@@ -301,7 +301,7 @@ ATIPreInit +@@ -123,6 +123,253 @@ ATIPrintNoiseIfRequested + ATIPrintRegisters(pATI); + } + ++#define BIOS_SIZE 0x00010000U /* 64kB */ ++#define BIOSByte(_n) ((CARD8)(BIOS[_n])) ++#define BIOSWord(_n) ((CARD16)(BIOS[_n] | \ ++ (BIOS[(_n) + 1] << 8))) ++ ++/* ++ * For Mach64 adapters, pick up, from the BIOS, the type of programmable ++ * clock generator (if any), and various information about it. ++ */ ++static void ++ati_bios_clock ++( ++ ScrnInfoPtr pScreenInfo, ++ ATIPtr pATI, ++ CARD8 *BIOS, ++ unsigned int ClockTable, ++ GDevPtr pGDev ++) ++{ ++ CARD16 ClockDac; ++ ++ if (ClockTable > 0) ++ { ++ pATI->ProgrammableClock = BIOSByte(ClockTable); ++ pATI->ClockNumberToProgramme = BIOSByte(ClockTable + 0x06U); ++ pATI->refclk = BIOSWord(ClockTable + 0x08U); ++ pATI->refclk *= 10000; ++ } ++ else ++ { ++ /* ++ * Compensate for BIOS absence. Note that the reference ++ * frequency has already been set by option processing. ++ */ ++ if ((pATI->DAC & ~0x0FU) == ATI_DAC_INTERNAL) ++ { ++ pATI->ProgrammableClock = ATI_CLOCK_INTERNAL; ++ } ++ else switch (pATI->DAC) ++ { ++ case ATI_DAC_STG1703: ++ pATI->ProgrammableClock = ATI_CLOCK_STG1703; ++ break; ++ ++ case ATI_DAC_CH8398: ++ pATI->ProgrammableClock = ATI_CLOCK_CH8398; ++ break; ++ ++ case ATI_DAC_ATT20C408: ++ pATI->ProgrammableClock = ATI_CLOCK_ATT20C408; ++ break; ++ ++ case ATI_DAC_IBMRGB514: ++ pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; ++ break; ++ ++ default: /* Provisional */ ++ pATI->ProgrammableClock = ATI_CLOCK_ICS2595; ++ break; ++ } ++ ++ /* This should be safe for all generators except IBM's RGB514 */ ++ pATI->ClockNumberToProgramme = 3; ++ } ++ ++ pATI->ClockDescriptor = ATIClockDescriptors[ATI_CLOCK_FIXED]; ++ ++ if ((pATI->ProgrammableClock > ATI_CLOCK_FIXED) && ++ (pATI->ProgrammableClock < ATI_CLOCK_MAX)) ++ { ++ /* ++ * Graphics PRO TURBO 1600's are unusual in that an ICS2595 is used ++ * to generate clocks for VGA modes, and an IBM RGB514 is used for ++ * accelerator modes. ++ */ ++ if ((pATI->ProgrammableClock == ATI_CLOCK_ICS2595) && ++ (pATI->DAC == ATI_DAC_IBMRGB514)) ++ pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; ++ ++ pATI->ClockDescriptor = ATIClockDescriptors[pATI->ProgrammableClock]; ++ } ++ ++ ClockDac = pATI->DAC; ++ switch (pATI->ProgrammableClock) ++ { ++ case ATI_CLOCK_ICS2595: ++ /* ++ * Pick up reference divider (43 or 46) appropriate to the chip ++ * revision level. ++ */ ++ if (ClockTable > 0) ++ pATI->ClockDescriptor.MinM = ++ pATI->ClockDescriptor.MaxM = BIOSWord(ClockTable + 0x0AU); ++ else if (!xf86NameCmp(pGDev->clockchip, "ATI 18818-0")) ++ pATI->ClockDescriptor.MinM = ++ pATI->ClockDescriptor.MaxM = 43; ++ else if (!xf86NameCmp(pGDev->clockchip, "ATI 18818-1")) ++ pATI->ClockDescriptor.MinM = ++ pATI->ClockDescriptor.MaxM = 46; ++ else ++ pATI->ProgrammableClock = ATI_CLOCK_UNKNOWN; ++ break; ++ ++ case ATI_CLOCK_STG1703: ++ /* This one's also a RAMDAC */ ++ ClockDac = ATI_DAC_STG1703; ++ break; ++ ++ case ATI_CLOCK_CH8398: ++ /* This one's also a RAMDAC */ ++ ClockDac = ATI_DAC_CH8398; ++ break; ++ ++ case ATI_CLOCK_INTERNAL: ++ /* ++ * The reference divider has already been programmed by BIOS ++ * initialisation. Because, there is only one reference ++ * divider for all generated frequencies (including MCLK), it ++ * cannot be changed without reprogramming all clocks every ++ * time one of them needs a different reference divider. ++ * ++ * Besides, it's not a good idea to change the reference ++ * divider. BIOS initialisation sets it to a value that ++ * effectively prevents generating frequencies beyond the ++ * graphics controller's tolerance. ++ */ ++ pATI->ClockDescriptor.MinM = ++ pATI->ClockDescriptor.MaxM = ATIMach64GetPLLReg(PLL_REF_DIV); ++ ++ /* The DAC is also integrated */ ++ if ((pATI->DAC & ~0x0FU) != ATI_DAC_INTERNAL) ++ ClockDac = ATI_DAC_INTERNAL; ++ ++ break; ++ ++ case ATI_CLOCK_ATT20C408: ++ /* This one's also a RAMDAC */ ++ ClockDac = ATI_DAC_ATT20C408; ++ break; ++ ++ case ATI_CLOCK_IBMRGB514: ++ /* This one's also a RAMDAC */ ++ ClockDac = ATI_DAC_IBMRGB514; ++ pATI->ClockNumberToProgramme = 7; ++ break; ++ ++ default: ++ break; ++ } ++ ++ /* ++ * We now have up to two indications of what RAMDAC the adapter uses. ++ * They should be the same. The following test and corresponding ++ * action are under construction. ++ */ ++ if (pATI->DAC != ClockDac) ++ { ++ xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, ++ "Mach64 RAMDAC probe discrepancy detected:\n" ++ " DAC=0x%02X; ClockDac=0x%02X.\n", ++ pATI->DAC, ClockDac); ++ ++ if (pATI->DAC == ATI_DAC_IBMRGB514) ++ { ++ pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; ++ pATI->ClockDescriptor = ATIClockDescriptors[ATI_CLOCK_IBMRGB514]; ++ pATI->ClockNumberToProgramme = 7; ++ } ++ else ++ { ++ pATI->DAC = ClockDac; /* For now */ ++ } ++ } ++ ++ switch (pATI->refclk / 100000) ++ { ++ case 143: ++ pATI->ReferenceNumerator = 157500; ++ pATI->ReferenceDenominator = 11; ++ break; ++ ++ case 286: ++ pATI->ReferenceNumerator = 315000; ++ pATI->ReferenceDenominator = 11; ++ break; ++ ++ default: ++ pATI->ReferenceNumerator = pATI->refclk / 1000; ++ pATI->ReferenceDenominator = 1; ++ break; ++ } ++} ++ ++/* ++ * Pick up multimedia information, which will be at different ++ * displacements depending on table revision. ++ */ ++static void ++ati_bios_mmedia ++( ++ ScrnInfoPtr pScreenInfo, ++ ATIPtr pATI, ++ CARD8 *BIOS, ++ unsigned int VideoTable ++) ++{ ++ pATI->Audio = ATI_AUDIO_NONE; ++ ++ if (VideoTable > 0) ++ { ++ switch (BIOSByte(VideoTable - 0x02U)) ++ { ++ case 0x00U: ++ pATI->Tuner = BIOSByte(VideoTable) & 0x1FU; ++ ++ /* ++ * XXX The VideoTable[1] byte is known to have been ++ * omitted in LTPro and Mobility BIOS'es. Any others? ++ */ ++ switch (pATI->Chip) ++ { ++ case ATI_CHIP_264LTPRO: ++ case ATI_CHIP_MOBILITY: ++ pATI->Decoder = BIOSByte(VideoTable + 0x01U) & 0x07U; ++ pATI->Audio = BIOSByte(VideoTable + 0x02U) & 0x0FU; ++ break; ++ ++ default: ++ pATI->Decoder = BIOSByte(VideoTable + 0x02U) & 0x07U; ++ pATI->Audio = BIOSByte(VideoTable + 0x03U) & 0x0FU; ++ break; ++ } ++ ++ break; ++ ++ case 0x01U: ++ pATI->Tuner = BIOSByte(VideoTable) & 0x1FU; ++ pATI->Audio = BIOSByte(VideoTable + 0x01U) & 0x0FU; ++ pATI->Decoder = BIOSByte(VideoTable + 0x05U) & 0x0FU; ++ break; ++ ++ default: ++ break; ++ } ++ } ++} ++ + /* + * ATIPreInit -- + * +@@ -136,15 +383,7 @@ ATIPreInit + int flags + ) + { +-# define BIOS_SIZE 0x00010000U /* 64kB */ + CARD8 BIOS[BIOS_SIZE]; +-# define BIOSByte(_n) ((CARD8)(BIOS[_n])) +-# define BIOSWord(_n) ((CARD16)(BIOS[_n] | \ +- (BIOS[(_n) + 1] << 8))) +-# define BIOSLong(_n) ((CARD32)(BIOS[_n] | \ +- (BIOS[(_n) + 1] << 8) | \ +- (BIOS[(_n) + 2] << 16) | \ +- (BIOS[(_n) + 3] << 24))) + unsigned int BIOSSize = 0; + unsigned int ROMTable = 0, ClockTable = 0, FrequencyTable = 0; + unsigned int LCDTable = 0, LCDPanelInfo = 0, VideoTable = 0; +@@ -301,7 +540,7 @@ ATIPreInit * If there is an ix86-style BIOS, ensure its initialisation entry point * has been executed, and retrieve DDC and VBE information from it. */ @@ -11769,7 +12326,7 @@ index 8114f51..2420b9f 100644 { xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, "Unable to load int10 module.\n"); -@@ -313,13 +313,13 @@ ATIPreInit +@@ -313,13 +552,13 @@ ATIPreInit } else { @@ -11785,8 +12342,258 @@ index 8114f51..2420b9f 100644 { xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, "Unable to load vbe module.\n"); +@@ -419,7 +658,6 @@ ATIPreInit + + pATI->LCDPanelID = -1; + pATI->nFIFOEntries = 16; /* For now */ +- pATI->Audio = ATI_AUDIO_NONE; + + /* Finish probing the adapter */ + { +@@ -590,17 +828,7 @@ ATIPreInit + pATI->DAC += ATI_DAC_INTERNAL; + } + +- /* +- * For Mach64 adapters, pick up, from the BIOS, the type of programmable +- * clock generator (if any), and various information about it. +- */ + { +- CARD16 ClockDac; +- +- /* Set up non-zero defaults */ +- pATI->ClockDescriptor = ATIClockDescriptors[ATI_CLOCK_FIXED]; +- pATI->ClockNumberToProgramme = -1; +- + ROMTable = BIOSWord(0x48U); + if ((ROMTable < 0x0002U) || + (BIOSWord(ROMTable - 0x02U) < 0x0012U) || +@@ -634,221 +862,9 @@ ATIPreInit + } + } + +- if (ClockTable > 0) +- { +- pATI->ProgrammableClock = BIOSByte(ClockTable); +- pATI->ClockNumberToProgramme = BIOSByte(ClockTable + 0x06U); +- switch (BIOSWord(ClockTable + 0x08U) / 10) +- { +- case 143: +- pATI->ReferenceNumerator = 157500; +- pATI->ReferenceDenominator = 11; +- break; +- +- case 286: +- pATI->ReferenceNumerator = 315000; +- pATI->ReferenceDenominator = 11; +- break; +- +- default: +- pATI->ReferenceNumerator = +- BIOSWord(ClockTable + 0x08U) * 10; +- pATI->ReferenceDenominator = 1; +- break; +- } +- } +- else +- { +- /* +- * Compensate for BIOS absence. Note that the reference +- * frequency has already been set by option processing. +- */ +- if ((pATI->DAC & ~0x0FU) == ATI_DAC_INTERNAL) +- { +- pATI->ProgrammableClock = ATI_CLOCK_INTERNAL; +- } +- else switch (pATI->DAC) +- { +- case ATI_DAC_STG1703: +- pATI->ProgrammableClock = ATI_CLOCK_STG1703; +- break; +- +- case ATI_DAC_CH8398: +- pATI->ProgrammableClock = ATI_CLOCK_CH8398; +- break; +- +- case ATI_DAC_ATT20C408: +- pATI->ProgrammableClock = ATI_CLOCK_ATT20C408; +- break; +- +- case ATI_DAC_IBMRGB514: +- pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; +- break; +- +- default: /* Provisional */ +- pATI->ProgrammableClock = ATI_CLOCK_ICS2595; +- break; +- } +- +- /* This should be safe for all generators except IBM's RGB514 */ +- pATI->ClockNumberToProgramme = 3; +- } +- +- if ((pATI->ProgrammableClock > ATI_CLOCK_FIXED) && +- (pATI->ProgrammableClock < ATI_CLOCK_MAX)) +- { +- /* +- * Graphics PRO TURBO 1600's are unusual in that an ICS2595 is used +- * to generate clocks for VGA modes, and an IBM RGB514 is used for +- * accelerator modes. +- */ +- if ((pATI->ProgrammableClock == ATI_CLOCK_ICS2595) && +- (pATI->DAC == ATI_DAC_IBMRGB514)) +- pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; +- +- pATI->ClockDescriptor = +- ATIClockDescriptors[pATI->ProgrammableClock]; +- } +- +- ClockDac = pATI->DAC; +- switch (pATI->ProgrammableClock) +- { +- case ATI_CLOCK_ICS2595: +- /* +- * Pick up reference divider (43 or 46) appropriate to the chip +- * revision level. +- */ +- if (ClockTable > 0) +- pATI->ClockDescriptor.MinM = +- pATI->ClockDescriptor.MaxM = +- BIOSWord(ClockTable + 0x0AU); +- else if (!xf86NameCmp(pGDev->clockchip, "ATI 18818-0")) +- pATI->ClockDescriptor.MinM = +- pATI->ClockDescriptor.MaxM = 43; +- else if (!xf86NameCmp(pGDev->clockchip, "ATI 18818-1")) +- pATI->ClockDescriptor.MinM = +- pATI->ClockDescriptor.MaxM = 46; +- else +- pATI->ProgrammableClock = ATI_CLOCK_UNKNOWN; +- break; +- +- case ATI_CLOCK_STG1703: +- /* This one's also a RAMDAC */ +- ClockDac = ATI_DAC_STG1703; +- break; +- +- case ATI_CLOCK_CH8398: +- /* This one's also a RAMDAC */ +- ClockDac = ATI_DAC_CH8398; +- break; +- +- case ATI_CLOCK_INTERNAL: +- /* +- * The reference divider has already been programmed by BIOS +- * initialisation. Because, there is only one reference +- * divider for all generated frequencies (including MCLK), it +- * cannot be changed without reprogramming all clocks every +- * time one of them needs a different reference divider. +- * +- * Besides, it's not a good idea to change the reference +- * divider. BIOS initialisation sets it to a value that +- * effectively prevents generating frequencies beyond the +- * graphics controller's tolerance. +- */ +- pATI->ClockDescriptor.MinM = pATI->ClockDescriptor.MaxM = +- ATIMach64GetPLLReg(PLL_REF_DIV); +- +- /* The DAC is also integrated */ +- if ((pATI->DAC & ~0x0FU) != ATI_DAC_INTERNAL) +- ClockDac = ATI_DAC_INTERNAL; +- +- break; +- +- case ATI_CLOCK_ATT20C408: +- /* This one's also a RAMDAC */ +- ClockDac = ATI_DAC_ATT20C408; +- break; +- +- case ATI_CLOCK_IBMRGB514: +- /* This one's also a RAMDAC */ +- ClockDac = ATI_DAC_IBMRGB514; +- pATI->ClockNumberToProgramme = 7; +- break; +- +- default: +- break; +- } +- +- /* +- * We now have up to two indications of what RAMDAC the adapter uses. +- * They should be the same. The following test and corresponding +- * action are under construction. +- */ +- if (pATI->DAC != ClockDac) +- { +- xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, +- "Mach64 RAMDAC probe discrepancy detected:\n" +- " DAC=0x%02X; ClockDac=0x%02X.\n", +- pATI->DAC, ClockDac); +- +- if (pATI->DAC == ATI_DAC_IBMRGB514) +- { +- pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; +- pATI->ClockDescriptor = +- ATIClockDescriptors[ATI_CLOCK_IBMRGB514]; +- pATI->ClockNumberToProgramme = 7; +- } +- else +- { +- pATI->DAC = ClockDac; /* For now */ +- } +- } +- +- /* +- * Pick up multimedia information, which will be at different +- * displacements depending on table revision. +- */ +- if (VideoTable > 0) +- { +- switch (BIOSByte(VideoTable - 0x02U)) +- { +- case 0x00U: +- pATI->Tuner = BIOSByte(VideoTable) & 0x1FU; ++ ati_bios_clock(pScreenInfo, pATI, BIOS, ClockTable, pGDev); + +- /* +- * XXX The VideoTable[1] byte is known to have been +- * omitted in LTPro and Mobility BIOS'es. Any others? +- */ +- switch (pATI->Chip) +- { +- case ATI_CHIP_264LTPRO: +- case ATI_CHIP_MOBILITY: +- pATI->Decoder = +- BIOSByte(VideoTable + 0x01U) & 0x07U; +- pATI->Audio = +- BIOSByte(VideoTable + 0x02U) & 0x0FU; +- break; +- +- default: +- pATI->Decoder = +- BIOSByte(VideoTable + 0x02U) & 0x07U; +- pATI->Audio = +- BIOSByte(VideoTable + 0x03U) & 0x0FU; +- break; +- } +- +- break; +- +- case 0x01U: +- pATI->Tuner = BIOSByte(VideoTable) & 0x1FU; +- pATI->Audio = BIOSByte(VideoTable + 0x01U) & 0x0FU; +- pATI->Decoder = BIOSByte(VideoTable + 0x05U) & 0x0FU; +- break; +- +- default: +- break; +- } +- } ++ ati_bios_mmedia(pScreenInfo, pATI, BIOS, VideoTable); + + /* Determine panel dimensions */ + if (pATI->LCDPanelID >= 0) diff --git a/src/atiprobe.c b/src/atiprobe.c -index 38ce90d..ddfed31 100644 +index 38ce90d..6636a7e 100644 --- a/src/atiprobe.c +++ b/src/atiprobe.c @@ -32,8 +32,8 @@ @@ -11824,7 +12631,18 @@ index 38ce90d..ddfed31 100644 " 0x%04lX was not detected.\n", pATI->CPIO_VGAWonder); pATI->CPIO_VGAWonder = 0; } -@@ -398,7 +398,7 @@ ATIMach64ProbeIO +@@ -191,10 +191,6 @@ ATIMach64Detect + return FALSE; + } + +- /* Determine legacy BIOS address */ +- pATI->BIOSBase = 0x000C0000U + +- (GetBits(inr(SCRATCH_REG1), BIOS_BASE_SEGMENT) << 11); +- + ATIUnmapApertures(-1, pATI); + return TRUE; + } +@@ -398,7 +394,7 @@ ATIMach64ProbeIO if (j == 0x03U) { @@ -11833,7 +12651,7 @@ index 38ce90d..ddfed31 100644 "PCI Mach64 in slot %d:%d:%d cannot be enabled\n" "because it has neither a block, nor a sparse, I/O base.\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo)); -@@ -406,6 +406,13 @@ ATIMach64ProbeIO +@@ -406,6 +402,13 @@ ATIMach64ProbeIO goto SkipSparse; } @@ -11847,7 +12665,7 @@ index 38ce90d..ddfed31 100644 /* FIXME: * Should not probe at sparse I/O bases which have been registered to * other PCI devices. The old ATIProbe() would scan the PCI space and -@@ -418,7 +425,7 @@ ATIMach64ProbeIO +@@ -418,7 +421,7 @@ ATIMach64ProbeIO */ if (!pATI->OptionProbeSparse) { @@ -11856,7 +12674,7 @@ index 38ce90d..ddfed31 100644 "PCI Mach64 in slot %d:%d:%d will not be probed\n" "set option \"probe_sparse\" to force sparse I/O probing.\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo)); -@@ -426,27 +433,20 @@ ATIMach64ProbeIO +@@ -426,27 +429,20 @@ ATIMach64ProbeIO goto SkipSparse; } @@ -11886,7 +12704,7 @@ index 38ce90d..ddfed31 100644 "Shared PCI Mach64 in slot %d:%d:%d with sparse PIO base" " 0x%04lX detected.\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo), -@@ -471,7 +471,7 @@ SkipSparse: +@@ -471,7 +467,7 @@ SkipSparse: if (ATIMach64Probe(pATI, pVideo, pATI->Chip)) { ProbeSuccess = TRUE; @@ -11895,7 +12713,7 @@ index 38ce90d..ddfed31 100644 "Shared PCI Mach64 in slot %d:%d:%d with Block 0 base" " 0x%08lX detected.\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo), -@@ -479,7 +479,7 @@ SkipSparse: +@@ -479,7 +475,7 @@ SkipSparse: } else { @@ -11904,7 +12722,7 @@ index 38ce90d..ddfed31 100644 "PCI Mach64 in slot %d:%d:%d could not be detected!\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo)); } -@@ -497,7 +497,7 @@ SkipSparse: +@@ -497,7 +493,7 @@ SkipSparse: if (ATIMach64Probe(pATI, pVideo, pATI->Chip)) { ProbeSuccess = TRUE; @@ -11913,7 +12731,7 @@ index 38ce90d..ddfed31 100644 "Shared PCI/AGP Mach64 in slot %d:%d:%d detected.\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo)); -@@ -511,7 +511,7 @@ SkipSparse: +@@ -511,7 +507,7 @@ SkipSparse: } else { @@ -11922,6 +12740,26 @@ index 38ce90d..ddfed31 100644 "PCI/AGP Mach64 in slot %d:%d:%d could not be detected!\n", PCI_DEV_BUS(pVideo), PCI_DEV_DEV(pVideo), PCI_DEV_FUNC(pVideo)); } +diff --git a/src/atistruct.h b/src/atistruct.h +index d574947..b9f4d08 100644 +--- a/src/atistruct.h ++++ b/src/atistruct.h +@@ -283,7 +283,6 @@ typedef struct _ATIRec + /* + * BIOS-related definitions. + */ +- unsigned long BIOSBase; + CARD8 I2CType, Tuner, Decoder, Audio; + + /* +@@ -353,6 +352,7 @@ typedef struct _ATIRec + /* + * Clock-related definitions. + */ ++ int refclk; + int ClockNumberToProgramme, ReferenceNumerator, ReferenceDenominator; + int ProgrammableClock, maxClock; + ClockRec ClockDescriptor; diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c new file mode 100644 index 0000000..bc2df18 @@ -16674,7 +17512,7 @@ index 0000000..7ade772 + return found; +} diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index f201cc4..f235a5c 100644 +index f201cc4..5a2191a 100644 --- a/src/pcidb/ati_pciids.csv +++ b/src/pcidb/ati_pciids.csv @@ -4,8 +4,8 @@ @@ -16715,7 +17553,7 @@ index f201cc4..f235a5c 100644 "0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" "0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" "0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" -@@ -216,5 +217,137 @@ +@@ -216,5 +217,143 @@ "0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" "0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)" "0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" @@ -16843,6 +17681,12 @@ index f201cc4..f235a5c 100644 +"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400" +"0x94CB","RV610_94CB","RV610",1,,,,,"ATI ATI RADEON E2400" +"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610" ++"0x9500","RV670_9500","RV670",,,,,,"ATI RV670" ++"0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870" ++"0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850" ++"0x9507","RV670_9507","RV670",,,,,,"ATI RV670" ++"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" ++"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" +"0x9580","RV630_9580","RV630",,,,,,"ATI RV630" +"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" +"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" @@ -17573,7 +18417,7 @@ index 0f715aa..8e83323 100644 break; } diff --git a/src/radeon.h b/src/radeon.h -index 801d616..ec952b5 100644 +index 801d616..7950ac8 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -166,7 +166,8 @@ typedef enum { @@ -17783,7 +18627,7 @@ index 801d616..ec952b5 100644 CARD32 best_vco; } RADEONPLLRec, *RADEONPLLPtr; -@@ -421,6 +259,18 @@ typedef enum { +@@ -421,6 +259,19 @@ typedef enum { CHIP_FAMILY_R420, /* R420/R423/M18 */ CHIP_FAMILY_RV410, /* RV410, M26 */ CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ @@ -17798,11 +18642,12 @@ index 801d616..ec952b5 100644 + CHIP_FAMILY_R630, + CHIP_FAMILY_RV610, + CHIP_FAMILY_RV630, ++ CHIP_FAMILY_RV670, + CHIP_FAMILY_RS740, CHIP_FAMILY_LAST } RADEONChipFamily; -@@ -441,6 +291,8 @@ typedef enum { +@@ -441,6 +292,8 @@ typedef enum { (info->ChipFamily == CHIP_FAMILY_RV410) || \ (info->ChipFamily == CHIP_FAMILY_RS400)) @@ -17811,7 +18656,7 @@ index 801d616..ec952b5 100644 /* * Errata workarounds */ -@@ -475,6 +327,8 @@ typedef enum { +@@ -475,6 +328,8 @@ typedef enum { CARD_PCIE } RADEONCardType; @@ -17820,7 +18665,7 @@ index 801d616..ec952b5 100644 typedef struct { CARD32 pci_device_id; RADEONChipFamily chip_family; -@@ -500,6 +354,7 @@ typedef struct { +@@ -500,6 +355,7 @@ typedef struct { CARD32 gartLocation; CARD32 mc_fb_location; CARD32 mc_agp_location; @@ -17828,7 +18673,7 @@ index 801d616..ec952b5 100644 void *MMIO; /* Map of MMIO region */ void *FB; /* Map of frame buffer */ -@@ -542,8 +397,8 @@ typedef struct { +@@ -542,8 +398,8 @@ typedef struct { Bool IsDDR; int DispPriority; @@ -17839,7 +18684,7 @@ index 801d616..ec952b5 100644 Bool (*CloseScreen)(int, ScreenPtr); void (*BlockHandler)(int, pointer, pointer, pointer); -@@ -815,14 +670,12 @@ typedef struct { +@@ -815,14 +671,12 @@ typedef struct { OptionInfoPtr Options; Bool useEXA; @@ -17854,7 +18699,7 @@ index 801d616..ec952b5 100644 /* X itself has the 3D context */ Bool XInited3D; -@@ -856,6 +709,10 @@ typedef struct { +@@ -856,6 +710,10 @@ typedef struct { #endif RADEONExtTMDSChip ext_tmds_chip; @@ -17865,7 +18710,7 @@ index 801d616..ec952b5 100644 /* output enable masks for outputs shared across connectors */ int output_crt1; int output_crt2; -@@ -867,6 +724,15 @@ typedef struct { +@@ -867,6 +725,15 @@ typedef struct { Rotation rotation; void (*PointerMoved)(int, int, int); CreateScreenResourcesProcPtr CreateScreenResources; @@ -17881,7 +18726,7 @@ index 801d616..ec952b5 100644 } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -894,6 +760,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn); +@@ -894,6 +761,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn); extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); @@ -17891,7 +18736,7 @@ index 801d616..ec952b5 100644 extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); -@@ -942,6 +811,7 @@ extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn); +@@ -942,6 +812,7 @@ extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn); extern Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output); extern Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output); extern Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output); @@ -17899,7 +18744,7 @@ index 801d616..ec952b5 100644 extern Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output); extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, -@@ -974,32 +844,22 @@ extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, +@@ -974,32 +845,22 @@ extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info); extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); extern Bool RADEONI2cInit(ScrnInfoPtr pScrn); @@ -17936,13 +18781,15 @@ index 801d616..ec952b5 100644 extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch); -@@ -1010,20 +870,23 @@ RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output); +@@ -1010,20 +871,25 @@ RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output); extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); -void +extern RADEONI2CBusRec +legacy_setup_i2c_bus(int ddc_line); ++extern RADEONI2CBusRec ++atom_setup_i2c_bus(int ddc_line); + +extern void radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y); @@ -17968,7 +18815,7 @@ index 801d616..ec952b5 100644 extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, xf86OutputPtr output); -@@ -1037,8 +900,10 @@ extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -1037,8 +903,10 @@ extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary); extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); @@ -18414,10 +19261,10 @@ index 212131f..e3b37c1 100644 } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c new file mode 100644 -index 0000000..e8f9e91 +index 0000000..913fafb --- /dev/null +++ b/src/radeon_atombios.c -@@ -0,0 +1,2833 @@ +@@ -0,0 +1,2842 @@ +/* + * Copyright 2007 Egbert Eich + * Copyright 2007 Luc Verhaegen @@ -19824,7 +20671,7 @@ index 0000000..e8f9e91 + +static void +rhdAtomParseI2CRecord(atomBiosHandlePtr handle, -+ ATOM_I2C_RECORD *Record, int *line) ++ ATOM_I2C_RECORD *Record, int *ddc_line) +{ + ErrorF(" %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n", + __func__, @@ -19834,13 +20681,22 @@ index 0000000..e8f9e91 + Record->ucI2CAddr); + + if (!*(unsigned char *)&(Record->sucI2cId)) -+ *line = 0; ++ *ddc_line = 0; + else { -+ + if (Record->ucI2CAddr != 0) + return; -+ *line = Record->sucI2cId.bfI2C_LineMux; -+ return; ++ ++ if (Record->sucI2cId.bfHW_Capable) { ++ switch(Record->sucI2cId.bfI2C_LineMux) { ++ case 0: *ddc_line = 0x7e40; break; ++ case 1: *ddc_line = 0x7e50; break; ++ case 2: *ddc_line = 0x7e30; break; ++ default: break; ++ } ++ return; ++ } else { ++ /* add GPIO pin parsing */ ++ } + } +} + @@ -19890,7 +20746,7 @@ index 0000000..e8f9e91 + unsigned short size; + atomDataTablesPtr atomDataPtr; + ATOM_CONNECTOR_OBJECT_TABLE *con_obj; -+ int i, j, line = 0; ++ int i, j, ddc_line; + + atomDataPtr = info->atomBIOS->atomDataPtr; + if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size)) @@ -19978,8 +20834,8 @@ index 0000000..e8f9e91 + case ATOM_I2C_RECORD_TYPE: + rhdAtomParseI2CRecord(info->atomBIOS, + (ATOM_I2C_RECORD *)Record, -+ &line); -+ info->BiosConnector[i].ddc_i2c = RADEONLookupGPIOLineForDDC(pScrn, line); ++ &ddc_line); ++ info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); + break; + case ATOM_HPD_INT_RECORD_TYPE: + break; @@ -22218,7 +23074,7 @@ index 7d4d12a..8e6bd8d 100644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown gpio reg: %d\n", gpio_reg); diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index a12b225..775df06 100644 +index a12b225..420f5d8 100644 --- a/src/radeon_chipinfo_gen.h +++ b/src/radeon_chipinfo_gen.h @@ -5,8 +5,8 @@ RADEONCardInfo RADEONCards[] = { @@ -22257,7 +23113,7 @@ index a12b225..775df06 100644 { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, -@@ -135,6 +136,138 @@ RADEONCardInfo RADEONCards[] = { +@@ -135,6 +136,144 @@ RADEONCardInfo RADEONCards[] = { { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, @@ -22385,6 +23241,12 @@ index a12b225..775df06 100644 + { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, + { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, + { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, + { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, + { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, + { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, @@ -22399,7 +23261,7 @@ index a12b225..775df06 100644 + { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, }; diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index 0a7a9c1..0c3fc96 100644 +index 0a7a9c1..e6890be 100644 --- a/src/radeon_chipset_gen.h +++ b/src/radeon_chipset_gen.h @@ -115,6 +115,7 @@ static SymTabRec RADEONChipsets[] = { @@ -22410,7 +23272,7 @@ index 0a7a9c1..0c3fc96 100644 { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, -@@ -135,7 +136,139 @@ static SymTabRec RADEONChipsets[] = { +@@ -135,7 +136,145 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, @@ -22536,6 +23398,12 @@ index 0a7a9c1..0c3fc96 100644 + { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, + { PCI_CHIP_RV610_94CB, "ATI ATI RADEON E2400" }, + { PCI_CHIP_RV610_94CC, "ATI RV610" }, ++ { PCI_CHIP_RV670_9500, "ATI RV670" }, ++ { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" }, ++ { PCI_CHIP_RV670_9505, "ATI Radeon HD3850" }, ++ { PCI_CHIP_RV670_9507, "ATI RV670" }, ++ { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, ++ { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, + { PCI_CHIP_RV630_9580, "ATI RV630" }, + { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, + { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, @@ -22551,10 +23419,10 @@ index 0a7a9c1..0c3fc96 100644 { -1, NULL } }; diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index a1802f8..53bbce9 100644 +index a1802f8..8c4b598 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c -@@ -57,8 +57,140 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -57,8 +57,127 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; @@ -22600,8 +23468,10 @@ index a1802f8..53bbce9 100644 + OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456); + OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300); + OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x6a014001); ++ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001); ++ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01); + OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688); ++ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688); + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400); + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); @@ -22616,7 +23486,7 @@ index a1802f8..53bbce9 100644 + + OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0); + OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1); -+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, 0x2); ++ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (0x2 << 3) | 0x2); + + OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); + OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); @@ -22648,21 +23518,6 @@ index a1802f8..53bbce9 100644 + OUT_ACCEL_REG(R300_RS_INST_0, 0x8); + FINISH_ACCEL(); + -+ BEGIN_ACCEL(12); -+ OUT_ACCEL_REG(R300_US_CONFIG, 0x8); -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0); -+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000); -+ OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -+ FINISH_ACCEL(); -+ + BEGIN_ACCEL(3); + OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0x0); + OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0x0); @@ -28946,7 +29801,7 @@ index 2b7f0e8..20b96a5 100644 (info->ChipFamily == CHIP_FAMILY_RV280) || (info->ChipFamily == CHIP_FAMILY_RS300) || diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index eae69c4..c642aff 100644 +index eae69c4..6003587 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -121,6 +121,17 @@ static struct formatinfo R200TexFormats[] = { @@ -28999,7 +29854,7 @@ index eae69c4..c642aff 100644 static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) { CARD32 sblend, dblend; -@@ -706,9 +742,304 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -706,9 +742,320 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, return TRUE; } @@ -29055,7 +29910,8 @@ index eae69c4..c642aff 100644 + RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset)); + if ((txpitch & 0x1f) != 0) + RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -+ + +-#define VTX_DWORD_COUNT 6 + pixel_shift = pPix->drawable.bitsPerPixel >> 4; + txpitch >>= pixel_shift; + txpitch -= 1; @@ -29197,7 +30053,7 @@ index eae69c4..c642aff 100644 + RINFO_FROM_SCREEN(pDst->drawable.pScreen); + CARD32 dst_format, dst_offset, dst_pitch; + CARD32 txenable, colorpitch; -+ /*CARD32 blendcntl, cblend, ablend;*/ ++ CARD32 blendcntl; + int pixel_shift; + ACCEL_PREAMBLE(); + @@ -29234,10 +30090,25 @@ index eae69c4..c642aff 100644 + } else { + is_transform[1] = FALSE; + } - --#define VTX_DWORD_COUNT 6 ++ + RADEON_SWITCH_TO_3D(); + ++ /* setup pixel shader */ ++ BEGIN_ACCEL(12); ++ OUT_ACCEL_REG(R300_US_CONFIG, 0x8); ++ OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0); ++ OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000); ++ OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); ++ FINISH_ACCEL(); ++ + BEGIN_ACCEL(6); + OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); + OUT_ACCEL_REG(R300_TX_ENABLE, txenable); @@ -29245,7 +30116,8 @@ index eae69c4..c642aff 100644 + OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); + OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); + -+ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, 0x0); ++ blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); ++ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl); + OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0x0); + +#if 0 @@ -29300,46 +30172,21 @@ index eae69c4..c642aff 100644 +} + +#define VTX_COUNT 6 -+#define R300_VTX_COUNT 4 + +#ifdef ACCEL_CP #define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ -@@ -720,9 +1051,15 @@ do { \ - OUT_RING_F(_maskY); \ - } while (0) +@@ -722,8 +1069,6 @@ do { \ --#else /* ACCEL_CP */ -+#define VTX_OUT4(_dstX, _dstY, _srcX, _srcY) \ -+do { \ -+ OUT_RING_F(_dstX); \ -+ OUT_RING_F(_dstY); \ -+ OUT_RING_F(_srcX); \ -+ OUT_RING_F(_srcY); \ -+} while (0) + #else /* ACCEL_CP */ -#define VTX_REG_COUNT 6 -+#else /* ACCEL_CP */ - +- #define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ -@@ -734,6 +1071,14 @@ do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ - } while (0) - -+#define VTX_OUT4(_dstX, _dstY, _srcX, _srcY) \ -+do { \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ -+} while (0) -+ - #endif /* !ACCEL_CP */ - - #ifdef ONLY_ONCE -@@ -759,6 +1104,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ +@@ -759,14 +1104,15 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, { RINFO_FROM_SCREEN(pDst->drawable.pScreen); int srcXend, srcYend, maskXend, maskYend; @@ -29347,12 +30194,13 @@ index eae69c4..c642aff 100644 xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; ACCEL_PREAMBLE(); -@@ -766,7 +1112,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + ENTER_DRAW(0); - /*ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", +- /*ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", - srcX, srcY, maskX, maskY,dstX, dstY, w, h);*/ -+ srcX, srcY, maskX, maskY,dstX, dstY, w, h);*/ ++ /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", ++ srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ srcXend = srcX + w; srcYend = srcY + h; @@ -29360,7 +30208,7 @@ index eae69c4..c642aff 100644 transformPoint(transform[1], &maskBottomRight); } -+ vtx_count = (info->ChipFamily >= CHIP_FAMILY_R300) ? R300_VTX_COUNT : VTX_COUNT; ++ vtx_count = VTX_COUNT; + + if (IS_R300_VARIANT) { + BEGIN_ACCEL(1); @@ -29406,30 +30254,7 @@ index eae69c4..c642aff 100644 if (info->ChipFamily < CHIP_FAMILY_R200) { OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | RADEON_VF_PRIM_WALK_DATA | -@@ -846,6 +1208,22 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - VTX_OUT(dstX, dstY + h, srcX, srcYend, maskX, maskYend); - VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend); - VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY); -+ } else if (IS_R300_VARIANT) { -+ VTX_OUT4((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], -+ xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ -+ VTX_OUT4((float)dstX, (float)(dstY + h), -+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], -+ xFixedToFloat(srcBottomLeft.y) / info->texH[0]); -+ -+ VTX_OUT4((float)(dstX + w), (float)(dstY + h), -+ xFixedToFloat(srcBottomRight.x) / info->texW[0], -+ xFixedToFloat(srcBottomRight.y) / info->texH[0]); -+ -+ VTX_OUT4((float)(dstX + w), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->texW[0], -+ xFixedToFloat(srcTopRight.y) / info->texH[0]); - } else { - VTX_OUT((float)dstX, (float)dstY, - xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], -@@ -861,6 +1239,11 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -861,6 +1223,11 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); } @@ -29441,7 +30266,7 @@ index eae69c4..c642aff 100644 #ifdef ACCEL_CP ADVANCE_RING(); #else -@@ -870,6 +1253,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -870,6 +1237,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, LEAVE_DRAW(0); } #undef VTX_OUT @@ -29790,7 +30615,7 @@ index 3c4badd..2c72395 100644 } } diff --git a/src/radeon_output.c b/src/radeon_output.c -index 64c0438..5ef864e 100644 +index 64c0438..248f94a 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -46,19 +46,22 @@ @@ -29854,9 +30679,8 @@ index 64c0438..5ef864e 100644 "Primary", "TVDAC/ExtDAC", - "None" -+ "ExtDac" - }; - +-}; +- -const char *ConnectorTypeName[8] = { - "None", - "Proprietary/LVDS", @@ -29866,8 +30690,9 @@ index 64c0438..5ef864e 100644 - "CTV", - "STV", - "Unsupported" --}; -- ++ "ExtDac" + }; + -const char *ConnectorTypeNameATOM[10] = { +const char *ConnectorTypeName[17] = { "None", @@ -29960,10 +30785,6 @@ index 64c0438..5ef864e 100644 - if (xf86I2CDevInit(dvo)) { - return dvo; - } -- -- xfree(dvo); -- return NULL; --} + 0x00000000, /* unknown */ + 0x00000000, /* legacy */ + 0x00000000, /* r100 */ @@ -29984,15 +30805,16 @@ index 64c0438..5ef864e 100644 + 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */ +}; +- xfree(dvo); +- return NULL; +-} + -void -RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - -- if (!radeon_output->DVOChip) -- return; +static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output); +static void RADEONUpdatePanelSize(xf86OutputPtr output); +static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output); @@ -30013,6 +30835,9 @@ index 64c0438..5ef864e 100644 +extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); +extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); +- if (!radeon_output->DVOChip) +- return; +- - OUTREG(radeon_output->dvo_i2c_reg, INREG(radeon_output->dvo_i2c_reg) & - (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); - @@ -30053,7 +30878,7 @@ index 64c0438..5ef864e 100644 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONOutputPrivatePtr radeon_output; xf86OutputPtr output; -@@ -260,33 +199,67 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) +@@ -260,18 +199,50 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) output = xf86_config->output[o]; radeon_output = output->driver_private; @@ -30072,11 +30897,11 @@ index 64c0438..5ef864e 100644 + DACTypeName[radeon_output->DACType], + TMDSTypeName[radeon_output->TMDSType], + (unsigned int)radeon_output->ddc_i2c.mask_clk_reg); - } - - } - - static RADEONMonitorType ++ } ++ ++} ++ ++static RADEONMonitorType +avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); @@ -30088,7 +30913,7 @@ index 64c0438..5ef864e 100644 + AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE); + MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); + AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE); -+ } + } + if (MonInfo) { + if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) + xf86OutputSetEDID(output, MonInfo); @@ -30106,12 +30931,12 @@ index 64c0438..5ef864e 100644 + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); -+ + + return MonType; -+} -+ -+static RADEONMonitorType - RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) + } + + static RADEONMonitorType +@@ -279,14 +250,16 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -31010,11 +31835,11 @@ index 64c0438..5ef864e 100644 - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); -- -- if (radeon_crtc->crtc_id == 0) -- RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); + RADEONInfoPtr info = RADEONPTR(output->scrn); +- if (radeon_crtc->crtc_id == 0) +- RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); +- - switch(radeon_output->MonType) { - case MT_LCD: - ErrorF("restore LVDS\n"); @@ -31624,9 +32449,7 @@ index 64c0438..5ef864e 100644 - if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I_ATOM) || - (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I)) { - monitor_type_atom = MAKE_ATOM("dvi_monitor_type"); -+ if (radeon_output->type == OUTPUT_DVI_I) { -+ monitor_type_atom = MAKE_ATOM("dvi_monitor_type"); - +- - err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom, - FALSE, FALSE, FALSE, 0, NULL); - if (err != 0) { @@ -31648,7 +32471,9 @@ index 64c0438..5ef864e 100644 - if (radeon_output->type == OUTPUT_STV || - radeon_output->type == OUTPUT_CTV) { - tv_hsize_atom = MAKE_ATOM("tv_horizontal_size"); -- ++ if (radeon_output->type == OUTPUT_DVI_I) { ++ monitor_type_atom = MAKE_ATOM("dvi_monitor_type"); + - range[0] = -MAX_H_SIZE; - range[1] = MAX_H_SIZE; - err = RRConfigureOutputProperty(output->randr_output, tv_hsize_atom, @@ -32067,14 +32892,14 @@ index 64c0438..5ef864e 100644 + val = INREG(pRADEONI2CBus->put_clk_reg) & (CARD32)~(pRADEONI2CBus->put_clk_mask); + val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask); + OUTREG(pRADEONI2CBus->put_clk_reg, val); -+ /* read back to improve reliability on some cards. */ + /* read back to improve reliability on some cards. */ +- val = INREG(b->DriverPrivate.uval); + val = INREG(pRADEONI2CBus->put_clk_reg); + + val = INREG(pRADEONI2CBus->put_data_reg) & (CARD32)~(pRADEONI2CBus->put_data_mask); + val |= (data ? 0:pRADEONI2CBus->put_data_mask); + OUTREG(pRADEONI2CBus->put_data_reg, val); - /* read back to improve reliability on some cards. */ -- val = INREG(b->DriverPrivate.uval); ++ /* read back to improve reliability on some cards. */ + val = INREG(pRADEONI2CBus->put_data_reg); + } @@ -32090,7 +32915,7 @@ index 64c0438..5ef864e 100644 pI2CBus = xf86CreateI2CBusRec(); if (!pI2CBus) return FALSE; -@@ -2373,14 +1349,44 @@ RADEONI2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name) +@@ -2373,14 +1349,81 @@ RADEONI2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name) pI2CBus->I2CPutBits = RADEONI2CPutBits; pI2CBus->I2CGetBits = RADEONI2CGetBits; pI2CBus->AcknTimeout = 5; @@ -32129,7 +32954,44 @@ index 64c0438..5ef864e 100644 + i2c.put_data_reg = ddc_line; + i2c.get_clk_reg = ddc_line; + i2c.get_data_reg = ddc_line; -+ i2c.valid = TRUE; ++ if (ddc_line) ++ i2c.valid = TRUE; ++ else ++ i2c.valid = FALSE; ++ ++ return i2c; ++} ++ ++RADEONI2CBusRec ++atom_setup_i2c_bus(int ddc_line) ++{ ++ RADEONI2CBusRec i2c; ++ ++ if (ddc_line == AVIVO_GPIO_0) { ++ i2c.put_clk_mask = (1 << 19); ++ i2c.put_data_mask = (1 << 18); ++ i2c.get_clk_mask = (1 << 19); ++ i2c.get_data_mask = (1 << 18); ++ i2c.mask_clk_mask = (1 << 19); ++ i2c.mask_data_mask = (1 << 18); ++ } else { ++ i2c.put_clk_mask = (1 << 0); ++ i2c.put_data_mask = (1 << 8); ++ i2c.get_clk_mask = (1 << 0); ++ i2c.get_data_mask = (1 << 8); ++ i2c.mask_clk_mask = (1 << 0); ++ i2c.mask_data_mask = (1 << 8); ++ } ++ i2c.mask_clk_reg = ddc_line; ++ i2c.mask_data_reg = ddc_line; ++ i2c.put_clk_reg = ddc_line + 0x8; ++ i2c.put_data_reg = ddc_line + 0x8; ++ i2c.get_clk_reg = ddc_line + 0xc; ++ i2c.get_data_reg = ddc_line + 0xc; ++ if (ddc_line) ++ i2c.valid = TRUE; ++ else ++ i2c.valid = FALSE; + + return i2c; +} @@ -32137,7 +32999,7 @@ index 64c0438..5ef864e 100644 static void RADEONGetPanelInfoFromReg (xf86OutputPtr output) { -@@ -2643,71 +1649,99 @@ RADEONGetTMDSInfo(xf86OutputPtr output) +@@ -2643,71 +1686,99 @@ RADEONGetTMDSInfo(xf86OutputPtr output) static void RADEONGetTVInfo(xf86OutputPtr output) { @@ -32265,7 +33127,7 @@ index 64c0438..5ef864e 100644 radeon_output->DVOChip = RADEONDVODeviceInit(pDVOBus, radeon_output->dvo_i2c_slave_addr); -@@ -2718,8 +1752,7 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2718,8 +1789,7 @@ void RADEONInitConnector(xf86OutputPtr output) RADEONGetTMDSInfo(output); } @@ -32275,7 +33137,7 @@ index 64c0438..5ef864e 100644 RADEONGetTVInfo(output); RADEONGetTVDacAdjInfo(output); } -@@ -2729,6 +1762,9 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2729,6 +1799,9 @@ void RADEONInitConnector(xf86OutputPtr output) RADEONGetTVDacAdjInfo(output); } @@ -32285,7 +33147,7 @@ index 64c0438..5ef864e 100644 } #if defined(__powerpc__) -@@ -2739,32 +1775,32 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2739,32 +1812,32 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) switch (info->MacModel) { case RADEON_MAC_IBOOK: @@ -32326,7 +33188,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_EXT; info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; -@@ -2773,17 +1809,18 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2773,17 +1846,18 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].ConnectorType = CONNECTOR_STV; info->BiosConnector[2].DACType = DAC_TVDAC; info->BiosConnector[2].TMDSType = TMDS_NONE; @@ -32349,7 +33211,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_INT; info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; -@@ -2792,17 +1829,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2792,17 +1866,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].ConnectorType = CONNECTOR_STV; info->BiosConnector[2].DACType = DAC_TVDAC; info->BiosConnector[2].TMDSType = TMDS_NONE; @@ -32371,7 +33233,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_INT; info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; -@@ -2811,11 +1848,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2811,11 +1885,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].ConnectorType = CONNECTOR_STV; info->BiosConnector[2].DACType = DAC_TVDAC; info->BiosConnector[2].TMDSType = TMDS_NONE; @@ -32385,7 +33247,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[0].DACType = DAC_TVDAC; info->BiosConnector[0].TMDSType = TMDS_EXT; info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; -@@ -2824,11 +1861,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2824,11 +1898,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[1].ConnectorType = CONNECTOR_STV; info->BiosConnector[1].DACType = DAC_TVDAC; info->BiosConnector[1].TMDSType = TMDS_NONE; @@ -32399,7 +33261,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[0].DACType = DAC_TVDAC; info->BiosConnector[0].TMDSType = TMDS_INT; info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; -@@ -2837,26 +1874,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2837,26 +1911,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[1].ConnectorType = CONNECTOR_STV; info->BiosConnector[1].DACType = DAC_TVDAC; info->BiosConnector[1].TMDSType = TMDS_NONE; @@ -32431,7 +33293,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[2].valid = TRUE; return TRUE; default: -@@ -2873,108 +1910,146 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) +@@ -2873,108 +1947,146 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); if (!pRADEONEnt->HasCRTC2) { @@ -32452,15 +33314,8 @@ index 64c0438..5ef864e 100644 - info->BiosConnector[0].DACType = DAC_UNKNOWN; - info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; - info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; -+ if (IS_AVIVO_VARIANT) { -+ if (info->IsMobility) { -+ info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(0x7e60); -+ info->BiosConnector[0].DACType = DAC_NONE; -+ info->BiosConnector[0].TMDSType = TMDS_NONE; -+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; -+ info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - info->BiosConnector[0].valid = TRUE; - +- info->BiosConnector[0].valid = TRUE; +- - /* IGP only has TVDAC */ - if (info->ChipFamily == CHIP_FAMILY_RS400) - info->BiosConnector[1].DDCType = DDC_CRT2; @@ -32479,10 +33334,17 @@ index 64c0438..5ef864e 100644 - info->BiosConnector[0].DACType = DAC_UNKNOWN; - info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; - info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; -- info->BiosConnector[0].valid = TRUE; -- ++ if (IS_AVIVO_VARIANT) { ++ if (info->IsMobility) { ++ info->BiosConnector[0].ddc_i2c = atom_setup_i2c_bus(0x7e60); ++ info->BiosConnector[0].DACType = DAC_NONE; ++ info->BiosConnector[0].TMDSType = TMDS_NONE; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; ++ info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; + info->BiosConnector[0].valid = TRUE; + - info->BiosConnector[1].DDCType = DDC_VGA; -+ info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(0x7e40); ++ info->BiosConnector[1].ddc_i2c = atom_setup_i2c_bus(0x7e40); info->BiosConnector[1].DACType = DAC_PRIMARY; - info->BiosConnector[1].TMDSType = TMDS_UNKNOWN; - info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; @@ -32513,7 +33375,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[1].valid = TRUE; } else { - info->BiosConnector[0].DDCType = DDC_DVI; -+ info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(0x7e50); ++ info->BiosConnector[0].ddc_i2c = atom_setup_i2c_bus(0x7e50); info->BiosConnector[0].DACType = DAC_TVDAC; info->BiosConnector[0].TMDSType = TMDS_INT; info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; @@ -32528,7 +33390,7 @@ index 64c0438..5ef864e 100644 - info->BiosConnector[1].valid = TRUE; -#else - info->BiosConnector[1].DDCType = DDC_VGA; -+ info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(0x7e40); ++ info->BiosConnector[1].ddc_i2c = atom_setup_i2c_bus(0x7e40); info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_NONE; - info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; @@ -32653,7 +33515,7 @@ index 64c0438..5ef864e 100644 } #if defined(__powerpc__) -@@ -3104,6 +2179,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3104,6 +2216,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) int i = 0; int num_vga = 0; int num_dvi = 0; @@ -32661,7 +33523,7 @@ index 64c0438..5ef864e 100644 /* We first get the information about all connectors from BIOS. * This is how the card is phyiscally wired up. -@@ -3111,9 +2187,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3111,9 +2224,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) */ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { info->BiosConnector[i].valid = FALSE; @@ -32674,7 +33536,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[i].ConnectorType = CONNECTOR_NONE; } -@@ -3162,15 +2238,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3162,15 +2275,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) RADEONSetupGenericConnectors(pScrn); } @@ -32692,7 +33554,7 @@ index 64c0438..5ef864e 100644 info->BiosConnector[i].DACType = DAC_PRIMARY; } } -@@ -3179,23 +2249,28 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3179,23 +2286,28 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE); if (optstr) { @@ -32724,7 +33586,7 @@ index 64c0438..5ef864e 100644 } info->tvdac_use_count = 0; -@@ -3204,21 +2279,15 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3204,21 +2316,15 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) if (info->BiosConnector[i].DACType == DAC_TVDAC) info->tvdac_use_count++; @@ -32755,7 +33617,7 @@ index 64c0438..5ef864e 100644 } } } -@@ -3243,67 +2312,47 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3243,67 +2349,47 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) } radeon_output->MonType = MT_UNKNOWN; radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType; @@ -32862,7 +33724,7 @@ index 64c0438..5ef864e 100644 if (!output) { return FALSE; diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index 7a36242..9d73b96 100644 +index 7a36242..ab6b62a 100644 --- a/src/radeon_pci_chipset_gen.h +++ b/src/radeon_pci_chipset_gen.h @@ -115,6 +115,7 @@ PciChipsets RADEONPciChipsets[] = { @@ -32873,7 +33735,7 @@ index 7a36242..9d73b96 100644 { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, -@@ -135,7 +136,139 @@ PciChipsets RADEONPciChipsets[] = { +@@ -135,7 +136,145 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, @@ -32999,6 +33861,12 @@ index 7a36242..9d73b96 100644 + { PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA }, + { PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA }, + { PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, + { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, + { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, + { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, @@ -33609,7 +34477,7 @@ index 7f8ce45..df87dab 100644 extern Bool RADEONScreenInit(int, ScreenPtr, int, char **); extern Bool RADEONSwitchMode(int, DisplayModePtr, int); diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 6e4e383..eec8784 100644 +index 6e4e383..8d45d7b 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -337,6 +337,8 @@ @@ -33649,7 +34517,7 @@ index 6e4e383..eec8784 100644 # define RADEON_TV_N0LO_SHIFT 8 # define RADEON_TV_N0HI_MASK 0x3 # define RADEON_TV_N0HI_SHIFT 21 -@@ -3271,4 +3275,680 @@ +@@ -3271,4 +3275,682 @@ #define RADEON_RS480_UNK_e38 0xe38 #define RADEON_RS480_UNK_e3c 0xe3c @@ -34145,7 +35013,9 @@ index 6e4e383..eec8784 100644 +#define R300_VAP_VTE_CNTL 0x20B0 +#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC +#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 ++#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 +#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 ++#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 +#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 +#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 +#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 diff --git a/radeon.xinf b/radeon.xinf index 69ec765..3823a6d 100644 --- a/radeon.xinf +++ b/radeon.xinf @@ -447,6 +447,12 @@ alias pcivideo:v00001002d000094C8sv*sd*bc*sc*i* radeon_tp # alias pcivideo:v00001002d000094C9sv*sd*bc*sc*i* radeon_tp # alias pcivideo:v00001002d000094CBsv*sd*bc*sc*i* radeon_tp # alias pcivideo:v00001002d000094CCsv*sd*bc*sc*i* radeon_tp # +alias pcivideo:v00001002d00009500sv*sd*bc*sc*i* radeon_tp # +alias pcivideo:v00001002d00009501sv*sd*bc*sc*i* radeon_tp # +alias pcivideo:v00001002d00009505sv*sd*bc*sc*i* radeon_tp # +alias pcivideo:v00001002d00009507sv*sd*bc*sc*i* radeon_tp # +alias pcivideo:v00001002d0000950Fsv*sd*bc*sc*i* radeon_tp # +alias pcivideo:v00001002d00009511sv*sd*bc*sc*i* radeon_tp # alias pcivideo:v00001002d00009580sv*sd*bc*sc*i* radeon_tp # alias pcivideo:v00001002d00009581sv*sd*bc*sc*i* radeon_tp # alias pcivideo:v00001002d00009583sv*sd*bc*sc*i* radeon_tp # diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index f6eb4c5..b251b35 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.7.197 -Release: 1%{?dist} +Release: 2%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -84,6 +84,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Fri Feb 08 2008 Dave Airlie 6.7.197-2 +- rebase to upstream git master - add rv67x ids + * Mon Feb 04 2008 Dave Airlie 6.7.197-1 - rebase to upstream git master - add r5xx and r6xx pci ids to xinf