diff --git a/radeon-6.9.0-add-hd3300.patch b/radeon-6.9.0-add-hd3300.patch deleted file mode 100644 index afc4610..0000000 --- a/radeon-6.9.0-add-hd3300.patch +++ /dev/null @@ -1,69 +0,0 @@ -commit df061f6e95f2e33a25ac44b6aad974b7788f97e7 -Author: Dave Airlie -Date: Wed Oct 29 15:53:57 2008 +1000 - - pciid: add HD3300 - 790GX chipset. - - RH BZ (#466706) - -diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index 633c5d3..ba7832e 100644 ---- a/src/ati_pciids_gen.h -+++ b/src/ati_pciids_gen.h -@@ -383,3 +383,4 @@ - #define PCI_CHIP_RS780_9611 0x9611 - #define PCI_CHIP_RS780_9612 0x9612 - #define PCI_CHIP_RS780_9613 0x9613 -+#define PCI_CHIP_RS780_9614 0x9614 -diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index 07e71a3..9366600 100644 ---- a/src/pcidb/ati_pciids.csv -+++ b/src/pcidb/ati_pciids.csv -@@ -384,3 +384,4 @@ - "0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics" - "0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" - "0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" -+"0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics" -diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index daaf717..3e9cfb9 100644 ---- a/src/radeon_chipinfo_gen.h -+++ b/src/radeon_chipinfo_gen.h -@@ -303,4 +303,5 @@ RADEONCardInfo RADEONCards[] = { - { 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, - { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, - { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, - }; -diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index 79b094a..2a96267 100644 ---- a/src/radeon_chipset_gen.h -+++ b/src/radeon_chipset_gen.h -@@ -303,5 +303,6 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" }, - { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, - { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, -+ { PCI_CHIP_RS780_9614, "ATI Radeon HD 3300 Graphics" }, - { -1, NULL } - }; -diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index ff1801f..48dea44 100644 ---- a/src/radeon_pci_chipset_gen.h -+++ b/src/radeon_pci_chipset_gen.h -@@ -303,5 +303,6 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA }, - { PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA }, - { PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA }, - { -1, -1, RES_UNDEFINED } - }; -diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h -index d650f9f..da6e5f7 100644 ---- a/src/radeon_pci_device_match_gen.h -+++ b/src/radeon_pci_device_match_gen.h -@@ -303,5 +303,6 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ), - { 0, 0, 0 } - }; diff --git a/radeon-6.9.0-dig1-hdmi.patch b/radeon-6.9.0-dig1-hdmi.patch deleted file mode 100644 index adc5b88..0000000 --- a/radeon-6.9.0-dig1-hdmi.patch +++ /dev/null @@ -1,75 +0,0 @@ -diff --git a/src/atombios_output.c b/src/atombios_output.c -index 49de04f..544c4c4 100644 ---- a/src/atombios_output.c -+++ b/src/atombios_output.c -@@ -374,6 +374,61 @@ atombios_output_digital_setup(xf86OutputPtr output, int device, DisplayModePtr m - return ATOM_NOT_IMPLEMENTED; - } - -+/* lame. this should go in the server. */ -+static int -+atombios_maybe_hdmi_mode(xf86OutputPtr output) -+{ -+ int i = 0, version, offset; -+ char *edid = NULL; -+#ifndef EDID_COMPLETE_RAWDATA -+ /* there's no getting this right unless we have complete EDID */ -+ return ATOM_ENCODER_MODE_HDMI; -+#else -+ if (output->MonInfo) -+ return ATOM_ENCODER_MODE_DVI; -+ -+ if (!(output->MonInfo->flags & EDID_COMPLETE_RAWDATA)) -+ return ATOM_ENCODER_MODE_DVI; -+ -+ if (!output->MonInfo->no_sections) -+ return ATOM_ENCODER_MODE_DVI; -+ -+ edid = (char *)output->MonInfo->rawData; -+ if (!edid) -+ return ATOM_ENCODER_MODE_DVI; -+ -+ /* find the CEA extension block */ -+ for (i = 0; i < output->MonInfo->no_sections; i++) -+ if (edid[i * 128] == 0x02) -+ break; -+ if (i == output->MonInfo->no_sections) -+ return ATOM_ENCODER_MODE_DVI; -+ edid += (i * 128); -+ -+ version = edid[1]; -+ offset = edid[2]; -+ if (version < 3 || offset < 4) -+ return ATOM_ENCODER_MODE_DVI; -+ -+ /* walk the cea data blocks */ -+ for (i = 4; i < offset; i += (edid[i] & 0x1f) + 1) { -+ char *x = edid + i; -+ -+ /* find a vendor specific block */ -+ if ((x[0] & 0xe0) >> 5 == 0x03) { -+ int oui = (x[3] << 16) + (x[2] << 8) + x[1]; -+ -+ /* find the HDMI vendor OUI */ -+ if (oui == 0x000c03) -+ return ATOM_ENCODER_MODE_HDMI; -+ } -+ } -+ -+ /* guess it's not HDMI after all */ -+ return ATOM_ENCODER_MODE_DVI; -+#endif -+} -+ - static int - atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode) - { -@@ -405,7 +460,7 @@ atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode) - if (OUTPUT_IS_DVI) - disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DVI; - else if (radeon_output->type == OUTPUT_HDMI) -- disp_data.ucEncoderMode = ATOM_ENCODER_MODE_HDMI; -+ disp_data.ucEncoderMode = atombios_maybe_hdmi_mode(output); - else if (radeon_output->type == OUTPUT_DP) - disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DP; - else if (radeon_output->type == OUTPUT_LVDS) diff --git a/radeon-6.9.0-quirk-agp.patch b/radeon-6.9.0-quirk-agp.patch deleted file mode 100644 index 29ea0a4..0000000 --- a/radeon-6.9.0-quirk-agp.patch +++ /dev/null @@ -1,82 +0,0 @@ -diff -up xf86-video-ati-6.9.0/src/atipciids.h.dave xf86-video-ati-6.9.0/src/atipciids.h ---- xf86-video-ati-6.9.0/src/atipciids.h.dave 2008-02-19 00:41:27.000000000 +1000 -+++ xf86-video-ati-6.9.0/src/atipciids.h 2008-10-29 16:04:14.000000000 +1000 -@@ -35,8 +35,11 @@ - - /* PCI Vendor */ - #define PCI_VENDOR_ATI 0x1002 -+#define PCI_VENDOR_IBM 0x1014 - #define PCI_VENDOR_AMD 0x1022 - #define PCI_VENDOR_DELL 0x1028 -+#define PCI_VENDOR_VIA 0x1106 -+#define PCI_VENDOR_INTEL 0x8086 - - #include "ati_pciids_gen.h" - -diff -up xf86-video-ati-6.9.0/src/radeon_dri.c.dave xf86-video-ati-6.9.0/src/radeon_dri.c ---- xf86-video-ati-6.9.0/src/radeon_dri.c.dave 2008-10-29 16:03:59.000000000 +1000 -+++ xf86-video-ati-6.9.0/src/radeon_dri.c 2008-10-29 16:04:14.000000000 +1000 -@@ -868,6 +868,41 @@ static void RADEONDRIInitGARTValues(RADE - - } - -+/* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with -+ * the standard AGPMode settings, so we detect and handle these -+ * on a case-by-base basis with quirks. To see if an AGPMode is valid, test -+ * it by setting Option "AGPMode" "1" (or "2", or "4" or "8"). */ -+typedef struct { -+ unsigned int hostbridgeVendor; -+ unsigned int hostbridgeDevice; -+ unsigned int chipVendor; -+ unsigned int chipDevice; -+ unsigned int subsysVendor; -+ unsigned int subsysDevice; -+ unsigned int defaultMode; -+} radeon_agpmode_quirk, *radeon_agpmode_quirk_ptr; -+ -+/* Keep sorted by hostbridge vendor and device */ -+static radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { -+ -+ /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */ -+ { PCI_VENDOR_INTEL,0x2570, PCI_VENDOR_ATI,0x4a4e, PCI_VENDOR_DELL,0x5106, 4 }, -+ /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */ -+ { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4c59, 0x1014,0x052f, 1}, -+ /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ -+ { PCI_VENDOR_INTEL,0x3575, PCI_VENDOR_ATI,0x4c59, PCI_VENDOR_DELL,0x00e3, 2 }, -+ /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ -+ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1025,0x0061, 1 }, -+ -+ /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (LP: #133192) */ -+ { 0x1849,0x3189, PCI_VENDOR_ATI,0x5960, 0x1787, 0x5960, 4}, -+ -+ /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */ -+ { 0x1106,0x3189, PCI_VENDOR_ATI,0x514d, 0x174b,0x7149, 4 }, -+ -+ { 0, 0, 0, 0, 0, 0, 0 }, -+}; -+ - /* Set AGP transfer mode according to requests and constraints */ - static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) - { -@@ -890,6 +925,21 @@ static Bool RADEONSetAgpMode(RADEONInfoP - else defaultMode = 1; - } - -+ /* Apply AGPMode Quirks */ -+ radeon_agpmode_quirk_ptr p = radeon_agpmode_quirk_list; -+ while (p && p->chipDevice != 0) { -+ if (vendor == p->hostbridgeVendor && -+ device == p->hostbridgeDevice && -+ PCI_DEV_VENDOR_ID(info->PciInfo) == p->chipVendor && -+ PCI_DEV_DEVICE_ID(info->PciInfo) == p->chipDevice && -+ PCI_SUB_VENDOR_ID(info->PciInfo) == p->subsysVendor && -+ PCI_SUB_DEVICE_ID(info->PciInfo) == p->subsysDevice) -+ { -+ defaultMode = p->defaultMode; -+ } -+ ++p; -+ } -+ - from = X_DEFAULT; - - if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->dri->agpMode)) { diff --git a/radeon-6.9.0-to-git.patch b/radeon-6.9.0-to-git.patch index 96ad34b..65ad506 100644 --- a/radeon-6.9.0-to-git.patch +++ b/radeon-6.9.0-to-git.patch @@ -1,18 +1,1624 @@ +commit 2346fd7cbd90dcdce2b361d374a53da064fa6a12 +Author: Dave Airlie +Date: Thu Dec 18 16:35:13 2008 +1000 + + radeon: add all new pci ids for rv730/rv710 families + +commit b2b43905a5385a8bb0b59b8e50952863d8dacb59 +Author: Alex Deucher +Date: Wed Dec 17 00:59:52 2008 -0500 + + Pre-avivo: fix FP setup + + - make sure to clear various shadow timing bits + - crtc1 select bit was set wrong. + - should fix bugs like 19100 + +commit 3754cc23abac99880eda87d06aa42e16081b6c8a +Author: Alex Deucher +Date: Wed Dec 17 00:56:19 2008 -0500 + + R2xx: switch EXA composite to rects rather quads + + For conistency with Xv path and to reduce potential diagonal tearing + +commit e3b08cb59716b525b3063b184eab70e32b9d66f0 +Author: Dave Airlie +Date: Tue Dec 16 15:43:16 2008 +1000 + + atombios: correct fix for previous issue. + + I committed an old patch. + +commit 1431bc6900b0e0d7f486b5b3ba281873472b3fdc +Author: Dave Airlie +Date: Tue Dec 16 15:31:34 2008 +1000 + + atombios: fix issue with Clearing of MM_INDEX 0. + + While playing with tv-out I discovered this issue with clearing + the MM_INDEX register. + +commit f72367aff2d09161d30066a00673ba291b292a36 +Author: Dave Airlie +Date: Tue Dec 16 12:32:24 2008 +1000 + + radeon: add initial rv730 pciids. + + Lots more to come, this just adds a few to start. + +commit 4d2429f3ec4d7d3e1512b268c7ff5cbff8d186b4 +Author: Dave Airlie +Date: Tue Dec 16 12:19:00 2008 +1000 + + DCE32: add support for DCE3.2 digital outputs. + + This adds support for the digital outputs on the RV730. + +commit 4d3792fd1b9f733107582436540f483d8993199f +Author: Dave Airlie +Date: Fri Dec 12 10:34:57 2008 +1000 + + radeon: fixes from Alex for some output engines + (cherry picked from commit 1e8ac6ea7b35ccbc3649c96ead60f69158f66ebc) + +commit f892154dbd0d8b6dd8abdf2196ab0c7c18327412 +Author: Alex Deucher +Date: Mon Dec 15 19:41:32 2008 -0500 + + R3xx-R5xx: switch back to quad rendering for Xv + + The large clipped triangle trick hits the guardband limits on + large displays. This gets textured video working again + until we sort out how to deal with the situation better. + + See bug 19046 + +commit 62344e460f5d0cac81f94c535cda77d3d76528a9 +Author: Alex Deucher +Date: Mon Dec 15 11:30:42 2008 -0500 + + Remove remnants of unused DDCMode option + +commit f1efee6a11dc9436276fb12cfb90aa79ada1192b +Author: Alex Deucher +Date: Mon Dec 15 11:27:17 2008 -0500 + + Remove mention of MergedFB from server log + + noticed by Fabio, bug 19098 + +commit 94bffac6968057cdedc792f8540fe44cb6ecfd7c +Author: Fabio +Date: Mon Dec 15 11:22:56 2008 -0500 + + man page updates + + from bug 19098 with some minor fixes from me + +commit c7899905ec824071f9cabbd1e271c4d76010b733 +Author: Fabio +Date: Mon Dec 15 10:58:23 2008 -0500 + + Remove duplicate ATI in some device names + + from bug 19098 + +commit 89a8fd5337c77abf1f3166e69ed061d85b5c20f0 +Author: Dave Airlie +Date: Mon Dec 15 14:41:10 2008 +1000 + + r600: don't idle engine + (cherry picked from commit b77729448e487d37707ce028d8edc59352d1cc2d) + +commit 4ce255a9db8027f2471ba50e57724d3e4d5b16ba +Author: Fabio +Date: Fri Dec 12 09:53:33 2008 -0500 + + Fix formatting in man page + + fixes bug 19039 + +commit 0e99017cb9a6d46b891705df73678c2705439532 +Author: Joseph Adams +Date: Thu Dec 11 00:57:03 2008 -0500 + + Add more eMac modes, fix crash in last patch + +commit fb46c30d316ab3ec54c54f3aec91d5164070a423 +Author: Alex Deucher +Date: Wed Dec 10 17:16:56 2008 -0500 + + Add support for Apple eMacs + + Thanks to Joseph Adams for helping me sort this out. + Verified on eMac G4/1.0 with radeon 7500 + Later eMacs with radeon 9200 or 9600 chips may have + different ddc setups. Need to verify. + +commit c0bcea9150ef215fa614733cef9a5b71a55a33bd +Author: Alex Deucher +Date: Wed Dec 10 11:40:47 2008 -0500 + + Add another AGP quirk + + fixes bug 12544 + +commit 607b02d6abf78147902a5944bd006897ad95e982 +Author: Alex Deucher +Date: Wed Dec 10 03:54:35 2008 -0500 + + Add randr 1.3 panning support + +commit 24007acbf36bcfd09cb5e74ce4a8d918d393cf34 +Author: Benjamin Close +Date: Wed Dec 10 02:17:56 2008 -0500 + + [PATCH] xf86misc extension has been removed, update driver to reflect it + +commit 69e445f7f2ebd299070e44457b434bbc28b7e05c +Author: Dave Airlie +Date: Tue Dec 9 18:59:11 2008 +1000 + + radeon: memset the pll setting function + + Thanks to Peter Zijlstra for making me debug this and providing + feedback. + +commit c72b732a2f5597cd72bd4ebe207799ae07f2681e +Author: Adrian Friedli +Date: Mon Dec 8 10:42:46 2008 -0500 + + Add another AGP quirk + +commit 979ad04d901676cb41aea5cf47a8a2e9c19064dd +Author: Alex Deucher +Date: Fri Dec 5 17:53:57 2008 -0500 + + Add missing .TP in man page + +commit b89d434011787fb71593395f462d142375783e35 +Author: Pierre Ossman +Date: Fri Dec 5 17:52:02 2008 -0500 + + Fix scissor setup for Xv + + We need to adjust the scissoring for each clip box, so move the setup + to inside the while loop. + +commit 83c1115333cbe763f86422fa5aabf4ab21951e68 +Author: Alex Deucher +Date: Fri Dec 5 11:52:18 2008 -0500 + + R200: Remove scissor setup from init3d() + + We aren't using them, so no need to set them up. + +commit 7593d5399cdb2f42ecbcb5193580385b286a9db9 +Author: Alex Deucher +Date: Fri Dec 5 11:18:15 2008 -0500 + + set coherent mode consistently (enabled for now) + + It's set to enabled in the output setup, but then was set to + disabled when teh output properties were setup. Set it up + consistently. + +commit ad2579f8898251105a6b36b745afd1ce1dab103e +Author: Dave Airlie +Date: Fri Dec 5 20:03:53 2008 +1000 + + radeon: damn you bios, HDMI cannot have DACs. + +commit bae30856f2cb3884387ef347327af6ff00b75854 +Author: Alex Deucher +Date: Fri Dec 5 08:15:59 2008 +0100 + + Make VSync for EXA and Xv configurable + +commit 33638d9e388b330e2f4eb4debd05ba09924cf176 +Author: Pierre Ossman +Date: Thu Dec 4 23:29:31 2008 +0100 + + Optimise RADEONWaitForVLine + + Only avoid the vlines we are rendering to, instead of the entire + screen. This way we don't stall the card for longer than we + absolutely have to. + + EXA calls fixed by Alex Deucher. + +commit d1690f5cc096e2f735c8b407c370a1c1cd7a8afc +Author: Pierre Ossman +Date: Wed Dec 3 21:49:37 2008 +0100 + + Improve tearing avoidance for Xvideo in two steps + + - Fix up VLINE handling to trigger whenever scanout is outside the + visible area. + + - Render the video as a scissored triangle as R300+ cannot render a + quad in a single pass. + +commit 4d98acbca2e630056bf56cdcd0e23007fded2ced +Author: Alex Deucher +Date: Wed Jul 16 03:14:06 2008 -0400 + + First pass at tear-free accel + + if the dest pixmap is the front buffer, stall the pipe + until the vline is outside the active area. + For EXA, pick crtc based on the larger mode area; + ideally we'd have one pixmap per crtc. + For Xv, use dst window area to determine crtc. + +commit 82d67b70d0fb747cf7b1eb0b64244ae56cb84572 +Author: Pierre Ossman +Date: Thu Dec 4 15:38:13 2008 -0500 + + Switch r200 Xv to use rect lists rather than quads to avoid tearing + + Patch from Pierre with fixes from me. + +commit 9eccd0ad0827a1b8ec9abb2cebf5768d204a5ce9 +Author: Alex Deucher +Date: Thu Dec 4 12:28:12 2008 -0500 + + Fix up US setup after r3xx bicubic merge + +commit e13fba853ba19e6b0f081b9b3d9fa76c38a0f82b +Merge: d296337... 79bbdd9... +Author: Alex Deucher +Date: Thu Dec 4 12:25:29 2008 -0500 + + Merge branch 'bicubic' of git://git.infradead.org/users/drzeus/xf86-video-ati + +commit d29633708b5451f5541e88371d831ae03019a7f5 +Author: Dave Airlie +Date: Thu Dec 4 09:08:48 2008 +1000 + + radeon: apply atom quirks to object table + +commit 941ac0d3ab839dc5aaaef2f3b7f5c7085b2894c5 +Author: Alex Deucher +Date: Wed Dec 3 17:31:25 2008 -0500 + + Make sure 3D state is emited when switching to 3D IB + + - fixes bug 18864 + +commit 79bbdd984c925e37f5b3db2605339f1a21377fcf +Author: Pierre Ossman +Date: Wed Dec 3 20:33:36 2008 +0100 + + Change the XV_BICUBIC attribute to a tristate, where the third state + automatically turns the filter on and off as appropriate. + +commit bbdf821c179242266fd86edf9e688a6be9cf985f +Author: Pierre Ossman +Date: Wed Dec 3 19:42:50 2008 +0100 + + Make the R300 bicubic shader program a bit easier to understand by + having comments that describe the operation, not how it has to be + implemented in the hardware. + +commit 8f4b22932c91f1d51fcbf1d1a99d852fcdaafdcc +Author: Pierre Ossman +Date: Wed Dec 3 19:31:31 2008 +0100 + + Now that we have a bicubic code path that messes up the pixel shader, + we need to restore it in the non-bicubic code. + +commit 0851daa6e7db77e440188d774ef8b3236146bcb9 +Author: Pierre Ossman +Date: Wed Dec 3 19:17:36 2008 +0100 + + Fix macros so that they are safe to use with expressions as parameters. + +commit e04bcb0066781f61e97787856261e3380036d304 +Author: Pierre Ossman +Date: Wed Dec 3 19:16:03 2008 +0100 + + Fix node setup on R300 bicubic pixel shader. It was backwards and used + the wrong base for sizes. + +commit 927aee181f3637bda1b761caf93fbc0652e1207b +Author: Alex Deucher +Date: Wed Dec 3 01:39:38 2008 -0500 + + Only flush IB when direct rendering is enabled + +commit ca74ebf8813b7fab8d08465ef9600f001c948e94 +Author: Alex Deucher +Date: Tue Dec 2 22:26:21 2008 -0500 + + move 3d state init after RADEON_SWITCH_TO_3D() + +commit fc079c5267baf431bbecee7744e484783d393152 +Author: Dave Airlie +Date: Tue Dec 2 22:11:57 2008 -0500 + + Don't mix 2D and 3D in the same IB + + fix from radeon-gem-cs + +commit 678693aabd0b4c1812ab44bf5abb4c8394b254bb +Author: Dave Airlie +Date: Tue Dec 2 22:02:21 2008 -0500 + + Stability fixes from radeon-gem-cs + +commit f231e4d9b2c683dc16f42cf09484fae926a892c1 +Author: Dave Airlie +Date: Wed Dec 3 11:39:04 2008 +1000 + + radeon: fix HDMI having DACs in some BIOSes + +commit fe73d9a7dfe8ec5c8f1a8dc08e14b4e138aa9276 +Author: Bryce Harrington +Date: Tue Dec 2 19:47:45 2008 -0500 + + Add another AGP quirk + +commit 6e0c48958c6a50a639368e369ce72d813256aee4 +Author: Alex Deucher +Date: Mon Dec 1 18:50:40 2008 -0500 + + Add quirk for r200 card with the primary dac wired to both ports + + refactor load detection setup as a byproduct + should fix bug 18719 + +commit fa496d7b0397d9be57db90d0860928e9ced73cca +Author: Pierre Ossman +Date: Mon Dec 1 08:29:29 2008 +0100 + + Fix comments for R500 fragment shader to reflect the code. + +commit 0d95fca114194664d9ab612c90d3222912cf41ff +Author: Corbin Simpson +Date: Sat Aug 30 12:38:43 2008 -0700 + + Fix indentation on IS_R300_3D Xv code. + +commit 36a62b8c47def3f23a0b735875f59d23ed3c095a +Author: Corbin Simpson +Date: Sat Aug 30 11:15:20 2008 -0700 + + r3xx: Various Xv fixes. + +commit 01ed5462fad56f5b7bf867041d00443bdf81c653 +Author: Corbin Simpson +Date: Thu Aug 7 18:08:54 2008 -0700 + + Switch to Mesa-style 24-bit float packing. + Seems like Mesa's got it right, so we should follow suit. + +commit 85bbe889045aa434f71a3eb0ba8153b7d2cc5023 +Author: Maciej Cencora +Date: Thu Aug 7 07:06:46 2008 -0700 + + Enable bicubic Xv on r3xx+. Still some buggies in the actual display, but looks pretty good. + +commit bf6263cff50bb85c19ff6dfebb739333fa8aca18 +Author: Maciej Cencora +Date: Thu Aug 7 07:00:36 2008 -0700 + + Add r3xx-specific bicubic filtering code. FP, RS, mostly, everything else is shared with r5xx. + +commit da021c36bbdf3bca31ee50ebe01cdb9495c09b36 +Author: Dave Airlie +Date: Sun Nov 30 18:44:24 2008 +1000 + + radeon_drm.h: remove kernel defines + + remove these we should update from an installed kernel copy not from the + original kernel copy. + +commit 783cdb7374941bb1d2b63eea375fbf2f1b808cc3 +Author: Dave Airlie +Date: Thu Nov 27 15:29:06 2008 +1000 + + r100/r200: EXA misrenders dst == a8 + dst alpha use. + + Fedora BZ#469556 + + I've played with various dst and texture formats and rewritten large + parts of this to no avail, so I'm punting for now. + +commit 2d7cfc421713286edd5121b56999246f9ae70286 +Author: Eygene Ryabinkin +Date: Tue Nov 25 13:25:33 2008 -0500 + + Catch unsubstituted macro for PCI region base access + + also fix up some warnings. + +commit af7690b9c300d37c3a0c51e27e0ad2ca009224a2 +Author: Benjamin Herrenschmidt +Date: Tue Nov 25 02:57:30 2008 -0500 + + [PATCH] radeon: Fix PCI usage of 32-bit driver on 64-bit platform + + The radeon driver is storing PCI addresses in unsigned long's which + won't work well on 32-bit platforms with 64-bit physical address space + such as PowerPC 4xx. This fixes it by using unsigned long long instead. + +commit 065938617c0feab17f4274a5350de02a692ba065 +Author: Ramon van der Stelt +Date: Tue Nov 25 02:23:46 2008 -0500 + + Interlaced mode fixes + + see bug 12626 + +commit 36a7dc6ea1e1929e986ab1159497c71521cb2f10 +Author: Bryce Harrington +Date: Tue Nov 25 01:04:37 2008 -0500 + + Additional AGP quirks + + bug 18693 + +commit 2acb8e4ed220fccb21b22a53c5142ab3a35d32ef +Author: Alex Deucher +Date: Tue Nov 25 15:07:09 2008 +1000 + + radeon: fixup shared DDC lines for some rv610 cards. + + Some cards share DDC between a HDMI and VGA output, and expect the + driver to use load detect or EDID to figure it out. + + airlied- shipped in RHEL5 + + Signed-off-by: Dave Airlie + +commit b01e35168de40d192fd7a9ce6884b9c7419afbd4 +Author: Alex Deucher +Date: Mon Nov 24 21:06:42 2008 -0500 + + Fix up posted logic + + noticed by benh on IRC + +commit d7a03e93372b17d642b42f5490464616ae7c99c1 +Author: Alex Deucher +Date: Mon Nov 24 15:52:05 2008 -0500 + + Get hardcoded edid from the bios for servers that support it + + should fix bug 11300 + +commit 3858e31fa9d77d52a5cabb02f53f06385eab40f7 +Author: Alex Deucher +Date: Mon Nov 24 14:39:41 2008 -0500 + + Don't support rotation is accel is not available + + Fixes bug 18068 + +commit 3d27876d91ef69d71f17b6cf8c07c26bf12857b4 +Author: Dave Airlie +Date: Mon Nov 10 15:47:13 2008 +1000 + + radeon: always align dstPitch to 64 bytes for textured video + + bz# 18454 + +commit 6c8b352264540ccc4622a7c0b704ce452dcd707d +Author: Dave Airlie +Date: Wed Oct 29 15:53:57 2008 +1000 + + pciid: add HD3300 - 790GX chipset. + + RH BZ (#466706) + +commit 902eaf768142c6c7dcc487e10775027b84cd1f9a +Author: Alex Deucher +Date: Thu Nov 6 15:46:43 2008 -0500 + + Check for LVDS on all IGP chips + + - fixes bug 18395 + +commit 44abaa0ea8e5e3bbe833fa73e6d011618bb6d7e7 +Author: Adam Jackson +Date: Mon Nov 3 15:09:28 2008 -0500 + + Fix HDMI output setup on DIG1/DIG2. + + The only reliable way to detect an HDMI sink is to check for the + appropriate EDID extension block, so this will only work right on + servers with xf86DoEEDID(). RANDR 1.2 will call this internally for + us if it exists, but pre-1.6 servers are out of luck. + +commit 937b7ac2a259cf504a19dcf62a58b1db1afb8eb9 +Author: Bryce Harrington +Date: Wed Oct 29 01:31:50 2008 -0400 + + Add AGP quirk table + + - set known good default agp modes for problematic chip/bridge combos + - should fix bug 17360, others + +commit 67bc2ae7f227a2afedc8e699cf0458fa7960f301 +Author: Julien Cristau +Date: Sun Oct 26 16:05:04 2008 +0100 + + Bug#7148: Fix manpage formatting + +commit 98fdd78a1229584b922f816f331a45bfc178c961 +Author: Dave Airlie +Date: Tue Oct 21 18:36:22 2008 +1000 + + atombios: oops typo + +commit 763dff6c117a10b6a57ba1854c5b798359789e44 +Author: Dave Airlie +Date: Tue Oct 21 18:35:44 2008 +1000 + + atombios: set missing pixel clock + +commit 435cf7da68186f2601c4b888296117d4f652c625 +Author: Alex Deucher +Date: Wed Oct 15 10:52:14 2008 -0400 + + Add LCD dithering quirk for macbook pro + + fixes bug 17897. + +commit c0e6cb6d0eeef8f2ea60d840e1cd668fa92cd7f9 +Author: Alex Deucher +Date: Fri Oct 10 11:09:27 2008 -0400 + + Fix grey level dithering setup + +commit 9eb2b6cd28224f0cbbabf3df451696ae1a845b9c +Author: Dave Airlie +Date: Fri Oct 10 16:18:05 2008 +1000 + + radeon: hopefully fix plls for 30" monitors. + + Only do the HIGH trick on the DCE3 cards. Tested on rv610/630/770. + +commit 0975e007ec7933acf9cd8ad2f281313ef8d32ac9 +Author: Dave Airlie +Date: Thu Oct 9 17:16:28 2008 +1100 + + radeon: rename radeon_memory to radeon_legacy_memory. + + This is a setup patch for the kms/memory management code. + +commit d744dc013cf5ca3141c0fdf55e36d713fe9f53ba +Author: Adam Jackson +Date: Wed Oct 8 15:50:25 2008 -0400 + + Fix connector table mapping for lvtma/kaleidoscope/uniphy. + + Fixes DPMS on LVDS. + +commit dc795ba66a8c0eb2c3fdb86bd42dfc17e0aa3b6e +Author: Alex Deucher +Date: Tue Oct 7 12:32:47 2008 -0400 + + Fixups from last DFP/LCD refactor + + - fix DFP1 -> LCD1 + - use _INDEX rather than _SUPPORT defs + +commit 4a9e8d9fe24278b56aef51677fd35289d01584a7 +Author: Alex Deucher +Date: Mon Oct 6 18:00:08 2008 -0400 + + set grey levels correctly for temporal dithering + +commit 5708624d1151877dd66a462d4a75fed6774604a7 +Author: Alex Deucher +Date: Mon Oct 6 15:11:56 2008 -0400 + + Turn coherent mode off by default on DVI + +commit a5c5ce96279d01eb519bfb92b94c06a58acb7f07 +Author: Alex Deucher +Date: Mon Oct 6 15:07:31 2008 -0400 + + Refactor atom LCD/DFP output setup + + Simplify the code, properly handle dithering, coherent mode, encoding, etc. + Should fix bug 17897. + +commit f9826a5694b7adb6920eb5bdf45d840d8fb14d53 +Author: Alex Deucher +Date: Fri Oct 3 15:24:12 2008 -0400 + + Add support for DDC via atom commands for RV410 + + The atom calls use the hw i2c engine for DDC. For some + reason, sw i2c doesn't seem to work on the VGA GPIO on + RV410 chips, so we use atom in that case. + + This fixes the longstanding VGA DDC problems on RV410/M26 + chips. + +commit 23c17c0121d43c2fd11bb5cfbaa4b02abac2b16d +Author: Alex Deucher +Date: Fri Oct 3 14:30:33 2008 -0400 + + man page updates + + Update render accel and page flipping information. + fixes bug 17887. + +commit 4ac6e499089aec3c79af5dbede5fe631b105ce3d +Author: Alex Deucher +Date: Wed Oct 1 18:53:15 2008 -0400 + + proper fix for initial rotation + + The initial modeset was setting the MC regs, so just set them + rather than the full modeset. + +commit 346228b20c69a965c9e7d67157f42c1d36a5b6c3 +Author: Alex Deucher +Date: Wed Oct 1 14:38:27 2008 -0400 + + Workaround to make initial rotation work + + Acceleration needs to be initialized before setting the mode + for initial rotation to work. Changing the order in RADEONScreenInit() + doesn't work because RADEONDRIKernelInit() hangs in the ioctl to + initialize the CP if the mode is not set prior (even if the heads + are turned off after setting the mode). The workaround is to set the + modes twice, once before accel and once after. + + This needs to be looked into further. + +commit c359c2a31caf9f75b9fc6b6bcbc3e9dc1fe404ba +Author: Michel Dänzer +Date: Tue Sep 30 11:04:54 2008 +0200 + + Pass base offset into RADEONDisplayVideo() explicitly. + + This prevents the base offset from flipping back and forth if double buffering + is enabled and the two buffers start on different sides of a 4 MB boundary. + + Should fix http://bugs.freedesktop.org/show_bug.cgi?id=17254 ; please don't + reopen that bug report without attaching a log file captured after reproducing + the problem with this fix. + +commit ba21d5ae7fbbf5828c44c41655aff8b182453e2e +Author: Michel Dänzer +Date: Tue Sep 30 11:03:04 2008 +0200 + + Update GEN_INT_CNTL register value after calling DRM modeset ioctl. + + Fixes sync-to-vblank hangs after mode switch with DRM vblank-rework. + +commit 3110646daf05fa09faaa70066cc8c3db1bb07cec +Author: Michel Dänzer +Date: Sun Sep 14 11:46:36 2008 +0200 + + Fix -Werror build. + +commit d82f2938f69402c641a1c8362fdc513419b27659 +Author: Alex Deucher +Date: Fri Sep 26 13:51:24 2008 -0400 + + atombios updates from upstream + +commit d0d58b39e49c5ce00bc8bd12f721ad8c7f554b91 +Author: Alex Deucher +Date: Wed Sep 24 11:54:34 2008 -0400 + + radeon: Further pll adjustments + +commit d100a6af8f828eb94f8ba6e8a96c24389b5cf46f +Author: Alex Deucher +Date: Fri Sep 19 14:04:59 2008 -0400 + + cleanup macbook quirk + +commit 1218e38c75351a20f7414ba6fcb3545689339442 +Author: Alex Deucher +Date: Fri Sep 19 13:52:07 2008 -0400 + + more macbook fixes + +commit 83e1f132965deadedda7a622184eb400cd4c120c +Author: Alex Deucher +Date: Fri Sep 19 09:36:59 2008 -0400 + + Fix copy/paste error in the last commit + + DVI-D -> DVI-I + +commit 4af825f7b13cba8c3b204e72a07cab5009331240 +Author: Alex Deucher +Date: Fri Sep 19 00:29:20 2008 -0400 + + radeon: Add quirk for macbook + + - should fix bug 17625 + +commit 38aa450fce6a91b35c191fd07112490a62cc29c6 +Author: Alex Deucher +Date: Tue Aug 26 21:50:23 2008 -0400 + + fix some fallout from the common allocator + + should fix bug 17317 + +commit a3cc1d7a421456186024c5c069e403d374a0f0b9 +Author: Dave Airlie +Date: Tue Aug 26 08:03:20 2008 +1000 + + radeon: fix powerpc build + +commit 6cebfe257f7ddad855ee743e4eb899bd6fac7f46 +Author: Alex Deucher +Date: Fri Jul 11 19:32:06 2008 -0400 + + Switch EXA path back to static cursor allocation + + pre-AVIVO cards have address limits for the cursor offset + +commit 4dff54a3c8d7c9f2d6ec50354ff0b92f1b7fcbdf +Author: Alex Deucher +Date: Fri Jul 11 17:28:03 2008 -0400 + + Switch cursors over to generic allocator + +commit 5b1978a4796bcc31ac2f01d303dc8f8f44323025 +Author: Alex Deucher +Date: Mon Aug 25 10:05:28 2008 -0400 + + Bicubic fixes from the last cherry-pick + +commit 7daba77ded1c718e93ae8c372a39a6e85228d513 +Author: Alex Deucher +Date: Fri Jul 11 02:02:38 2008 -0400 + + Convert randr, Xv to a common allocator + +commit 610fe1a937da78f4ac813ac919c158dde8f42442 +Author: Alex Deucher +Date: Thu Jul 10 22:47:35 2008 -0400 + + Switch to using radeon_drm.h from the drm + + modelled after Matthias' similar rhd change + +commit a6561f2ec673b38907f7181235386f32e60c32ba +Author: Alex Deucher +Date: Thu Jul 10 22:31:13 2008 -0400 + + Move DRI to a separate struct + + based on Matthias' similar work in rhd + +commit 75ef8dc214715d3c5c50996b293933842903ba65 +Author: Egbert Eich +Date: Thu Jul 10 21:49:55 2008 -0400 + + Cleanups from rhd port + + - remove unused vars + - remove static exa render vars + +commit 71ad140fa11f3a504c38d6bddf40e3a3c0a20e60 +Author: Alex Deucher +Date: Thu Jul 10 21:24:16 2008 -0400 + + Move accel state to a separate struct + +commit 5b2e095c31b88d8495a4f86e6cb46b49fa4acd65 +Author: Alex Deucher +Date: Thu Jul 10 20:07:44 2008 -0400 + + Move CP into a separate struct + +commit 2145309230e36aee7758bd244deb1e72ada0c065 +Author: Alex Deucher +Date: Mon Aug 25 08:47:59 2008 -0400 + + match textured video macro names with other accel code + + OUT_VIDEO_REG() -> OUT_ACCEL_REG() + etc. + +commit 01daef0f095fbbaee701d5fe97f3dd7838b5f915 +Author: Alex Deucher +Date: Mon Aug 25 08:26:16 2008 -0400 + + Additional cleanups and re-arragement following bicubic merge + +commit 0a51d08c24af040fe48690662b1a912acad51700 +Author: Alex Deucher +Date: Mon Aug 25 06:43:14 2008 -0400 + + Whitespace cleanup from bucubic merge + +commit c0170fef510b53a6ca2c6ea7a99119235229c929 +Author: Maciej Cencora +Date: Thu Aug 7 06:53:39 2008 -0700 + + Add needed FP registers, etc. for r3xx bicubic Xv. + +commit d9c38326cf70f57ab777ffdf9520b8cdea9d9cb6 +Author: Dennis Kasprzyk +Date: Tue Aug 5 18:45:38 2008 +0200 + + Fix typos. + +commit d38ceba62aa5cee76baa342ce7719a983a79f09e +Author: Dennis Kasprzyk +Date: Tue Aug 5 16:21:57 2008 +0200 + + Fix bicubic fp calculation. + +commit 6f9c7fde75edc0399559f975db9a6c4dc22714ae +Author: Dennis Kasprzyk +Date: Tue Aug 5 15:38:42 2008 +0200 + + Fixed bicubic fragment program comments. + +commit 48b09ca40ccb28b5584069316fd38786a78c1dd3 +Author: Corbin Simpson +Date: Sat Aug 2 02:36:21 2008 -0700 + + Switch from 32-bit floats to 16-bit half-floats. + Massive bandwidth savings, or so I'm told. Yay? + +commit ebbb7fb634fcadf28ff99c1df2c3db89fd56932d +Author: Corbin Simpson +Date: Sat Aug 2 01:45:43 2008 -0700 + + Change floats to uint32_t hex. + Useful for moving to 16-bit half-floats. + +commit 3b46162d8a90be3524cb513d42b9ad3d0bea45f5 +Author: Dennis Kasprzyk +Date: Fri Aug 1 15:24:01 2008 +0200 + + Move some ALU instructions after the TEX instructions, so we can do something usefull while we are waiting for the texture values. + +commit 2ecdec4bafc97212dde4d6908ee4ccf618adc0e1 +Author: Dennis Kasprzyk +Date: Fri Aug 1 04:03:12 2008 +0200 + + Another uneeded SEM_AQUIRE. + +commit e93b5d1b80d6203f63543b7b678e2f1d9221b5b3 +Author: Dennis Kasprzyk +Date: Fri Aug 1 03:00:26 2008 +0200 + + Smarter usage of the texture semaphore. + +commit 286f7aa18f19bd21b263701adab38b736dbeda0f +Author: Corbin Simpson +Date: Thu Jul 31 17:01:44 2008 -0700 + + Enable bicubic filtering for all r5xx HW. + +commit 242aa4f630b4c60aefa3c12dc459a4d4d0b334a0 +Author: Dennis Kasprzyk +Date: Fri Aug 1 01:11:28 2008 +0200 + + Remove one constant. + +commit 413eacb0538977b0b3c92df074d40510f4539abc +Author: Dennis Kasprzyk +Date: Fri Aug 1 00:52:09 2008 +0200 + + Heavy optimizations. + +commit a0c4a949cb49e5ac1e857aef08a8742b9f7b49da +Author: Dennis Kasprzyk +Date: Thu Jul 31 21:19:18 2008 +0200 + + Remove uneeded negations. + +commit abb2b2e757d92591ab9277824b9d9746ba98f875 +Author: Dennis Kasprzyk +Date: Thu Jul 31 20:31:03 2008 +0200 + + Implement LPR in one instruction. + +commit c370b74bec13194573348583c38adf710b880e79 +Author: Dennis Kasprzyk +Date: Thu Jul 31 19:50:49 2008 +0200 + + Set helper texture filter correctly. + +commit 5e85d5a5d0c50b29086ec0c219c8b52d25dbc2e9 +Author: Corbin Simpson +Date: Wed Jul 30 19:45:15 2008 -0700 + + Update bicubic tables. + Now including the 2048x1 texture as well. + +commit 17e5e9573e59c3d82d51c261b9c5005f6aec7d43 +Author: Corbin Simpson +Date: Wed Jul 30 11:57:25 2008 -0700 + + Force R580-only for bicubic. + Initial reading of docs suggest RV560 and RV570 can't handle it, + but they're welcome to test. + +commit 83b52473d0e7102265918b07be053fcda17a14b4 +Author: Corbin Simpson +Date: Wed Jul 30 01:03:57 2008 -0700 + + Bump bicubic cutoff to R580. + RV530 chipsets can't handle fullscreen bicubic... + +commit 69a4998d1286bcdd7bfe874cd5628bc1cc232bae +Author: Corbin Simpson +Date: Wed Jul 30 01:03:46 2008 -0700 + + Oops, made a mistake with vertices. + +commit a4ec30a677906ec2ff9824c7ddca586655f6d1a8 +Author: Corbin Simpson +Date: Wed Jul 30 00:54:32 2008 -0700 + + Merge upstream changes to vertices, and also add Xv attributes for textured video, including bicubic filtering. + +commit f3b81c7582aed307fa44e134ee161cd8a3158657 +Author: Corbin Simpson +Date: Mon Jul 28 19:50:10 2008 -0700 + + Fix constants. + +commit 7dbb7023ba023ec1a38be63af9c9f49e40222b7b +Author: Corbin Simpson +Date: Mon Jul 28 17:30:41 2008 -0700 + + Finally got the fragment program fully working for bicubic filtering on r5xx. + +commit 0e4dd73b9ebc6f608eeff945b4d463a00c02e07c +Author: Corbin Simpson +Date: Mon Jul 28 12:16:50 2008 -0700 + + More bicubic FP buggies. + +commit a87647e0c27e0950f4d0d8203a1242a994ad3419 +Author: Dennis Kasprzyk +Date: Sun Jul 27 10:43:01 2008 -0700 + + Fix texture size, texture filter, vertex offsets, etc. + +commit 232aa3e943fef4c4037b255c3b64a0aaff90ab5c +Author: Corbin Simpson +Date: Sat Jul 26 10:56:56 2008 -0700 + + Make vertices emit properly. + *bangs head against wall* + +commit 8c84f67b93d926095633830aa8d95930a48b1c7b +Author: Corbin Simpson +Date: Sun Jul 20 14:25:44 2008 -0700 + + Try to get tex coords from the VAP to RS properly when bicubic filtering is enabled. + I'm soo bad at this... :c + +commit a4a7d5f5967c51c394229de5eccaec44cfec8f50 +Author: Corbin Simpson +Date: Sat Jul 19 13:02:02 2008 -0700 + + Upload pixel shader to card for r5xx. This was ridiculous. Also it doesn't work yet... + +commit 20c1db2d7c110ab5c1117a57b169baa1ab070518 +Author: Corbin Simpson +Date: Fri Jul 18 13:48:08 2008 -0700 + + Upload bicubic filter to card. This was a LOT easier than I had feared, to be honest. + +commit a760e628134c6d7d42ec3c98118b6e5f6fcd3e7f +Author: Corbin Simpson +Date: Fri Jul 18 12:21:20 2008 -0700 + + Allocate memory for the bicubic filter texture. + +commit b6c9e2bb5365de82315c6814f915e57b0c4fa444 +Author: Corbin Simpson +Date: Fri Jul 18 11:24:14 2008 -0700 + + Fixed typos in the bicubic texture tables. Whoops, looks like I'm still asleep. + +commit ca51f4f37e1dbf53bf7ffc0e8f612e9609e11209 +Author: Corbin Simpson +Date: Fri Jul 18 11:06:34 2008 -0700 + + Add bicubic texture table, as well as the script used to (re)generate it. To regenerate, just run "python bicubic_table.py > bicubic_table.h". + +commit 1cf7a5494fa94e8d9f30f9b2905dfbe6d4faa445 +Author: Bryce Harrington +Date: Wed Aug 20 09:46:59 2008 -0400 + + radeon: Fix pasto in connector table setup for vga powerbooks + + fixes bug 17214 + +commit a55e85f742d1334bf88e4681e553f025d2de38df +Author: Michel Dänzer +Date: Thu Aug 14 15:21:51 2008 -0400 + + Make sure video offerlay offsets don't exceed the hardware limit of 128 MB. + + Always set the overlay base address such that the buffer offsets are as small + as possible. This could still break in theory if the buffers were more than + 128 MB apart, but in reality this can't happen ATM because we always allocate + a single memory area for all buffers. + + Fixes http://bugs.freedesktop.org/show_bug.cgi?id=16845 . + +commit 92ee21df344a989778e37369c7beb3904a00ead6 +Author: Alex Deucher +Date: Thu Aug 14 14:49:45 2008 -0400 + + PLL adjustments + + Seems higher dotclocks prefer a higher FB div. + Someone with a lot of should try and find out where + the div sweet spots are for various dotclock ranges. + fixes bug 17125 + +commit 0d5e0347af4322713075193154b8a348de4a0b52 +Author: Alex Deucher +Date: Wed Aug 13 14:17:34 2008 -0400 + + Remove reset of 3D scissor registers when using the CP in the ddx + + They should only affect 3D and init3d() should take care of that case + noticed by libv on IRC. + +commit 7e456e9c427d48151b166bcac08c3e8a8b180f01 +Author: Dave Airlie +Date: Tue Aug 12 08:18:30 2008 +1000 + + radeon: add 0x9441 for hd 4870 x2 + + thanks to Michael Larabel for testing + +commit 4dbdeea7c9316575fba26b41fd347452e42cdcf2 +Author: Alex Deucher +Date: Fri Aug 8 17:39:48 2008 -0400 + + Further cleanup and unification of i2c code + + - unify the ddc and i2c code + - add gpio mask support for legacy chips + - remove the magic gpio dance for ancient monitors + (if you have an ancient monitor that ddc stops + working on let me know). This should speed up DDC + on legacy chips. + + -- radeon sw gpio i2c -- + 4 sets of gpio registers for clk and data and corresponding bit masks + mask - locks the gpio for use by sw + get - reads the value off the gpio pad + put - sets the gpio direction to output + a - "other stuff" On legacy chips you clear them if you want + to use a gpio for i2c. In some cases they are used for the + output value when the gpio in the output state. + +commit 268c848130ec1770bb645a74197b6aca7fc95abc +Author: Alex Deucher +Date: Fri Aug 8 15:50:07 2008 -0400 + + Fix VT switching on M6 chips + + Some M6 chips have a faulty MEM_SIZE register that in + some cases reports 0 on 8 MB cards. On EnterVT we check + the MEM_SIZE reg as a check to see if the card is posted or + not. Since this reg returns 0, the driver attempts to post + the card which can lead to a hang. Switch this to check if + either crtc is active as is done in the bios init code. + fixes bug 13994 + +commit 33f88f7fc90d9d93fdcbba9ad59dd70a6596bc3f +Author: Alex Deucher +Date: Thu Aug 7 17:57:07 2008 -0400 + + RS4xx DDC fixes take 3 + +commit df0d1ef53100f0a19c5b5fdc349f5186c8d9bd87 +Author: Alex Deucher +Date: Wed Aug 6 19:13:56 2008 -0400 + + RS4xx: Fix up ddc gpio + + - I mixed up the regs previously + +commit 18429390440a829fb24ed3afd99ccf8278138496 +Author: Alex Deucher +Date: Wed Aug 6 00:35:15 2008 -0400 + + Remove un-needed dac check for single crtc cards + + Connector tables should be setup properly already and this + check breaks systems with 2 DACs and 1 crtc like the es1000. + +commit 001c535687d8588873037ee5363d0a709f44b418 +Author: Alex Deucher +Date: Tue Aug 5 17:14:48 2008 -0400 + + IGP: fix typo in IGP quirk handling + +commit eb65ddf70d182b6457e1ef5ebb820456039e8f6d +Author: Alex Deucher +Date: Tue Aug 5 15:01:33 2008 -0400 + + IGP: attempt to get external TMDS working + + RS4xx chips have a tmds init table in the mobile info table + +commit 8b8990917809b9a35c6e9c1b9e3b12ff81c6dbb3 +Author: Alex Deucher +Date: Tue Aug 5 12:16:06 2008 -0400 + + IGP: Updated quirk handling + + - Hopefully finally fix DDC on RS4xx chips + - RS3xx/RS4xx do not have internal TMDS + - general quirk handling cleanup + - we don't currently support mm gpio for external TMDS + so return false. + +commit cb0deba5412a575d36f2f99377120b123506c946 +Author: Calvin Fong +Date: Mon Aug 4 02:04:15 2008 -0400 + + IGP: add support for NTSC tv-out on legacy IGP chips + + Patch from Calvin with some cleanups from me. + No support for PAL yet. + +commit 942b18aca91819fa65d853cd15ffd1cd720cbd68 +Author: Dave Airlie +Date: Mon Aug 4 14:38:21 2008 +1000 + + radeon: make r600 use i2c table lookup for ddc. + + This may fix DDC on rv770 cards. + +commit 1f3eee3682f3598a303c9c3accfbe01b245cacf9 +Author: Alex Deucher +Date: Tue Jul 29 20:29:32 2008 -0400 + + Change prim types for exa and textured video to help avoid tearing + + - r1xx - switch from tri fan to rect list + - r2xx/r3xx/r4xx/r5xx - switch from tri fan to quad list + +commit 5b5441f8cc119db0d1e03dd35bd06015a26270dd +Author: Brice Goglin +Date: Tue Jul 29 23:31:14 2008 +0200 + + Increase default GART size to 32MB on >=R300 + +commit 0a505297f09aefb1b4432176a263bfdf6f256f77 +Author: Alex Deucher +Date: Mon Jul 28 17:12:41 2008 -0400 + + Fix error in driver connector table for powerbook w/ vga + +commit d5799ac53c3e1b2ca1da97780b171a44060c3aad +Author: Alex Deucher +Date: Mon Jul 28 11:09:10 2008 -0400 + + Add quirk for oem x300 card + + - debian bug 492457 + +commit 64dbadddcf6d069c0472f37afeab89d3e31e937d +Author: Owain Gordon Ainsworth +Date: Mon Jul 28 10:40:58 2008 +1000 + + radeon: don't call ioctl unless DRI is initialised + +commit 1c5858484da4fb1c9bc3ac3b4d7a97863ab99730 +Author: Alex Deucher +Date: Mon Jul 21 23:47:45 2008 -0400 + + First pass at InitDispBandwidth() for AVIVO chips + + - support for LB allocation + - MC priority bumps for display1/2 on RV515 variants and RS690 + If you are having display underflow problems (flickering on sides of + screen in high res modes, etc.) on RV515 or RS690 boards, try setting: + Option "DisplayPriority" "HIGH" in your config. + - still no support for full display watermark programming yet + + Something similar might be useful in rhd as well. + +commit b0378bb145c8a915c943bef7d17f2cdecfccc891 +Author: Alex Deucher +Date: Mon Jul 21 13:47:09 2008 -0400 + + Interlaced mode fixups for AVIVO chips + +commit c18fad622a3c4f9572051120d83af68b625b5686 +Author: Alex Deucher +Date: Mon Jul 21 10:36:48 2008 -0400 + + Clear display priority bits before resetting them + +commit dc231ff8e063313d2bcf5acccad67a9f8a7e3314 +Author: Alex Deucher +Date: Mon Jul 21 10:30:41 2008 -0400 + + Clean up legacy display watermark setup + + - makes crtc1 and crtc2 watermark setup independant. + - fixes the case where only crtc2 is active + +commit f9034214f070fe3054cd9cefd7034252de234f38 +Author: Michel Dänzer +Date: Mon Jul 21 09:09:02 2008 +0200 + + Call DRM modeset ioctl after the IRQ has been initialized. + + This lets the DRM know it can safely disable the vblank interrupts. + +commit ecb6347a3d7071890600c98c2addef3a8ca260ee +Author: Alex Deucher +Date: Sat Jul 19 11:34:16 2008 -0400 + + Add oem quirk for external tmds setup on Dell Inspiron 8600 + + Noticed by fnord42 on IRC. + +commit df53d12a06fad41f00cff849458cb358ab5e2098 +Author: Benjamin Herrenschmidt +Date: Thu Jul 17 14:37:05 2008 +1000 + + Fix console switch on R500 + + This patch fixes the console switch for me on R5xx. + + There are two aspects to it: + + - Fix the ordering of avivo_restore() to better match what's + happening in the driver & ATOM, properly locking/unlocking and + only enabling the CRTCs after everything has been properly + programmed. + + - Don't ASIC_INIT if the card has any CRTC enabled. This is the + best I came up with for avoiding spurrious ASIC_INIT on cards that + -are- POSTed but don't have the BIOS coming from c0000 on x86. The + problem with spurrious ASIC_INIT is that we do it before we do + RADEONSave(), so that screws up the console switch. + + Note that I think we also should save/restore the palette, I don't think + we do. right now, it's a minor issue for me because I fixed offb to be + able to set it on AVIVO's but it might still have to be done in the long + run. + + Tested with a VGA analog setup on DACA and a DVI setup on TMDS 0. I + haven't tested any other combo but that should get us going. + + Cheers, + Ben. + + Signed-off-by: Dave Airlie + +commit e8c07270e1fc2ee455320370692aaf90abac2773 +Author: Alex Deucher +Date: Tue Jul 15 17:50:32 2008 -0400 + + ATOM: fix for r4xx cards with no VRAM_Usage tables + + fixes bug 15954 + +commit da41e71efd41907d9347a902720bce60b32550e5 +Author: Alex Deucher +Date: Mon Jul 14 13:21:38 2008 -0400 + + ATOM: Add support for UpdateCRTC_DoubleBufferRegisters cmd table + + locks/unlocks the crtc/grph/mode regs before updating the crtc + +commit a5e0cf13dc7ace6cf0e44e18b73b9a9266e740ab +Author: Julien Cristau +Date: Sun Jul 6 12:17:28 2008 +0200 + + Link with -lpciaccess and -ldrm if needed + + This makes sure the driver ends up with a DT_NEEDED reference to + the libraries it's using. + +commit f8da849fd89322a54cc4d722767da755358eab70 +Author: Michel Dänzer +Date: Sun Jul 13 11:31:03 2008 +0200 + + Only declare local variable when it's used. + +commit a6db4dc65aec560f3b1f37ff73ec6b0bd8207295 +Author: Dave Airlie +Date: Sat Jul 12 18:47:07 2008 +1000 + + atombios: fix typo in mode conversion for panel + +commit 19a0d5879851eff23a3e7d5cdea55bd784051115 +Author: Dave Airlie +Date: Sat Jul 12 17:04:25 2008 +1000 + + atombios: use macro to get offset into table + +commit a9746114369d516072d841ec356ec3ba3d0be71a +Author: Dave Airlie +Date: Sat Jul 12 10:46:36 2008 +1000 + + pciid: add radeon HD3850. + + pci id from legume on #radeon + +commit ab14f725676e4d4e45278c64b03fe2d328a3e439 +Author: Alex Deucher +Date: Fri Jul 11 19:05:00 2008 -0400 + + R300: NUM_FPU adjustments for VAP_CNTL + +commit 810c28cc2660b73e03e4d27be97988fc5321a06f +Author: Alex Deucher +Date: Fri Jul 11 15:31:57 2008 -0400 + + Make sure cursor offsets are properly aligned when using EXA + +commit 7e67d0163579a44f104e8f354a929ac9b33e4c21 +Author: Alex Deucher +Date: Fri Jul 11 14:30:17 2008 -0400 + + Fix cursor with multi-head and rotation + +commit 9086d008fb8c3cde0633b90ce19ffbf4eded388d +Author: Alex Deucher +Date: Tue Jul 8 09:57:04 2008 -0400 + + Add quirk for Falcon NW laptop + +commit 61f82ace0210251beb0bcc492218a75a193e1deb +Author: Benjamin Herrenschmidt +Date: Tue Jul 8 21:58:43 2008 +1000 + + atombios: add support for other endians. + + This is a cleaned up (in as much as atombios can be..) of benh's patch. + + airlied - removed benh's debugging for now, it might need to be put back later.. + +commit b4d1a47b5c6eafda5e274398eebe2701b030f22e +Author: Dave Airlie +Date: Tue Jul 8 11:09:01 2008 +1000 + + rv770 initial support + + adds pci ids and one register from AMD code + +commit 7ae4cec8cc8c90aee5dc4fa7abcce22321d4f4eb +Author: Roland Scheidegger +Date: Mon Jul 7 14:39:47 2008 -0400 + + clamp tex coords (r100/r200) for textured video + + fixes bug 14904 + +commit 879f9a37856642b337e3c0233e38fd5443338eef +Author: Alex Deucher +Date: Fri Jul 4 13:54:49 2008 -0400 + + Revert "rotate: fix rotation in conf file." + + This reverts commit 22c6ca0d5d226c725ba448e5db63fdba9e32332c. + + There seems to be an ordering issue in that causes a nasty hang + if the DRI is enabled. This needs more investigation. + +commit 22c6ca0d5d226c725ba448e5db63fdba9e32332c +Author: Dave Airlie +Date: Thu Jul 3 20:14:59 2008 +1000 + + rotate: fix rotation in conf file. + + need to set modes after init accel architecture + + reported-by: Christoph Bartoschek + +commit ce1a3edd52b647744cfa4433301befb437d211bb +Author: Dave Airlie +Date: Thu Jul 3 20:05:54 2008 +1000 + + radeon: drop all use of CPMode. + + We never test the other codepath and I don't think I've ever recommended it + for anyone. + +commit c037b4ce8769ad840a257e22b1e4ad58b8ed96fa +Author: Wolke Liu +Date: Tue Jul 1 10:45:39 2008 -0400 + + Add pci id for FireMV 2400 + +commit 72992668ca96717bf69bcea95a5deeaf7c57e826 +Author: Alex Deucher +Date: Mon Jun 30 14:09:09 2008 -0400 + + RS4xx: enable the DRI by default on all variants + + Some RS4xx chips had the DRI disabled by default. + With the recent drm and ddx changes these chips have been + reported to work now with the DRI. + +commit 0378c8ed88c829f09b5c6d51314325eaf2685fdb +Author: Michel Dänzer +Date: Sat Jun 28 14:06:45 2008 +0200 + + Restore versioning of interface for Mesa DRI driver. + + This doesn't have anything to do with the package version. + +commit cfaa23d925e3c062cf87ea844566ac11ea02d69e +Author: Alex Deucher +Date: Fri Jun 27 20:36:54 2008 -0400 + + RADEON: IGP VGA fixes take 2 + + It seems only RS300/350/400/480 are missing the primary dac + See bug 15708 + +commit 31c27ffcb3c4c5334cf726ecd4e293a678b2a1ea +Author: Alex Deucher +Date: Fri Jun 27 20:29:04 2008 -0400 + + Revert "IGP: attempt to fix VGA on IGP chips" + + This reverts commit e78e8a21b4040cd7f1983c241c860d9209398396. + +commit af79a77e6d8206b18bba97cf4e0770921dc439a7 +Author: Brice Goglin +Date: Fri Jun 27 17:09:13 2008 +0200 + + use PACKAGE_VERSION_* for radeon version + + now radeon shows verion 6.9.0 instead of 4.3.0. + + RADEON_VERSION_MAJOR_TILED is dropped from ddxDriverMajorVersion + since RADEON_VERSION_MAJOR is bigger now. +diff --git a/configure.ac b/configure.ac +index b8c18a6..5ffe0d9 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -72,7 +72,6 @@ XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto) + XORG_DRIVER_CHECK_EXT(RANDR, randrproto) + XORG_DRIVER_CHECK_EXT(RENDER, renderproto) + XORG_DRIVER_CHECK_EXT(XV, videoproto) +-XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto) + XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) + + # Checks for pkg-config packages diff --git a/man/radeon.man b/man/radeon.man -index 03622a0..68029ed 100644 +index 03622a0..f8526df 100644 --- a/man/radeon.man +++ b/man/radeon.man -@@ -283,7 +283,8 @@ The default value is - .BI "Option \*qEnablePageFlip\*q \*q" boolean \*q +@@ -13,14 +13,44 @@ radeon \- ATI RADEON video driver + .fi + .SH DESCRIPTION + .B radeon +-is an __xservername__ driver for ATI RADEON based video cards. It contains +-full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup, +-flat panel, hardware 2D acceleration, hardware 3D acceleration, hardware cursor, +-XV extension, and the Xinerama extension. ++is an __xservername__ driver for ATI RADEON based video cards with the ++following features: ++.PP ++.PD 0 ++.TP 2 ++\(bu ++Full support for 8, 15, 16 and 24 bit pixel depths; ++.TP ++\(bu ++RandR 1.2 and RandR 1.3 support; ++.TP ++\(bu ++TV Out support (only on R/RV/RS1xx, R/RV/RS2xx, R/RV/RS3xx); ++.TP ++\(bu ++Full EXA 2D acceleration (not supported on R/RV6xx and R/RV/RS7xx); ++.TP ++\(bu ++Full XAA 2D acceleration (not supported on R/RV6xx and R/RV/RS7xx. XAA Render ++acceleration supported only on R/RV100, R/RV/RS2xx and RS300); ++.TP ++\(bu ++Textured XVideo acceleration (not supported on R/RV6xx and R/RV/RS7xx. ++Bicubic filtering only available on R/RV3xx, R/RV/RS4xx, R/RV5xx, and RS690); ++.TP ++\(bu ++Overlay XVideo acceleration (only on R/RV/RS1xx, R/RV/RS2xx, ++R/RV/RS3xx, R/RV/RS4xx); ++.TP ++\(bu ++3D acceleration (not supported on R/RV6xx and R/RV/RS7xx); ++.PD + .SH SUPPORTED HARDWARE + The + .B radeon +-driver supports PCI and AGP video cards based on the following ATI chips ++driver supports PCI, AGP, and PCIE video cards based on the following ATI chips: ++.PP ++.PD 0 + .TP 12 + .B R100 + Radeon 7200 +@@ -103,8 +133,8 @@ Radeon X1600/X1650/X1700 + .B RV570/R580 + Radeon X1900/X1950 + .TP 12 +-.B RS600/RS690 +-Radeon X1200 ++.B RS600/RS690/RS740 ++Radeon X1200, X2100 + .TP 12 + .B R600 + Radeon HD 2900 +@@ -119,8 +149,11 @@ Radeon HD 3850/3870 + Radeon HD 3450/3470 + .TP 12 + .B RS780 +-Radeon HD 3200 +- ++Radeon HD 3100/3200/3300 ++.TP 12 ++.B RV770 ++Radeon HD 4850/4870 ++.PD + .SH CONFIGURATION DETAILS + Please refer to __xconfigfile__(__filemansuffix__) for general configuration + details. This section only covers configuration details specific to this +@@ -221,12 +254,6 @@ PCIE \-\- PCI Express (falls back to PCI at present) + .br + The default is + .B auto detect. +-.TP +-.BI "Option \*qDDCMode\*q \*q" boolean \*q +-Force to use the modes queried from the connected monitor. +-.br +-The default is +-.B off. + .TP + .BI "Option \*qDisplayPriority\*q \*q" string \*q + .br +@@ -249,9 +276,7 @@ The default value is + Frame buffer can be addressed either in linear or tiled mode. Tiled mode can provide + significant performance benefits with 3D applications, for 2D it shouldn't matter + much. Tiling will be disabled if the virtual x resolution exceeds 2048 (3968 for R300 +-and above), if option +-.B UseFBDev +-is used, or (if DRI is enabled) the drm module is too old. ++and above), or if DRI is enabled the drm module is too old. + .br + If this option is enabled, a new dri driver is required for direct rendering too. + .br +@@ -271,7 +296,7 @@ The default value is + Should only be used when driver cannot detect the correct panel size. + Apply to both desktop (TMDS) and laptop (LVDS) digital panels. + When a valid panel size is specified, the timings collected from +-DDC and BIOS will not be used. If you have a panel with timings ++DDC and BIOS will not be used. If you have a panel with timings + different from that of a standard VESA mode, you have to provide + this information through the Modeline. + .br +@@ -284,6 +309,7 @@ The default value is Enable page flipping for 3D acceleration. This will increase performance but not work correctly in some rare cases, hence the default is --.B off. -+.B off. -+It is currently only supported on r4xx and older hardware. + .B off. ++It is currently only supported on R/RV/RS4xx and older hardware. .TP .BI "Option \*qForceMinDotClock\*q \*q" frequency \*q Override minimum dot clock. Some Radeon BIOSes report a minimum dot -@@ -297,10 +298,9 @@ parameter may be specified as a float value with standard suffixes like +@@ -297,10 +323,9 @@ parameter may be specified as a float value with standard suffixes like "k", "kHz", "M", "MHz". .TP .BI "Option \*qRenderAccel\*q \*q" boolean \*q @@ -20,14 +1626,131 @@ index 03622a0..68029ed 100644 -support component alpha (subpixel) rendering. It is only supported on -Radeon series up to and including 9200 (9500/9700 and newer -unsupported). The default is to -+Enables or disables hardware Render acceleration. It is supported on -+Radeon series up to and including r5xx for EXA and up to and -+including r2xx for XAA. The default is to ++Enables or disables hardware Render acceleration. It is supported on all ++Radeon cards when using EXA acceleration and on Radeon R/RV/RS1xx, ++R/RV/RS2xx and RS300 when usig XAA. The default is to .B enable Render acceleration. .TP +@@ -369,7 +394,7 @@ This option is intended to be used in following cases: + .br + 3. Adjust to one display type in dual-head clone mode setup. + .br +-4. Get better performance with Render acceleration on ++4. Get better performance with Render acceleration on + digital panels (use NONE setting). + .br + The default is +@@ -379,8 +404,8 @@ for CRT, + for digital panels + .TP + .BI "Option \*qDynamicClocks\*q \*q" boolean \*q +-Enable dynamic clock scaling. The on-chip clocks will scale dynamically +-based on usage. This can help reduce heat and increase battery ++Enable dynamic clock scaling. The on-chip clocks will scale dynamically ++based on usage. This can help reduce heat and increase battery + life by reducing power usage. Some users report reduced 3D performance + with this enabled. The default is + .B off. +@@ -398,7 +423,7 @@ on other architectures. + .TP + .BI "Option \*qReverseDDC\*q \*q" boolean \*q + When BIOS connector informations aren't available, use this option to +-reverse the mapping of the 2 main DDC ports. Use this if the X serve ++reverse the mapping of the 2 main DDC ports. Use this if the X server + obviously detects the wrong display for each connector. This is + typically needed on the Radeon 9600 cards bundled with Apple G5s. The + default is +@@ -414,30 +439,30 @@ The default is + .B on. + .TP + .BI "Option \*qTVDACLoadDetect\*q \*q" boolean \*q +-Enable load detection on the TV DAC. The TV DAC is used to drive both +-TV-OUT and analog monitors. Load detection is often unreliable in the ++Enable load detection on the TV DAC. The TV DAC is used to drive both ++TV-OUT and analog monitors. Load detection is often unreliable in the + TV DAC so it is disabled by default. + The default is + .B off. + .TP + .BI "Option \*qDefaultTMDSPLL\*q \*q" boolean \*q + Use the default driver provided TMDS PLL values rather than the ones +-provided by the bios. This option has no effect on Mac cards. Enable +-this option if you are having problems with a DVI monitor using the ++provided by the bios. This option has no effect on Mac cards. Enable ++this option if you are having problems with a DVI monitor using the + internal TMDS controller. + The default is + .B off. + .TP + .BI "Option \*qDefaultTVDACAdj\*q \*q" boolean \*q + Use the default driver provided TVDAC Adj values rather than the ones +-provided by the bios. This option has no effect on Mac cards. Enable +-this option if you are having problems with a washed out display on ++provided by the bios. This option has no effect on Mac cards. Enable ++this option if you are having problems with a washed out display on + the secondary DAC. + The default is + .B off. + .TP + .BI "Option \*qDRI\*q \*q" boolean \*q +-Enable DRI support. This option allows you to enable to disable the DRI. ++Enable DRI support. This option allows you to enable to disable the DRI. + The default is + .B off + for RN50/ES1000 and +@@ -446,7 +471,7 @@ for others. + .TP + .BI "Option \*qDefaultConnectorTable\*q \*q" boolean \*q + Enable this option to skip the BIOS connector table parsing and use the +-driver defaults for each chip. ++driver defaults for each chip. + The default is + .B off + .TP +@@ -454,8 +479,8 @@ The default is + .br + Used to specify Mac models for connector tables and quirks. If you have + a powerbook or mini with DVI that does not work properly, try the alternate +- options as Apple does not seem to provide a good way of knowing whether +- they use internal or external TMDS for DVI. Only valid on PowerPC. ++options as Apple does not seem to provide a good way of knowing whether ++they use internal or external TMDS for DVI. Only valid on PowerPC. + .br + ibook \-\- ibooks + .br +@@ -477,6 +502,8 @@ mini \-\- mini-external alias + .br + imac-g5-isight \-\- iMac G5 iSight + .br ++emac \-\- eMac G4 ++.br + The default value is + .B undefined. + .TP +@@ -512,11 +539,17 @@ The default is + .B on. + .TP + .BI "Option \*qInt10\*q \*q" boolean \*q +-This option allows you to disable int10 initialization. Set this to ++This option allows you to disable int10 initialization. Set this to + False if you are experiencing a hang when initializing a secondary card. + The default is +-.B on. +-.TP ++.B on. ++.TP ++.BI "Option \*qEXAVSync\*q \*q" boolean \*q ++This option attempts to avoid tearing by stalling the engine until the display ++controller has passed the destination region. It reduces tearing at the cost ++of performance. ++The default is ++.B off. + + .SH SEE ALSO + __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c -index 509aa0c..58c4ae9 100644 +index 509aa0c..6b28560 100644 --- a/src/AtomBios/CD_Operations.c +++ b/src/AtomBios/CD_Operations.c @@ -44,7 +44,6 @@ Revision History: @@ -141,7 +1864,22 @@ index 509aa0c..58c4ae9 100644 } else { SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); -@@ -664,7 +668,8 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ +@@ -614,7 +618,13 @@ VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); +- pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]); ++ ++ if (pParserTempData->ParametersType.Destination == 0 && ++ pParserTempData->Multipurpose.CurrentPort == ATI_RegsPort && ++ pParserTempData->Index == 0) { ++ pParserTempData->DestData32 = 0; ++ } else ++ pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]); + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); + + } +@@ -664,7 +674,8 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; @@ -151,7 +1889,7 @@ index 509aa0c..58c4ae9 100644 { if (*pParserTempData->pWorkingTableData->IP == 'c') { -@@ -673,7 +678,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ +@@ -673,7 +684,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ pParserTempData->Index=GetParametersDirect16(pParserTempData); if (pParserTempData->SourceData32 == pParserTempData->DestData32) { @@ -160,7 +1898,7 @@ index 509aa0c..58c4ae9 100644 return; } } -@@ -695,7 +700,7 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -695,7 +706,7 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) } else { pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); @@ -169,7 +1907,7 @@ index 509aa0c..58c4ae9 100644 } } pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -@@ -704,13 +709,13 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -704,13 +715,13 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) { pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; @@ -185,7 +1923,7 @@ index 509aa0c..58c4ae9 100644 pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); } -@@ -754,19 +759,23 @@ VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -754,19 +765,23 @@ VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) { @@ -213,7 +1951,7 @@ index 509aa0c..58c4ae9 100644 pParserTempData->pDeviceData->pParameterSpace+= pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; pParserTempData->Status=CD_CALL_TABLE; -@@ -792,7 +801,7 @@ VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -792,7 +807,7 @@ VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) { @@ -222,7 +1960,7 @@ index 509aa0c..58c4ae9 100644 } else { pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -@@ -805,7 +814,7 @@ VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -805,7 +820,7 @@ VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) { @@ -231,7 +1969,7 @@ index 509aa0c..58c4ae9 100644 } else { pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -@@ -817,7 +826,7 @@ VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -817,7 +832,7 @@ VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) if (pParserTempData->CompareFlags != Equal) { @@ -2320,7 +4058,7 @@ index 5333495..d65a3e4 100644 ativersion.h \ generic_bus.h \ diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index a740df8..633c5d3 100644 +index a740df8..6f23628 100644 --- a/src/ati_pciids_gen.h +++ b/src/ati_pciids_gen.h @@ -1,4 +1,5 @@ @@ -2329,26 +4067,86 @@ index a740df8..633c5d3 100644 #define PCI_CHIP_RV380_3152 0x3152 #define PCI_CHIP_RV380_3154 0x3154 #define PCI_CHIP_RV380_3E50 0x3E50 -@@ -330,6 +331,9 @@ +@@ -330,6 +331,27 @@ #define PCI_CHIP_R600_940A 0x940A #define PCI_CHIP_R600_940B 0x940B #define PCI_CHIP_R600_940F 0x940F +#define PCI_CHIP_RV770_9440 0x9440 +#define PCI_CHIP_RV770_9441 0x9441 +#define PCI_CHIP_RV770_9442 0x9442 ++#define PCI_CHIP_RV770_9444 0x9444 ++#define PCI_CHIP_RV770_9446 0x9446 ++#define PCI_CHIP_RV770_944A 0x944A ++#define PCI_CHIP_RV770_944B 0x944B ++#define PCI_CHIP_RV770_944C 0x944C ++#define PCI_CHIP_RV770_944E 0x944E ++#define PCI_CHIP_RV770_9450 0x9450 ++#define PCI_CHIP_RV770_9452 0x9452 ++#define PCI_CHIP_RV770_9456 0x9456 ++#define PCI_CHIP_RV770_945A 0x945A ++#define PCI_CHIP_RV770_945B 0x945B ++#define PCI_CHIP_RV730_9487 0x9487 ++#define PCI_CHIP_RV730_948F 0x948F ++#define PCI_CHIP_RV730_9490 0x9490 ++#define PCI_CHIP_RV730_9498 0x9498 ++#define PCI_CHIP_RV730_949C 0x949C ++#define PCI_CHIP_RV730_949E 0x949E ++#define PCI_CHIP_RV730_949F 0x949F #define PCI_CHIP_RV610_94C0 0x94C0 #define PCI_CHIP_RV610_94C1 0x94C1 #define PCI_CHIP_RV610_94C3 0x94C3 -@@ -347,6 +351,7 @@ +@@ -347,6 +369,13 @@ #define PCI_CHIP_RV670_9507 0x9507 #define PCI_CHIP_RV670_950F 0x950F #define PCI_CHIP_RV670_9511 0x9511 +#define PCI_CHIP_RV670_9515 0x9515 ++#define PCI_CHIP_RV710_9540 0x9540 ++#define PCI_CHIP_RV710_9541 0x9541 ++#define PCI_CHIP_RV710_954E 0x954E ++#define PCI_CHIP_RV710_954F 0x954F ++#define PCI_CHIP_RV710_9552 0x9552 ++#define PCI_CHIP_RV710_9553 0x9553 #define PCI_CHIP_RV630_9580 0x9580 #define PCI_CHIP_RV630_9581 0x9581 #define PCI_CHIP_RV630_9583 0x9583 +@@ -359,11 +388,12 @@ + #define PCI_CHIP_RV630_958C 0x958C + #define PCI_CHIP_RV630_958D 0x958D + #define PCI_CHIP_RV630_958E 0x958E ++#define PCI_CHIP_RV710_9592 0x9592 + #define PCI_CHIP_RV620_95C0 0x95C0 +-#define PCI_CHIP_RV620_95C5 0x95C5 +-#define PCI_CHIP_RV620_95C7 0x95C7 + #define PCI_CHIP_RV620_95C2 0x95C2 + #define PCI_CHIP_RV620_95C4 0x95C4 ++#define PCI_CHIP_RV620_95C5 0x95C5 ++#define PCI_CHIP_RV620_95C7 0x95C7 + #define PCI_CHIP_RV620_95CD 0x95CD + #define PCI_CHIP_RV620_95CE 0x95CE + #define PCI_CHIP_RV620_95CF 0x95CF +@@ -378,3 +408,4 @@ + #define PCI_CHIP_RS780_9611 0x9611 + #define PCI_CHIP_RS780_9612 0x9612 + #define PCI_CHIP_RS780_9613 0x9613 ++#define PCI_CHIP_RS780_9614 0x9614 +diff --git a/src/atipciids.h b/src/atipciids.h +index f24f8fb..7735e93 100644 +--- a/src/atipciids.h ++++ b/src/atipciids.h +@@ -35,8 +35,11 @@ + + /* PCI Vendor */ + #define PCI_VENDOR_ATI 0x1002 ++#define PCI_VENDOR_IBM 0x1014 + #define PCI_VENDOR_AMD 0x1022 + #define PCI_VENDOR_DELL 0x1028 ++#define PCI_VENDOR_VIA 0x1106 ++#define PCI_VENDOR_INTEL 0x8086 + + #include "ati_pciids_gen.h" + diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c -index 363addf..4e2395f 100644 +index 363addf..93bf94f 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -43,11 +43,33 @@ @@ -2425,7 +4223,11 @@ index 363addf..4e2395f 100644 if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ErrorF("Set CRTC Timing success\n"); -@@ -185,7 +224,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) +@@ -182,10 +221,15 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) + unsigned char *space; + RADEONSavePtr save = info->ModeReg; + ++ memset(&spc_param, 0, sizeof(spc_param)); if (IS_AVIVO_VARIANT) { uint32_t temp; @@ -2438,7 +4240,7 @@ index 363addf..4e2395f 100644 RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); sclock = temp; -@@ -235,9 +278,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) +@@ -235,9 +279,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) case 1: case 2: spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput; @@ -2451,7 +4253,7 @@ index 363addf..4e2395f 100644 spc2_ptr->ucPostDiv = post_div; spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; spc2_ptr->ucCRTC = radeon_crtc->crtc_id; -@@ -246,9 +289,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) +@@ -246,9 +290,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) break; case 3: spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput; @@ -2464,7 +4266,7 @@ index 363addf..4e2395f 100644 spc3_ptr->ucPostDiv = post_div; spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); -@@ -442,9 +485,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -442,43 +486,40 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; } @@ -2474,7 +4276,18 @@ index 363addf..4e2395f 100644 OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); -@@ -459,26 +499,27 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, + + OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); + OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); +- OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x); +- OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y); +- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + mode->HDisplay); +- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + mode->VDisplay); ++ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX); ++ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY); + OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, crtc->scrn->displayWidth); OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); @@ -2484,8 +4297,9 @@ index 363addf..4e2395f 100644 - /* lock the mode regs */ - OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); - - OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, - mode->VDisplay); +- OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, +- mode->VDisplay); ++ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay); OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay); @@ -2638,10 +4452,19 @@ index 363addf..4e2395f 100644 + +} diff --git a/src/atombios_output.c b/src/atombios_output.c -index 51be301..148a1da 100644 +index 51be301..396af31 100644 --- a/src/atombios_output.c +++ b/src/atombios_output.c -@@ -78,7 +78,7 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -43,6 +43,8 @@ + #include "radeon_macros.h" + #include "radeon_atombios.h" + ++#include "ati_pciids_gen.h" ++ + static int + atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode) + { +@@ -78,7 +80,7 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode) } } @@ -2650,7 +4473,7 @@ index 51be301..148a1da 100644 data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); data.exec.dataSpace = (void *)&space; data.exec.pspace = &disp_data; -@@ -128,7 +128,7 @@ atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -128,7 +130,7 @@ atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode) } } @@ -2659,7 +4482,7 @@ index 51be301..148a1da 100644 data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); data.exec.dataSpace = (void *)&space; data.exec.pspace = &disp_data; -@@ -188,7 +188,7 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -188,7 +190,7 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) } } @@ -2668,7 +4491,7 @@ index 51be301..148a1da 100644 data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); data.exec.dataSpace = (void *)&space; data.exec.pspace = &disp_data; -@@ -206,7 +206,8 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -206,7 +208,8 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) { @@ -2678,7 +4501,7 @@ index 51be301..148a1da 100644 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data; AtomBiosArgRec data; unsigned char *space; -@@ -218,7 +219,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -218,7 +221,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) else disp_data.sXTmdsEncoder.ucMisc = 0; @@ -2687,7 +4510,7 @@ index 51be301..148a1da 100644 disp_data.sXTmdsEncoder.ucMisc |= (1 << 1); data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); -@@ -243,7 +244,7 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -243,7 +246,7 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) unsigned char *space; disp_data.sDVOEncoder.ucAction = ATOM_ENABLE; @@ -2696,7 +4519,7 @@ index 51be301..148a1da 100644 if (mode->Clock > 165000) disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; -@@ -264,84 +265,109 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) +@@ -264,214 +267,169 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) } static int @@ -2747,7 +4570,8 @@ index 51be301..148a1da 100644 - return ATOM_NOT_IMPLEMENTED; - -} -- ++ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); + -static int -atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode) -{ @@ -2755,21 +4579,6 @@ index 51be301..148a1da 100644 - TMDS2_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; -- -- disp_data.ucAction = 1; -- if (mode->Clock > 165000) -- disp_data.ucMisc = 1; -- else -- disp_data.ucMisc = 0; -- disp_data.usPixelClock = mode->Clock / 10; -- data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); -- data.exec.dataSpace = (void *)&space; -- data.exec.pspace = &disp_data; -+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - -- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -- ErrorF("Output TMDS2 setup success\n"); -- return ATOM_SUCCESS; + /*ErrorF("table is %d %d\n", major, minor);*/ + switch (major) { + case 0: @@ -2806,6 +4615,7 @@ index 51be301..148a1da 100644 + } + if (radeon_output->type == OUTPUT_HDMI) + disp_data2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; ++ disp_data2.usPixelClock = cpu_to_le16(mode->Clock / 10); + disp_data2.ucTruncate = 0; + disp_data2.ucSpatial = 0; + disp_data2.ucTemporal = 0; @@ -2833,15 +4643,34 @@ index 51be301..148a1da 100644 + break; + } + break; ++ } + +- disp_data.ucAction = 1; +- if (mode->Clock > 165000) +- disp_data.ucMisc = 1; +- else +- disp_data.ucMisc = 0; +- disp_data.usPixelClock = mode->Clock / 10; +- data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); ++ data.exec.index = index; + data.exec.dataSpace = (void *)&space; +- data.exec.pspace = &disp_data; + + if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { +- ErrorF("Output TMDS2 setup success\n"); ++ ErrorF("Output digital setup success\n"); + return ATOM_SUCCESS; } - ErrorF("Output TMDS2 setup failed\n"); -- return ATOM_NOT_IMPLEMENTED; --} -- --static int ++ ErrorF("Output digital setup failed\n"); + return ATOM_NOT_IMPLEMENTED; + } + + static int -atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode) --{ ++atombios_maybe_hdmi_mode(xf86OutputPtr output) + { - RADEONInfoPtr info = RADEONPTR(output->scrn); - LVDS_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; @@ -2854,58 +4683,389 @@ index 51be301..148a1da 100644 - disp_data.ucMisc = 0; - disp_data.usPixelClock = mode->Clock / 10; - data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); +- data.exec.dataSpace = (void *)&space; +- data.exec.pspace = &disp_data; +- +- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { +- ErrorF("Output LVDS setup success\n"); +- return ATOM_SUCCESS; +- } +- +- ErrorF("Output LVDS setup failed\n"); +- return ATOM_NOT_IMPLEMENTED; ++#ifndef EDID_COMPLETE_RAWDATA ++ /* there's no getting this right unless we have complete EDID */ ++ return ATOM_ENCODER_MODE_HDMI; ++#else ++ if (output && xf86MonitorIsHDMI(output->MonInfo)) ++ return ATOM_ENCODER_MODE_HDMI; ++ ++ return ATOM_ENCODER_MODE_DVI; ++#endif + } + + static int +-atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode) ++atombios_output_dig_encoder_setup(xf86OutputPtr output, int device, DisplayModePtr mode) + { + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(output->scrn); + DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data; + AtomBiosArgRec data; + unsigned char *space; ++ int index; ++ int major, minor; + +- disp_data.ucAction = 1; +- disp_data.usPixelClock = mode->Clock / 10; +- disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; +- if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { +- if (radeon_output->coherent_mode) { +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; +- xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG1: Coherent Mode enabled\n"); +- } else +- xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG1: Coherent Mode disabled\n"); +- } +- +- if (mode->Clock > 165000) { +- disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; +- disp_data.ucLaneNum = 8; +- } else { +- disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; +- disp_data.ucLaneNum = 4; +- } +- +- if (OUTPUT_IS_DVI) +- disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DVI; +- else if (radeon_output->type == OUTPUT_HDMI) +- disp_data.ucEncoderMode = ATOM_ENCODER_MODE_HDMI; +- else if (radeon_output->type == OUTPUT_DP) +- disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DP; +- else if (radeon_output->type == OUTPUT_LVDS) +- disp_data.ucEncoderMode = ATOM_ENCODER_MODE_LVDS; +- +- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); +- data.exec.dataSpace = (void *)&space; +- data.exec.pspace = &disp_data; +- +- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { +- ErrorF("Output DIG1 setup success\n"); +- return ATOM_SUCCESS; +- } +- +- ErrorF("Output DIG1 setup failed\n"); +- return ATOM_NOT_IMPLEMENTED; +- +-} ++ if (radeon_crtc->crtc_id) ++ index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); ++ else ++ index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); + +-static int +-atombios_output_dig1_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) +-{ +- RADEONOutputPrivatePtr radeon_output = output->driver_private; +- RADEONInfoPtr info = RADEONPTR(output->scrn); +- DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data; +- AtomBiosArgRec data; +- unsigned char *space; ++ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); + +- disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; +- disp_data.usPixelClock = mode->Clock / 10; +- disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; ++ disp_data.ucAction = ATOM_ENABLE; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + +- if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { +- if (mode->Clock > 165000) { +- disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | +- ATOM_TRANSMITTER_CONFIG_LINKA_B); +- /* guess */ +- if (radeon_output->igp_lane_info & 0x3) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; +- else if (radeon_output->igp_lane_info & 0xc) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; +- } else { +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; +- if (radeon_output->igp_lane_info & 0x1) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; +- else if (radeon_output->igp_lane_info & 0x2) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; +- else if (radeon_output->igp_lane_info & 0x4) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; +- else if (radeon_output->igp_lane_info & 0x8) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; +- } ++ if (IS_DCE32_VARIANT) { ++ if (radeon_output->TMDSType == TMDS_UNIPHY) ++ disp_data.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; ++ if (radeon_output->TMDSType == TMDS_UNIPHY1) ++ disp_data.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; ++ if (radeon_output->TMDSType == TMDS_UNIPHY2) ++ disp_data.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; + } else { +- if (mode->Clock > 165000) +- disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | +- ATOM_TRANSMITTER_CONFIG_LINKA_B | +- ATOM_TRANSMITTER_CONFIG_LANE_0_7); +- else +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; +- } +- +- radeon_output->transmitter_config = disp_data.ucConfig; +- +- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); +- data.exec.dataSpace = (void *)&space; +- data.exec.pspace = &disp_data; +- +- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { +- ErrorF("Output DIG1 transmitter setup success\n"); +- return ATOM_SUCCESS; +- } +- +- ErrorF("Output DIG1 transmitter setup failed\n"); +- return ATOM_NOT_IMPLEMENTED; +- +-} +- +-static int +-atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode) +-{ +- RADEONOutputPrivatePtr radeon_output = output->driver_private; +- RADEONInfoPtr info = RADEONPTR(output->scrn); +- DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data; +- AtomBiosArgRec data; +- unsigned char *space; +- +- disp_data.ucAction = 1; +- disp_data.usPixelClock = mode->Clock / 10; +- disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; +- if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { +- if (radeon_output->coherent_mode) { +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; +- xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG2: Coherent Mode enabled\n"); +- } else +- xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG2: Coherent Mode disabled\n"); ++ switch (device) { ++ case ATOM_DEVICE_DFP1_INDEX: ++ disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; ++ break; ++ case ATOM_DEVICE_LCD1_INDEX: ++ case ATOM_DEVICE_DFP3_INDEX: ++ disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ break; ++ } + } + + if (mode->Clock > 165000) { +@@ -485,80 +443,164 @@ atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode) + if (OUTPUT_IS_DVI) + disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DVI; + else if (radeon_output->type == OUTPUT_HDMI) +- disp_data.ucEncoderMode = ATOM_ENCODER_MODE_HDMI; ++ disp_data.ucEncoderMode = atombios_maybe_hdmi_mode(output); + else if (radeon_output->type == OUTPUT_DP) + disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DP; + else if (radeon_output->type == OUTPUT_LVDS) + disp_data.ucEncoderMode = ATOM_ENCODER_MODE_LVDS; + +- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); + data.exec.index = index; data.exec.dataSpace = (void *)&space; -- data.exec.pspace = &disp_data; + data.exec.pspace = &disp_data; if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -- ErrorF("Output LVDS setup success\n"); -+ ErrorF("Output digital setup success\n"); +- ErrorF("Output DIG2 setup success\n"); ++ ErrorF("Output DIG%d encoder setup success\n", radeon_crtc->crtc_id + 1); return ATOM_SUCCESS; } -- ErrorF("Output LVDS setup failed\n"); -+ ErrorF("Output digital setup failed\n"); +- ErrorF("Output DIG2 setup failed\n"); ++ ErrorF("Output DIG%d setup failed\n", radeon_crtc->crtc_id + 1); return ATOM_NOT_IMPLEMENTED; + } -@@ -355,7 +381,7 @@ atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode) ++union dig_transmitter_control { ++ DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; ++ DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; ++}; ++ + static int +-atombios_output_dig2_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) ++atombios_output_dig_transmitter_setup(xf86OutputPtr output, int device, DisplayModePtr mode) + { + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(output->scrn); +- DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data; ++ union dig_transmitter_control disp_data; + AtomBiosArgRec data; unsigned char *space; ++ int index, num = 0; ++ int major, minor; - disp_data.ucAction = 1; +- disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; - disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; - if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { - if (radeon_output->coherent_mode) { -@@ -406,7 +432,7 @@ atombios_output_dig1_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode - unsigned char *space; +- disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; ++ memset(&disp_data,0, sizeof(disp_data)); ++ if (IS_DCE32_VARIANT) ++ index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); ++ else { ++ switch (device) { ++ case ATOM_DEVICE_DFP1_INDEX: ++ index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); ++ num = 1; ++ break; ++ case ATOM_DEVICE_LCD1_INDEX: ++ case ATOM_DEVICE_DFP3_INDEX: ++ index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); ++ num = 2; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ break; ++ } ++ } - disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; +- if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { ++ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); ++ ++ disp_data.v1.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; ++ ++ if (IS_DCE32_VARIANT) { + if (mode->Clock > 165000) { +- disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | +- ATOM_TRANSMITTER_CONFIG_LINKA_B); +- /* guess */ +- if (radeon_output->igp_lane_info & 0x3) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; +- else if (radeon_output->igp_lane_info & 0xc) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; ++ disp_data.v2.usPixelClock = cpu_to_le16((mode->Clock * 10 * 2) / 100); ++ disp_data.v2.acConfig.fDualLinkConnector = 1; + } else { +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; +- if (radeon_output->igp_lane_info & 0x1) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; +- else if (radeon_output->igp_lane_info & 0x2) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; +- else if (radeon_output->igp_lane_info & 0x4) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; +- else if (radeon_output->igp_lane_info & 0x8) +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; ++ disp_data.v2.usPixelClock = cpu_to_le16((mode->Clock * 10 * 4) / 100); ++ } ++ if (radeon_crtc->crtc_id) ++ disp_data.v2.acConfig.ucEncoderSel = 1; ++ ++ switch (radeon_output->TMDSType) { ++ case TMDS_UNIPHY: ++ disp_data.v2.acConfig.ucTransmitterSel = 0; ++ num = 0; ++ break; ++ case TMDS_UNIPHY1: ++ disp_data.v2.acConfig.ucTransmitterSel = 1; ++ num = 1; ++ break; ++ case TMDS_UNIPHY2: ++ disp_data.v2.acConfig.ucTransmitterSel = 2; ++ num = 2; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ break; ++ } ++ ++ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { ++ if (radeon_output->coherent_mode) { ++ disp_data.v2.acConfig.fCoherentMode = 1; ++ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "UNIPHY%d transmitter: Coherent Mode enabled\n",disp_data.v2.acConfig.ucTransmitterSel); ++ } else ++ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "UNIPHY%d transmitter: Coherent Mode disabled\n",disp_data.v2.acConfig.ucTransmitterSel); + } + } else { +- if (mode->Clock > 165000) +- disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | +- ATOM_TRANSMITTER_CONFIG_LINKA_B | +- ATOM_TRANSMITTER_CONFIG_LANE_0_7); ++ disp_data.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; ++ disp_data.v1.usPixelClock = cpu_to_le16((mode->Clock) / 10); ++ ++ if (radeon_crtc->crtc_id) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; + else +- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; ++ ++ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { ++ if (radeon_output->coherent_mode) { ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; ++ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG%d transmitter: Coherent Mode enabled\n", num); ++ } else ++ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG%d transmitter: Coherent Mode disabled\n", num); ++ } ++ ++ if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { ++ if (mode->Clock > 165000) { ++ disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | ++ ATOM_TRANSMITTER_CONFIG_LINKA_B); ++ /* guess */ ++ if (radeon_output->igp_lane_info & 0x3) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; ++ else if (radeon_output->igp_lane_info & 0xc) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; ++ } else { ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; ++ if (radeon_output->igp_lane_info & 0x1) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; ++ else if (radeon_output->igp_lane_info & 0x2) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; ++ else if (radeon_output->igp_lane_info & 0x4) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; ++ else if (radeon_output->igp_lane_info & 0x8) ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; ++ } ++ } else { ++ if (mode->Clock > 165000) ++ disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | ++ ATOM_TRANSMITTER_CONFIG_LINKA_B | ++ ATOM_TRANSMITTER_CONFIG_LANE_0_7); ++ else ++ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; ++ } + } - if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { -@@ -464,7 +490,7 @@ atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode) - unsigned char *space; +- radeon_output->transmitter_config = disp_data.ucConfig; +- +- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); ++ radeon_output->transmitter_config = disp_data.v1.ucConfig; ++ ++ data.exec.index = index; + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; - disp_data.ucAction = 1; -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; - if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { - if (radeon_output->coherent_mode) { -@@ -515,7 +541,7 @@ atombios_output_dig2_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode - unsigned char *space; + if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { +- ErrorF("Output DIG2 transmitter setup success\n"); ++ if (IS_DCE32_VARIANT) ++ ErrorF("Output UNIPHY%d transmitter setup success\n", num); ++ else ++ ErrorF("Output DIG%d transmitter setup success\n", num); + return ATOM_SUCCESS; + } - disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; +- ErrorF("Output DIG2 transmitter setup failed\n"); ++ ErrorF("Output DIG%d transmitter setup failed\n", num); + return ATOM_NOT_IMPLEMENTED; - if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { -@@ -600,34 +626,6 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) + } +@@ -600,34 +642,6 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) } @@ -2940,20 +5100,194 @@ index 51be301..148a1da 100644 static AtomBiosResult atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state) { -@@ -920,10 +918,8 @@ atombios_output_mode_set(xf86OutputPtr output, +@@ -677,10 +691,16 @@ atombios_device_dpms(xf86OutputPtr output, int device, int mode) + index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); + break; + case ATOM_DEVICE_TV1_SUPPORT: +- index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); ++ if (IS_DCE3_VARIANT) ++ index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); ++ else ++ index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); + break; + case ATOM_DEVICE_CV_SUPPORT: +- index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); ++ if (IS_DCE3_VARIANT) ++ index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); ++ else ++ index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); + break; + default: + return; +@@ -707,6 +727,7 @@ atombios_output_dig_dpms(xf86OutputPtr output, int mode, int block) + AtomBiosArgRec data; + unsigned char *space; + ++ memset(&disp_data, 0, sizeof(disp_data)); + switch (mode) { + case DPMSModeOn: + disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT; +@@ -720,10 +741,15 @@ atombios_output_dig_dpms(xf86OutputPtr output, int mode, int block) + + disp_data.ucConfig = radeon_output->transmitter_config; + +- if (block == 1) +- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); +- else +- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); ++ if (IS_DCE32_VARIANT) { ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); ++ } ++ else { ++ if (block == 1) ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); ++ else ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); ++ } + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; + +@@ -760,15 +786,21 @@ atombios_output_dpms(xf86OutputPtr output, int mode) + else + atombios_device_dpms(output, ATOM_DEVICE_DFP1_SUPPORT, mode); + } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) { +- if (IS_DCE3_VARIANT) ++ if (IS_DCE32_VARIANT) ++ atombios_output_dig_dpms(output, mode, 2); ++ else if (IS_DCE3_VARIANT) + return; // fixme + else + atombios_device_dpms(output, ATOM_DEVICE_DFP2_SUPPORT, mode); + } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) { + if (IS_DCE3_VARIANT) +- atombios_output_dig_dpms(output, mode, 2); ++ atombios_output_dig_dpms(output, mode, 0); + else + atombios_device_dpms(output, ATOM_DEVICE_DFP3_SUPPORT, mode); ++ } else if (radeon_output->devices & ATOM_DEVICE_DFP4_SUPPORT) { ++ atombios_output_dig_dpms(output, mode, 1); ++ } else if (radeon_output->devices & ATOM_DEVICE_DFP5_SUPPORT) { ++ atombios_output_dig_dpms(output, mode, 2); + } + } else if (radeon_output->MonType == MT_CRT) { + /*ErrorF("AGD: dac dpms\n");*/ +@@ -802,6 +834,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) + int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); + int major, minor; + ++ memset(&crtc_src_param, 0, sizeof(crtc_src_param)); ++ memset(&crtc_src_param2, 0, sizeof(crtc_src_param2)); + atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); + + /*ErrorF("select crtc source table is %d %d\n", major, minor);*/ +@@ -826,6 +860,10 @@ atombios_set_output_crtc_source(xf86OutputPtr output) + crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX; + else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) + crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_DFP4_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_DFP4_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_DFP5_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_DFP5_INDEX; + } else if (radeon_output->MonType == MT_LCD) { + if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) + crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX; +@@ -842,22 +880,31 @@ atombios_set_output_crtc_source(xf86OutputPtr output) + case 2: + crtc_src_param2.ucCRTC = radeon_crtc->crtc_id; + if (radeon_output->MonType == MT_CRT) { ++ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; + if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) +- crtc_src_param2.ucEncoderID = ATOM_DEVICE_CRT1_INDEX; ++ crtc_src_param2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; + else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) +- crtc_src_param2.ucEncoderID = ATOM_DEVICE_CRT2_INDEX; +- crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; ++ crtc_src_param2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; + } else if (radeon_output->MonType == MT_DFP) { +- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) +- crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP1_INDEX; +- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) +- crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP2_INDEX; +- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) +- crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP3_INDEX; ++ if (IS_DCE3_VARIANT) { ++ /* we route digital encoders using the CRTC ids */ ++ if (radeon_crtc->crtc_id) ++ crtc_src_param2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; ++ else ++ crtc_src_param2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; ++ } else { ++ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) ++ crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP1_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) ++ crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP2_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) ++ crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP3_INDEX; ++ } + if (OUTPUT_IS_DVI) + crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_DVI; + else if (radeon_output->type == OUTPUT_HDMI) +- crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_HDMI; ++ crtc_src_param2.ucEncodeMode = ++ atombios_maybe_hdmi_mode(output); + else if (radeon_output->type == OUTPUT_DP) + crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_DP; + } else if (radeon_output->MonType == MT_LCD) { +@@ -896,6 +943,30 @@ atombios_set_output_crtc_source(xf86OutputPtr output) + return; + } + ++static void ++atombios_apply_output_quirks(xf86OutputPtr output) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ /* Funky macbooks */ ++ if ((info->Chipset == PCI_CHIP_RV530_71C5) && ++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x106b) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0080)) { ++ if (radeon_output->MonType == MT_LCD) { ++ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) { ++ uint32_t lvtma_bit_depth_control = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); ++ ++ lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; ++ lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; ++ ++ OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); ++ } ++ } ++ } ++} ++ + void + atombios_output_mode_set(xf86OutputPtr output, + DisplayModePtr mode, +@@ -918,15 +989,14 @@ atombios_output_mode_set(xf86OutputPtr output, + } else if (radeon_output->MonType == MT_DFP) { + if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) { if (IS_DCE3_VARIANT) { - atombios_output_dig1_setup(output, adjusted_mode); - atombios_output_dig1_transmitter_setup(output, adjusted_mode); +- atombios_output_dig1_setup(output, adjusted_mode); +- atombios_output_dig1_transmitter_setup(output, adjusted_mode); - } else { - atombios_output_tmds1_setup(output, adjusted_mode); - dfp_disable_dither(output, ATOM_DEVICE_DFP1_SUPPORT); - } ++ atombios_output_dig_encoder_setup(output, ATOM_DEVICE_DFP1_INDEX, adjusted_mode); ++ atombios_output_dig_transmitter_setup(output, ATOM_DEVICE_DFP1_INDEX, adjusted_mode); + } else + atombios_output_digital_setup(output, ATOM_DEVICE_DFP1_INDEX, adjusted_mode); } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) { - if (IS_DCE3_VARIANT) { - // fix me -@@ -934,26 +930,21 @@ atombios_output_mode_set(xf86OutputPtr output, +- if (IS_DCE3_VARIANT) { +- // fix me ++ if (IS_DCE32_VARIANT) { ++ atombios_output_dig_encoder_setup(output, ATOM_DEVICE_DFP2_INDEX, adjusted_mode); ++ atombios_output_dig_transmitter_setup(output, ATOM_DEVICE_DFP2_INDEX, adjusted_mode); + } else { + if ((info->ChipFamily == CHIP_FAMILY_RS600) || + (info->ChipFamily == CHIP_FAMILY_RS690) || +@@ -934,26 +1004,27 @@ atombios_output_mode_set(xf86OutputPtr output, atombios_output_ddia_setup(output, adjusted_mode); else atombios_external_tmds_setup(output, adjusted_mode); @@ -2961,30 +5295,49 @@ index 51be301..148a1da 100644 } } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) { if (IS_DCE3_VARIANT) { - atombios_output_dig2_setup(output, adjusted_mode); - atombios_output_dig2_transmitter_setup(output, adjusted_mode); +- atombios_output_dig2_setup(output, adjusted_mode); +- atombios_output_dig2_transmitter_setup(output, adjusted_mode); - } else { - atombios_output_tmds2_setup(output, adjusted_mode); - dfp_disable_dither(output, ATOM_DEVICE_DFP3_SUPPORT); - } ++ atombios_output_dig_encoder_setup(output, ATOM_DEVICE_DFP3_INDEX, adjusted_mode); ++ atombios_output_dig_transmitter_setup(output, ATOM_DEVICE_DFP3_INDEX, adjusted_mode); + } else + atombios_output_digital_setup(output, ATOM_DEVICE_DFP3_INDEX, adjusted_mode); ++ } else if (radeon_output->devices & ATOM_DEVICE_DFP4_SUPPORT) { ++ atombios_output_dig_encoder_setup(output, ATOM_DEVICE_DFP4_INDEX, adjusted_mode); ++ atombios_output_dig_transmitter_setup(output, ATOM_DEVICE_DFP4_INDEX, adjusted_mode); ++ } else if (radeon_output->devices & ATOM_DEVICE_DFP5_SUPPORT) { ++ atombios_output_dig_encoder_setup(output, ATOM_DEVICE_DFP5_INDEX, adjusted_mode); ++ atombios_output_dig_transmitter_setup(output, ATOM_DEVICE_DFP5_INDEX, adjusted_mode); } } else if (radeon_output->MonType == MT_LCD) { if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) { if (IS_DCE3_VARIANT) { - atombios_output_dig2_setup(output, adjusted_mode); - atombios_output_dig2_transmitter_setup(output, adjusted_mode); +- atombios_output_dig2_setup(output, adjusted_mode); +- atombios_output_dig2_transmitter_setup(output, adjusted_mode); - } else { - atombios_output_lvds_setup(output, adjusted_mode); - dfp_disable_dither(output, ATOM_DEVICE_LCD1_SUPPORT); - } ++ atombios_output_dig_encoder_setup(output, ATOM_DEVICE_LCD1_INDEX, adjusted_mode); ++ atombios_output_dig_transmitter_setup(output, ATOM_DEVICE_LCD1_INDEX, adjusted_mode); + } else + atombios_output_digital_setup(output, ATOM_DEVICE_LCD1_INDEX, adjusted_mode); } } else if ((radeon_output->MonType == MT_CTV) || (radeon_output->MonType == MT_STV) || -@@ -979,19 +970,19 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) +@@ -964,7 +1035,7 @@ atombios_output_mode_set(xf86OutputPtr output, + atombios_output_dac2_setup(output, adjusted_mode); + atombios_output_tv1_setup(output, adjusted_mode); + } +- ++ atombios_apply_output_quirks(output); + } + + static AtomBiosResult +@@ -979,19 +1050,19 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) dac_data.sDacload.ucMisc = 0; if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { @@ -3007,7 +5360,7 @@ index 51be301..148a1da 100644 if (radeon_output->DACType == DAC_PRIMARY) dac_data.sDacload.ucDacType = ATOM_DAC_A; else if (radeon_output->DACType == DAC_TVDAC) -@@ -999,7 +990,7 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) +@@ -999,7 +1070,7 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) if (IS_DCE3_VARIANT) dac_data.sDacload.ucMisc = 1; } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { @@ -3747,7 +6100,7 @@ index 0000000..232ccb7 +maketable(512) +maketable(2048) diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c -index 3df61a7..75ab6c8 100644 +index 3df61a7..78ac5b3 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -48,8 +48,7 @@ @@ -3760,7 +6113,71 @@ index 3df61a7..75ab6c8 100644 #include "sarea.h" #ifdef DRM_IOCTL_MODESET_CTL #include -@@ -624,11 +623,17 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) +@@ -104,6 +103,31 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, + } + } + ++void ++RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, ++ RADEONSavePtr restore) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ if (IS_R300_VARIANT) ++ OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0); ++ OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); ++ OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset); ++} ++ ++void ++RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, ++ RADEONSavePtr restore) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ if (IS_R300_VARIANT) ++ OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0); ++ OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); ++ OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset); ++} + + /* Write CRTC registers */ + void +@@ -134,10 +158,7 @@ RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, + OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp); + OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid); + +- if (IS_R300_VARIANT) +- OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0); +- OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); +- OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset); ++ RADEONRestoreCrtcBase(pScrn, restore); + + OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); + OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); +@@ -181,10 +202,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, + OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid); + OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid); + +- if (IS_R300_VARIANT) +- OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0); +- OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); +- OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset); ++ RADEONRestoreCrtc2Base(pScrn, restore); + + OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); + OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); +@@ -554,6 +572,7 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) + save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); + save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); + save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); ++ + save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET); + save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); + save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH); +@@ -624,11 +643,17 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) RADEONInfoPtr info = RADEONPTR(crtc->scrn); RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; struct drm_modeset_ctl modeset; @@ -3779,7 +6196,17 @@ index 3df61a7..75ab6c8 100644 #endif } -@@ -752,13 +757,13 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -743,8 +768,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) + + } + +- +-static Bool ++void + RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, + int x, int y) + { +@@ -752,13 +776,13 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, RADEONInfoPtr info = RADEONPTR(pScrn); int Base; #ifdef XF86DRI @@ -3795,7 +6222,7 @@ index 3df61a7..75ab6c8 100644 save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; else #endif -@@ -851,7 +856,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -851,14 +875,12 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, pSAREA->frame.height = pScrn->frameY1 - y + 1; if (pSAREAPriv->pfCurrentPage == 1) { @@ -3804,7 +6231,23 @@ index 3df61a7..75ab6c8 100644 } } #endif -@@ -970,7 +975,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, + save->crtc_offset = Base; + +- return TRUE; +- + } + + /* Define CRTC registers for requested video mode */ +@@ -962,7 +984,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + } + + +-static Bool ++void + RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, + int x, int y) + { +@@ -970,7 +992,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, RADEONInfoPtr info = RADEONPTR(pScrn); int Base; #ifdef XF86DRI @@ -3813,7 +6256,7 @@ index 3df61a7..75ab6c8 100644 XF86DRISAREAPtr pSAREA; #endif -@@ -978,7 +983,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -978,7 +1000,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, */ save->crtc2_offset = pScrn->fbOffset; #ifdef XF86DRI @@ -3822,7 +6265,7 @@ index 3df61a7..75ab6c8 100644 save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; else #endif -@@ -1065,7 +1070,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -1065,13 +1087,12 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, pSAREAPriv->crtc2_base = Base; if (pSAREAPriv->pfCurrentPage == 1) { @@ -3831,7 +6274,13 @@ index 3df61a7..75ab6c8 100644 } } #endif -@@ -1327,9 +1332,12 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) + save->crtc2_offset = Base; + +- return TRUE; + } + + +@@ -1327,9 +1348,12 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) } /* Calculate display buffer watermark to prevent buffer underflow */ @@ -3846,7 +6295,7 @@ index 3df61a7..75ab6c8 100644 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; -@@ -1352,10 +1360,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1352,10 +1376,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 float min_mem_eff = 0.8; float sclk_eff, sclk_delay; float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; @@ -3859,7 +6308,7 @@ index 3df61a7..75ab6c8 100644 int stop_req, max_stop_req; float read_return_rate, time_disp1_drop_priority; -@@ -1366,15 +1374,15 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1366,15 +1390,15 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 */ if ((info->DispPriority == 2) && IS_R300_VARIANT) { uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); @@ -3881,7 +6330,7 @@ index 3df61a7..75ab6c8 100644 /* R420 and RV410 family not supported yet */ if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; -@@ -1383,15 +1391,17 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1383,15 +1407,17 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 */ mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); @@ -3907,7 +6356,7 @@ index 3df61a7..75ab6c8 100644 if (peak_disp_bw >= mem_bw * min_mem_eff) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -@@ -1399,20 +1409,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1399,20 +1425,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); } @@ -3928,7 +6377,7 @@ index 3df61a7..75ab6c8 100644 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ temp = INREG(RADEON_MEM_TIMING_CNTL); if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ -@@ -1435,9 +1431,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1435,9 +1447,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 } if (IS_R300_VARIANT) { @@ -3939,7 +6388,7 @@ index 3df61a7..75ab6c8 100644 temp = INREG(RADEON_MEM_CNTL); data = (R300_MEM_NUM_CHANNELS_MASK & temp); if (data == 1) { -@@ -1467,13 +1462,14 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1467,13 +1478,14 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 } else { #ifdef XF86DRI if (info->directRenderingEnabled) @@ -3956,7 +6405,7 @@ index 3df61a7..75ab6c8 100644 */ if (IS_R300_VARIANT) { /*not enough for R350 ???*/ -@@ -1527,89 +1523,107 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1527,89 +1539,107 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); @@ -4130,7 +6579,7 @@ index 3df61a7..75ab6c8 100644 temp = info->SavedReg->grph2_buffer_cntl; temp &= ~(RADEON_GRPH_STOP_REQ_MASK); temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); -@@ -1629,7 +1643,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1629,7 +1659,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 critical_point2 = 0; else { read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); @@ -4142,7 +6591,7 @@ index 3df61a7..75ab6c8 100644 critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + disp_latency) * disp_drain_rate2 + 0.5); -@@ -1681,45 +1698,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1681,45 +1714,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 } void @@ -4188,7 +6637,7 @@ index 3df61a7..75ab6c8 100644 legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode, int x, int y) { -@@ -1729,10 +1707,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -1729,10 +1723,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, RADEONInfoPtr info = RADEONPTR(pScrn); int i = 0; double dot_clock = 0; @@ -4206,7 +6655,7 @@ index 3df61a7..75ab6c8 100644 radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; tilingChanged = RADEONSetTiling(pScrn); diff --git a/src/legacy_output.c b/src/legacy_output.c -index 9c9ebb9..e5ddf1f 100644 +index 9c9ebb9..f9b0dff 100644 --- a/src/legacy_output.c +++ b/src/legacy_output.c @@ -48,6 +48,8 @@ @@ -4274,7 +6723,37 @@ index 9c9ebb9..e5ddf1f 100644 } } else if (radeon_output->MonType == MT_DFP) { if (radeon_output->TMDSType == TMDS_INT) { -@@ -1033,9 +1016,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, +@@ -964,12 +947,19 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + + save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); + ++ save->fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | ++ RADEON_FP_DFP_SYNC_SEL | ++ RADEON_FP_CRT_SYNC_SEL | ++ RADEON_FP_CRTC_LOCK_8DOT | ++ RADEON_FP_USE_SHADOW_EN | ++ RADEON_FP_CRTC_USE_SHADOW_VEND | ++ RADEON_FP_CRT_SYNC_ALT); ++ + if (pScrn->rgbBits == 8) + save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ + else + save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ + +- + if (IsPrimary) { + if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { + save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; +@@ -978,7 +968,7 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + else + save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; + } else +- save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1; ++ save->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; + } else { + if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { + save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; +@@ -1033,9 +1023,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, RADEON_FP2_DVO_RATE_SEL_SDR); @@ -4291,7 +6770,26 @@ index 9c9ebb9..e5ddf1f 100644 #if 0 if (mode->Clock > 165000) save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN; -@@ -1383,7 +1371,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, +@@ -1049,16 +1044,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; + else + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; +- } else { ++ } else + save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; +- } + } else { + if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { + save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; +- } else { ++ } else + save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; +- } + } + + if ((info->ChipFamily == CHIP_FAMILY_RS400) || +@@ -1383,7 +1376,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, { Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE; RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -4299,7 +6797,7 @@ index 9c9ebb9..e5ddf1f 100644 if (crtc_num == 0) RADEONInitRMXRegisters(output, save, mode); -@@ -1393,9 +1380,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, +@@ -1393,9 +1385,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, RADEONInitDACRegisters(output, save, mode, IsPrimary); } else { RADEONInitDAC2Registers(output, save, mode, IsPrimary); @@ -4309,7 +6807,7 @@ index 9c9ebb9..e5ddf1f 100644 } } else if (radeon_output->MonType == MT_LCD) { RADEONInitLVDSRegisters(output, save, mode, IsPrimary); -@@ -1456,8 +1440,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, +@@ -1456,8 +1445,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, } OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); } else { @@ -4320,7 +6818,7 @@ index 9c9ebb9..e5ddf1f 100644 } break; diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index 1f6fa82..07e71a3 100644 +index 1f6fa82..aea0931 100644 --- a/src/pcidb/ati_pciids.csv +++ b/src/pcidb/ati_pciids.csv @@ -1,5 +1,6 @@ @@ -4330,26 +6828,99 @@ index 1f6fa82..07e71a3 100644 "0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)" "0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)" "0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)" -@@ -331,6 +332,9 @@ +@@ -307,7 +308,7 @@ + "0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT" + "0x7289","RV570_7289","RV570",,,,,,"ATI RV570" + "0x728B","RV570_728B","RV570",,,,,,"ATI RV570" +-"0x728C","RV570_728C","RV570",,,,,,"ATI ATI FireGL V7400" ++"0x728C","RV570_728C","RV570",,,,,,"ATI FireGL V7400" + "0x7290","RV560_7290","RV560",,,,,,"ATI RV560" + "0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650" + "0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650" +@@ -331,13 +332,34 @@ "0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650" "0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600" "0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600" +"0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series" +"0x9441","RV770_9441","RV770",,,,,,"ATI Radeon HD 4870 x2" +"0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series" ++"0x9444","RV770_9444","RV770",,,,,,"ATI FirePro V8750 (FireGL)" ++"0x9446","RV770_9446","RV770",,,,,,"ATI FirePro V7760 (FireGL)" ++"0x944A","RV770_944A","RV770",1,,,,,"ATI Mobility RADEON HD 4850" ++"0x944B","RV770_944B","RV770",1,,,,,"ATI Mobility RADEON HD 4850 X2" ++"0x944C","RV770_944C","RV770",,,,,,"ATI Radeon 4800 Series" ++"0x944E","RV770_944E","RV770",,,,,,"ATI FirePro RV770" ++"0x9450","RV770_9450","RV770",,,,,,"AMD FireStream 9270" ++"0x9452","RV770_9452","RV770",,,,,,"AMD FireStream 9250" ++"0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)" ++"0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870" ++"0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98" ++"0x9487","RV730_9487","RV730",,,,,,"ATI Radeon RV730 (AGP)" ++"0x948F","RV730_948F","RV730",,,,,,"ATI Radeon RV730 (AGP)" ++"0x9490","RV730_9490","RV730",,,,,,"ATI RV730XT [Radeon HD 4670]" ++"0x9498","RV730_9498","RV730",,,,,,"ATI RV730 PRO [Radeon HD 4650]" ++"0x949C","RV730_949C","RV730",,,,,,"ATI FirePro V7750 (FireGL)" ++"0x949E","RV730_949E","RV730",,,,,,"ATI FirePro V5700 (FireGL)" ++"0x949F","RV730_949F","RV730",,,,,,"ATI FirePro V3750 (FireGL)" "0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" "0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" "0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" -@@ -348,6 +352,7 @@ + "0x94C4","RV610_94C4","RV610",,,,,,"ATI Radeon HD 2400 PRO AGP" + "0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000" + "0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610" +-"0x94C7","RV610_94C7","RV610",,,,,,"ATI ATI Radeon HD 2350" ++"0x94C7","RV610_94C7","RV610",,,,,,"ATI Radeon HD 2350" + "0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT" + "0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400" + "0x94CB","RV610_94CB","RV610",1,,,,,"ATI RADEON E2400" +@@ -348,6 +370,13 @@ "0x9507","RV670_9507","RV670",,,,,,"ATI RV670" "0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" "0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" +"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850" ++"0x9540","RV710_9540","RV710",,,,,,"ATI Radeon HD 4550" ++"0x9541","RV710_9541","RV710",,,,,,"ATI Radeon RV710" ++"0x954E","RV710_954E","RV710",,,,,,"ATI Radeon RV710" ++"0x954F","RV710_954F","RV710",,,,,,"ATI Radeon HD 4350" ++"0x9552","RV710_9552","RV710",1,,,,,"ATI Mobility Radeon 4300 Series" ++"0x9553","RV710_9553","RV710",1,,,,,"ATI Mobility Radeon 4500 Series" "0x9580","RV630_9580","RV630",,,,,,"ATI RV630" "0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" "0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" +@@ -360,22 +389,24 @@ + "0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600" + "0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" + "0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE" ++"0x9592","RV710_9592","RV710",,,,,,"ATI Radeon RV710" + "0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470" +-"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450" +-"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430" + "0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430" + "0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series" ++"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450" ++"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430" + "0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450" + "0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260" + "0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260" +-"0x9590","RV635_9590","RV635",,,,,,"ATI ATI Radeon HD 3600 Series" +-"0x9596","RV635_9596","RV635",,,,,,"ATI ATI Radeon HD 3650 AGP" +-"0x9597","RV635_9597","RV635",,,,,,"ATI ATI Radeon HD 3600 PRO" +-"0x9598","RV635_9598","RV635",,,,,,"ATI ATI Radeon HD 3600 XT" +-"0x9599","RV635_9599","RV635",,,,,,"ATI ATI Radeon HD 3600 PRO" ++"0x9590","RV635_9590","RV635",,,,,,"ATI Radeon HD 3600 Series" ++"0x9596","RV635_9596","RV635",,,,,,"ATI Radeon HD 3650 AGP" ++"0x9597","RV635_9597","RV635",,,,,,"ATI Radeon HD 3600 PRO" ++"0x9598","RV635_9598","RV635",,,,,,"ATI Radeon HD 3600 XT" ++"0x9599","RV635_9599","RV635",,,,,,"ATI Radeon HD 3600 PRO" + "0x9591","RV635_9591","RV635",1,,,,,"ATI Mobility Radeon HD 3650" + "0x9593","RV635_9593","RV635",1,,,,,"ATI Mobility Radeon HD 3670" + "0x9610","RS780_9610","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" + "0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics" + "0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" + "0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" ++"0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics" diff --git a/src/radeon.h b/src/radeon.h -index 4f77c3b..f7ae1a8 100644 +index 4f77c3b..a67962c 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -72,9 +72,10 @@ @@ -4401,6 +6972,24 @@ index 4f77c3b..f7ae1a8 100644 /* Provide substitutes for gcc's __FUNCTION__ on other compilers */ #if !defined(__GNUC__) && !defined(__FUNCTION__) # define __FUNCTION__ __func__ /* C99 */ +@@ -134,7 +165,6 @@ typedef enum { + OPTION_ACCEL_DFS, + #endif + #endif +- OPTION_DDC_MODE, + OPTION_IGNORE_EDID, + OPTION_DISP_PRIORITY, + OPTION_PANEL_SIZE, +@@ -174,7 +204,8 @@ typedef enum { + OPTION_TVSTD, + OPTION_IGNORE_LID_STATUS, + OPTION_DEFAULT_TVDAC_ADJ, +- OPTION_INT10 ++ OPTION_INT10, ++ OPTION_EXA_VSYNC + } RADEONOpts; + + @@ -220,7 +251,12 @@ typedef struct { #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) @@ -4415,15 +7004,36 @@ index 4f77c3b..f7ae1a8 100644 typedef struct { uint16_t reference_freq; -@@ -287,6 +323,7 @@ typedef enum { +@@ -287,6 +323,9 @@ typedef enum { CHIP_FAMILY_RV620, CHIP_FAMILY_RV635, CHIP_FAMILY_RS780, + CHIP_FAMILY_RV770, ++ CHIP_FAMILY_RV730, ++ CHIP_FAMILY_RV710, CHIP_FAMILY_LAST } RADEONChipFamily; -@@ -377,156 +414,45 @@ typedef struct { +@@ -312,6 +351,8 @@ typedef enum { + + #define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) + ++#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) ++ + #define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ + (info->ChipFamily == CHIP_FAMILY_R520) || \ + (info->ChipFamily == CHIP_FAMILY_RV530) || \ +@@ -355,7 +396,8 @@ typedef enum { + RADEON_MAC_POWERBOOK_VGA, + RADEON_MAC_MINI_EXTERNAL, + RADEON_MAC_MINI_INTERNAL, +- RADEON_MAC_IMAC_G5_ISIGHT ++ RADEON_MAC_IMAC_G5_ISIGHT, ++ RADEON_MAC_EMAC + } RADEONMacModel; + #endif + +@@ -377,156 +419,45 @@ typedef struct { int singledac; } RADEONCardInfo; @@ -4610,7 +7220,7 @@ index 4f77c3b..f7ae1a8 100644 Bool newMemoryMap; drmVersionPtr pLibDRMVersion; drmVersionPtr pKernelDRMVersion; -@@ -542,7 +468,6 @@ typedef struct { +@@ -542,7 +473,6 @@ typedef struct { drmSize registerSize; drm_handle_t registerHandle; @@ -4618,7 +7228,7 @@ index 4f77c3b..f7ae1a8 100644 drmSize pciSize; drm_handle_t pciMemHandle; unsigned char *PCI; /* Map */ -@@ -564,15 +489,7 @@ typedef struct { +@@ -564,15 +494,7 @@ typedef struct { uint32_t pciCommand; @@ -4635,7 +7245,7 @@ index 4f77c3b..f7ae1a8 100644 unsigned long ringStart; /* Offset into GART space */ drm_handle_t ringHandle; /* Handle from drmAddMap */ drmSize ringMapSize; /* Size of map */ -@@ -585,7 +502,7 @@ typedef struct { +@@ -585,7 +507,7 @@ typedef struct { drmSize ringReadMapSize; /* Size of map */ drmAddress ringReadPtr; /* Map */ @@ -4644,7 +7254,7 @@ index 4f77c3b..f7ae1a8 100644 unsigned long bufStart; /* Offset into GART space */ drm_handle_t bufHandle; /* Handle from drmAddMap */ drmSize bufMapSize; /* Size of map */ -@@ -594,7 +511,7 @@ typedef struct { +@@ -594,7 +516,7 @@ typedef struct { int bufNumBufs; /* Number of buffers */ drmBufMapPtr buffers; /* Buffer map */ @@ -4653,7 +7263,7 @@ index 4f77c3b..f7ae1a8 100644 unsigned long gartTexStart; /* Offset into GART space */ drm_handle_t gartTexHandle; /* Handle from drmAddMap */ drmSize gartTexMapSize; /* Size of map */ -@@ -602,11 +519,7 @@ typedef struct { +@@ -602,11 +524,7 @@ typedef struct { drmAddress gartTex; /* Map */ int log2GARTTexGran; @@ -4666,7 +7276,7 @@ index 4f77c3b..f7ae1a8 100644 int fbX; int fbY; int backX; -@@ -628,43 +541,215 @@ typedef struct { +@@ -628,43 +546,217 @@ typedef struct { int pciGartSize; uint32_t pciGartOffset; void *pciGartBackup; @@ -4736,6 +7346,8 @@ index 4f77c3b..f7ae1a8 100644 + /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ + Bool src_tile_width; + Bool src_tile_height; ++ ++ Bool vsync; +#endif + +#ifdef USE_XAA @@ -4762,7 +7374,9 @@ index 4f77c3b..f7ae1a8 100644 + uint32_t dashPattern; + int dash_fg; + int dash_bg; -+ + +- uint32_t re_top_left; +- uint32_t re_width_height; + FBLinearPtr RenderTex; + void (*RenderCallback)(ScrnInfoPtr); + Time RenderTimeout; @@ -4772,11 +7386,11 @@ index 4f77c3b..f7ae1a8 100644 + */ + Bool XAAForceTransBlit; +#endif -+ + +- uint32_t aux_sc_cntl; +}; -- uint32_t re_top_left; -- uint32_t re_width_height; +- int irq; +typedef struct { + EntityInfoPtr pEnt; + pciVideoPtr PciInfo; @@ -4784,36 +7398,34 @@ index 4f77c3b..f7ae1a8 100644 + int Chipset; + RADEONChipFamily ChipFamily; + RADEONErrata ChipErrata; -+ -+ unsigned long LinearAddr; /* Frame buffer physical address */ -+ unsigned long MMIOAddr; /* MMIO region physical address */ -+ unsigned long BIOSAddr; /* BIOS physical address */ + +- Bool DMAForXv; ++ unsigned long long LinearAddr; /* Frame buffer physical address */ ++ unsigned long long MMIOAddr; /* MMIO region physical address */ ++ unsigned long long BIOSAddr; /* BIOS physical address */ + uint32_t fbLocation; + uint32_t gartLocation; + uint32_t mc_fb_location; + uint32_t mc_agp_location; + uint32_t mc_agp_location_hi; -- uint32_t aux_sc_cntl; +-#ifdef PER_CONTEXT_SAREA +- int perctx_sarea_size; + void *MMIO; /* Map of MMIO region */ + void *FB; /* Map of frame buffer */ + uint8_t *VBIOS; /* Video BIOS pointer */ - -- int irq; ++ + Bool IsAtomBios; /* New BIOS used in R420 etc. */ + int ROMHeaderStart; /* Start of the ROM Info Table */ + int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ - -- Bool DMAForXv; ++ + uint32_t MemCntl; + uint32_t BusCntl; + unsigned long MMIOSize; /* MMIO region physical address */ + unsigned long FbMapSize; /* Size of frame buffer, in bytes */ + unsigned long FbSecureSize; /* Size of secured fb area at end of + framebuffer */ - --#ifdef PER_CONTEXT_SAREA -- int perctx_sarea_size; ++ + Bool IsMobility; /* Mobile chips for laptops */ + Bool IsIGP; /* IGP chips */ + Bool HasSingleDAC; /* only TVDAC on chip */ @@ -4899,7 +7511,7 @@ index 4f77c3b..f7ae1a8 100644 /* XVideo */ XF86VideoAdaptorPtr adaptor; void (*VideoTimerCallback)(ScrnInfoPtr, Time); -@@ -693,31 +778,10 @@ typedef struct { +@@ -693,31 +785,10 @@ typedef struct { int overlay_scaler_buffer_width; int ecp_div; @@ -4931,12 +7543,15 @@ index 4f77c3b..f7ae1a8 100644 DisplayModePtr currentMode, savedCurrentMode; /* special handlings for DELL triple-head server */ -@@ -772,22 +836,19 @@ typedef struct { +@@ -772,22 +843,22 @@ typedef struct { Bool r600_shadow_fb; void *fb_shadow; - int num_gb_pipes; - Bool has_tcl; ++ /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ ++ Bool get_hardcoded_edid_from_bios; ++ } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ @@ -4956,7 +7571,15 @@ index 4f77c3b..f7ae1a8 100644 extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, -@@ -872,6 +933,7 @@ extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output); +@@ -865,19 +936,24 @@ extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); + extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); + extern Bool RADEONGetDAC2InfoFromBIOS(xf86OutputPtr output); + extern Bool RADEONGetExtTMDSInfoFromBIOS(xf86OutputPtr output); +-extern Bool RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); ++extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); + extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); + extern Bool RADEONGetLVDSInfoFromBIOS(xf86OutputPtr output); + extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output); extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); @@ -4964,7 +7587,17 @@ index 4f77c3b..f7ae1a8 100644 /* radeon_commonfuncs.c */ #ifdef XF86DRI -@@ -894,6 +956,7 @@ extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, + extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); ++extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, ++ int crtc, int start, int stop, int enable); + #endif + extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); ++extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, ++ int crtc, int start, int stop, int enable); + + /* radeon_crtc.c */ + extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); +@@ -894,6 +970,7 @@ extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode); extern void RADEONUnblank(ScrnInfoPtr pScrn); extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); @@ -4972,7 +7605,7 @@ index 4f77c3b..f7ae1a8 100644 /* radeon_cursor.c */ extern Bool RADEONCursorInit(ScreenPtr pScreen); -@@ -983,6 +1046,8 @@ extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); +@@ -983,6 +1060,8 @@ extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); extern void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output); extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); @@ -4981,7 +7614,7 @@ index 4f77c3b..f7ae1a8 100644 /* radeon_tv.c */ extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -@@ -1003,6 +1068,16 @@ extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); +@@ -1003,6 +1082,16 @@ extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); extern void RADEONInitVideo(ScreenPtr pScreen); extern void RADEONResetVideo(ScrnInfoPtr pScrn); @@ -4998,7 +7631,7 @@ index 4f77c3b..f7ae1a8 100644 #ifdef XF86DRI # ifdef USE_XAA /* radeon_accelfuncs.c */ -@@ -1011,72 +1086,58 @@ extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); +@@ -1011,72 +1100,58 @@ extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); #define RADEONCP_START(pScrn, info) \ do { \ @@ -5083,7 +7716,7 @@ index 4f77c3b..f7ae1a8 100644 } \ } while (0) -@@ -1100,33 +1161,33 @@ do { \ +@@ -1100,33 +1175,33 @@ do { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ } \ @@ -5131,7 +7764,7 @@ index 4f77c3b..f7ae1a8 100644 } \ if (__count != __expected) { \ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ -@@ -1136,11 +1197,11 @@ do { \ +@@ -1136,11 +1211,11 @@ do { \ if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "ADVANCE_RING() start: %d used: %d count: %d\n", \ @@ -5146,7 +7779,7 @@ index 4f77c3b..f7ae1a8 100644 } while (0) #define OUT_RING(x) do { \ -@@ -1162,7 +1223,7 @@ do { \ +@@ -1162,7 +1237,7 @@ do { \ if (RADEON_VERBOSE) \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "FLUSH_RING in %s\n", __FUNCTION__); \ @@ -5155,7 +7788,51 @@ index 4f77c3b..f7ae1a8 100644 RADEONCPFlushIndirect(pScrn, 0); \ } \ } while (0) -@@ -1236,19 +1297,19 @@ static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) +@@ -1228,6 +1303,43 @@ do { \ + + #endif /* XF86DRI */ + ++#if defined(XF86DRI) && defined(USE_EXA) ++#define RADEON_SWITCH_TO_2D() \ ++do { \ ++ uint32_t flush = 0; \ ++ switch (info->accel_state->engineMode) { \ ++ case EXA_ENGINEMODE_UNKNOWN: \ ++ case EXA_ENGINEMODE_3D: \ ++ flush = 1; \ ++ case EXA_ENGINEMODE_2D: \ ++ break; \ ++ } \ ++ if (flush && info->directRenderingEnabled) \ ++ RADEONCPFlushIndirect(pScrn, 1); \ ++ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ ++} while (0); ++ ++#define RADEON_SWITCH_TO_3D() \ ++do { \ ++ uint32_t flush = 0; \ ++ switch (info->accel_state->engineMode) { \ ++ case EXA_ENGINEMODE_UNKNOWN: \ ++ case EXA_ENGINEMODE_2D: \ ++ flush = 1; \ ++ case EXA_ENGINEMODE_3D: \ ++ break; \ ++ } \ ++ if (flush && info->directRenderingEnabled) { \ ++ RADEONCPFlushIndirect(pScrn, 1); \ ++ RADEONInit3DEngine(pScrn); \ ++ } \ ++ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ ++} while (0); ++#else ++#define RADEON_SWITCH_TO_2D() ++#define RADEON_SWITCH_TO_3D() ++#endif ++ + static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) + { + #ifdef USE_EXA +@@ -1236,19 +1348,19 @@ static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) #endif #ifdef USE_XAA if (!info->useEXA) @@ -5180,7 +7857,7 @@ index 4f77c3b..f7ae1a8 100644 } diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 65ad33d..a6e332d 100644 +index 65ad33d..2f62fa5 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -83,9 +83,7 @@ @@ -5206,7 +7883,26 @@ index 65ad33d..a6e332d 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "FIFO timed out: %u entries, stat=0x%08x\n", -@@ -324,8 +322,8 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) +@@ -158,6 +156,9 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) + unsigned char *RADEONMMIO = info->MMIO; + int i; + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return; ++ + if (info->ChipFamily <= CHIP_FAMILY_RV280) { + OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT, + RADEON_RB3D_DC_FLUSH_ALL, +@@ -197,6 +198,8 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + uint32_t rbbm_soft_reset; + uint32_t host_path_cntl; + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return; + /* The following RBBM_SOFT_RESET sequence can help un-wedge + * an R300 after the command processor got stuck. + */ +@@ -324,8 +327,8 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) * in the wrong place (happened). */ RADEONWaitForFifo(pScrn, 2); @@ -5217,7 +7913,7 @@ index 65ad33d..a6e332d 100644 RADEONWaitForFifo(pScrn, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN -@@ -343,7 +341,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) +@@ -343,7 +346,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX)); RADEONWaitForFifo(pScrn, 1); @@ -5226,7 +7922,7 @@ index 65ad33d..a6e332d 100644 | RADEON_GMC_BRUSH_SOLID_COLOR | RADEON_GMC_SRC_DATATYPE_COLOR)); -@@ -356,7 +354,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) +@@ -356,7 +359,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) RADEONWaitForIdleMMIO(pScrn); @@ -5235,7 +7931,7 @@ index 65ad33d..a6e332d 100644 } /* Initialize the acceleration hardware */ -@@ -364,6 +362,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -364,6 +367,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -5243,7 +7939,7 @@ index 65ad33d..a6e332d 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "EngineInit (%d/%d)\n", -@@ -372,21 +371,21 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -372,21 +376,21 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) #ifdef XF86DRI if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { @@ -5269,7 +7965,7 @@ index 65ad33d..a6e332d 100644 } } #endif -@@ -399,34 +398,34 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -399,34 +403,34 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) (info->ChipFamily == CHIP_FAMILY_RS400) || (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) { @@ -5311,7 +8007,7 @@ index 65ad33d..a6e332d 100644 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; -@@ -446,11 +445,11 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -446,11 +450,11 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) RADEONEngineReset(pScrn); switch (info->CurrentLayout.pixel_code) { @@ -5328,16 +8024,16 @@ index 65ad33d..a6e332d 100644 default: xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unknown depth/bpp = %d/%d (code = %d)\n", -@@ -458,34 +457,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -458,34 +462,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->CurrentLayout.bitsPerPixel, info->CurrentLayout.pixel_code); } - info->pitch = ((info->CurrentLayout.displayWidth / 8) * - (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1)); - +- - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Pitch for acceleration = %d\n", info->pitch); -- + - info->dp_gui_master_cntl = - ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) + info->accel_state->dp_gui_master_cntl = @@ -5365,7 +8061,7 @@ index 65ad33d..a6e332d 100644 RADEONEngineRestore(pScrn); } -@@ -534,14 +511,14 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -534,14 +516,14 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) /* Stop the CP */ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) { @@ -5383,7 +8079,7 @@ index 65ad33d..a6e332d 100644 if (ret == 0) { return 0; -@@ -553,8 +530,8 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) +@@ -553,8 +535,8 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) i = 0; do { @@ -5394,7 +8090,7 @@ index 65ad33d..a6e332d 100644 } while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY); if (ret == 0) { -@@ -565,8 +542,8 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) +@@ -565,8 +547,8 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) stop.idle = 0; @@ -5405,7 +8101,7 @@ index 65ad33d..a6e332d 100644 return -errno; } else { return 0; -@@ -608,7 +585,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -608,7 +590,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) while (1) { do { @@ -5414,7 +8110,7 @@ index 65ad33d..a6e332d 100644 if (ret && ret != -EBUSY) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: CP GetBuffer %d\n", __FUNCTION__, ret); -@@ -616,7 +593,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -616,7 +598,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); if (ret == 0) { @@ -5423,7 +8119,7 @@ index 65ad33d..a6e332d 100644 buf->used = 0; if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, -@@ -641,9 +618,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -641,9 +623,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -5436,7 +8132,7 @@ index 65ad33d..a6e332d 100644 if (!buffer) return; if (start == buffer->used && !discard) return; -@@ -658,18 +635,18 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -658,18 +640,18 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) indirect.end = buffer->used; indirect.discard = discard; @@ -5461,7 +8157,7 @@ index 65ad33d..a6e332d 100644 } } } -@@ -678,12 +655,12 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -678,12 +660,12 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -5479,7 +8175,7 @@ index 65ad33d..a6e332d 100644 if (!buffer) return; -@@ -697,8 +674,8 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -697,8 +679,8 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) indirect.end = buffer->used; indirect.discard = 1; @@ -5490,7 +8186,7 @@ index 65ad33d..a6e332d 100644 } /** \brief Calculate HostDataBlit parameters from pointer and pitch -@@ -964,7 +941,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -964,7 +946,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) if (!info->useEXA) { XAAInfoRecPtr a; @@ -5499,7 +8195,7 @@ index 65ad33d..a6e332d 100644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAACreateInfoRec Error\n"); return FALSE; } -@@ -993,16 +970,16 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -993,16 +975,16 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) #ifdef XF86DRI if (info->directRenderingEnabled) { @@ -5519,7 +8215,7 @@ index 65ad33d..a6e332d 100644 } #ifdef USE_XAA -@@ -1013,7 +990,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1013,7 +995,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); int cpp = info->CurrentLayout.pixel_bytes; @@ -5528,7 +8224,7 @@ index 65ad33d..a6e332d 100644 int width_bytes = pScrn->displayWidth * cpp; int bufferSize; int depthSize; -@@ -1023,9 +1000,9 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1023,9 +1005,9 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) BoxRec MemBox; FBAreaPtr fbarea; @@ -5541,7 +8237,7 @@ index 65ad33d..a6e332d 100644 /* make sure we use 16 line alignment for tiling (8 might be enough). * Might need that for non-XF86DRI too? -@@ -1042,30 +1019,18 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1042,30 +1024,18 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) * which is always the case if color tiling is used due to color pitch * but not necessarily otherwise, and its height a multiple of 16 lines. */ @@ -5578,7 +8274,7 @@ index 65ad33d..a6e332d 100644 /* Try for front, back, depth, and three framebuffers worth of * pixmap cache. Should be enough for a fullscreen background -@@ -1075,35 +1040,35 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1075,35 +1045,35 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) * otherwise probably), and never reserve more than 3 offscreen buffers as it's * probably useless for XAA. */ @@ -5623,7 +8319,7 @@ index 65ad33d..a6e332d 100644 - 2 * width_bytes - 16384 - info->FbSecureSize; } -@@ -1112,14 +1077,14 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1112,14 +1082,14 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) */ /* FIXME: what's this good for? condition is pretty much impossible to meet */ if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize @@ -5642,7 +8338,7 @@ index 65ad33d..a6e332d 100644 } /* RADEON_BUFFER_ALIGN is not sufficient for backbuffer! -@@ -1131,61 +1096,61 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1131,61 +1101,61 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) can't be used (?) due to that log_tex_granularity thing??? Could use different copyscreentoscreen function for the pageflip copies (which would use different src and dst offsets) to avoid this. */ @@ -5730,7 +8426,7 @@ index 65ad33d..a6e332d 100644 scanlines = (info->FbMapSize-info->FbSecureSize) / width_bytes; if (scanlines > 8191) -@@ -1236,12 +1201,12 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1236,12 +1206,12 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) /* Lines in offscreen area needed for depth buffer and * textures */ @@ -5749,7 +8445,7 @@ index 65ad33d..a6e332d 100644 } else { xf86DrvMsg(scrnIndex, X_ERROR, "Unable to determine largest offscreen area " -@@ -1252,30 +1217,30 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1252,30 +1222,30 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) xf86DrvMsg(scrnIndex, X_INFO, "Will use front buffer at offset 0x%x\n", @@ -6531,7 +9227,7 @@ index 56793cd..45eb6d5 100644 = FUNC_NAME(RADEONSetupForScanlineImageWrite); a->SubsequentScanlineImageWriteRect diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index 20aa722..851014b 100644 +index 20aa722..d612572 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -501,11 +501,11 @@ rhdAtomASICInit(atomBiosHandlePtr handle) @@ -6675,7 +9371,7 @@ index 20aa722..851014b 100644 } static RADEONI2CBusRec -@@ -1450,36 +1467,53 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) +@@ -1450,36 +1467,101 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; @@ -6725,15 +9421,63 @@ index 20aa722..851014b 100644 +static RADEONI2CBusRec +rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle, -+ ATOM_I2C_RECORD *Record) ++ ATOM_I2C_RECORD *Record, int i) +{ ++ RADEONInfoPtr info = RADEONPTR (pScrn); ++ ++ info->BiosConnector[i].i2c_line_mux = Record->sucI2cId.bfI2C_LineMux; + return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux); +} + ++static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index) ++{ ++ RADEONInfoPtr info = RADEONPTR (pScrn); ++ ++ /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ ++ if ((info->Chipset == PCI_CHIP_RS690_791E) && ++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x826d)) { ++ if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) && ++ (info->BiosConnector[index].TMDSType == TMDS_LVTMA)) { ++ info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; ++ } ++ } ++ ++ /* Falcon NW laptop lists vga ddc line for LVDS */ ++ if ((info->Chipset == PCI_CHIP_RV410_5653) && ++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0291)) { ++ if (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS) { ++ info->BiosConnector[index].ddc_i2c.valid = FALSE; ++ } ++ } ++ ++ /* Funky macbooks */ ++ if ((info->Chipset == PCI_CHIP_RV530_71C5) && ++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x106b) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0080)) { ++ if ((index == ATOM_DEVICE_CRT1_INDEX) || ++ (index == ATOM_DEVICE_CRT2_INDEX) || ++ (index == ATOM_DEVICE_DFP2_INDEX)) ++ info->BiosConnector[index].valid = FALSE; ++ ++ if (index == ATOM_DEVICE_DFP1_INDEX) { ++ info->BiosConnector[index].DACType = DAC_TVDAC; ++ info->BiosConnector[index].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); ++ } ++ } ++ ++ /* BIOSes seem to report DAC on HDMI - they hurt me with their lies */ ++ if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) || ++ (info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_B)) { ++ info->BiosConnector[index].DACType = DAC_NONE; ++ } ++} ++ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) { -@@ -1489,7 +1523,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1489,7 +1571,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) atomDataTablesPtr atomDataPtr; ATOM_CONNECTOR_OBJECT_TABLE *con_obj; ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL; @@ -6742,7 +9486,7 @@ index 20aa722..851014b 100644 atomDataPtr = info->atomBIOS->atomDataPtr; if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size)) -@@ -1560,15 +1594,23 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1560,15 +1642,43 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) break; case ENCODER_OBJECT_ID_INTERNAL_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: @@ -6770,10 +9514,30 @@ index 20aa722..851014b 100644 + info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX); + info->BiosConnector[i].TMDSType = TMDS_UNIPHY; + } ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS) ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX); ++ else { ++ if (num == 1) ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP3_INDEX); ++ else ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP4_INDEX); ++ info->BiosConnector[i].TMDSType = TMDS_UNIPHY1; ++ } ++ break; ++ ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS) ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX); ++ else { ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP5_INDEX); ++ info->BiosConnector[i].TMDSType = TMDS_UNIPHY2; ++ } break; case ENCODER_OBJECT_ID_INTERNAL_TMDS2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: -@@ -1577,8 +1619,12 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1577,11 +1687,18 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) break; case ENCODER_OBJECT_ID_INTERNAL_LVTM1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: @@ -6788,7 +9552,23 @@ index 20aa722..851014b 100644 break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: -@@ -1617,10 +1663,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A || ++ info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B) ++ break; + if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || + info->BiosConnector[i].ConnectorType == CONNECTOR_STV || + info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) +@@ -1593,6 +1710,9 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A || ++ info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B) ++ break; + if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || + info->BiosConnector[i].ConnectorType == CONNECTOR_STV || + info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) +@@ -1617,10 +1737,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) ErrorF("record type %d\n", Record->ucRecordType); switch (Record->ucRecordType) { case ATOM_I2C_RECORD_TYPE: @@ -6797,14 +9577,35 @@ index 20aa722..851014b 100644 - &ddc_line); - info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); + info->BiosConnector[i].ddc_i2c = rhdAtomParseI2CRecord(pScrn, info->atomBIOS, -+ (ATOM_I2C_RECORD *)Record); ++ (ATOM_I2C_RECORD *)Record, i); break; case ATOM_HPD_INT_RECORD_TYPE: break; -@@ -1636,6 +1680,71 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - } - - Bool +@@ -1631,7 +1749,88 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + Record = (ATOM_COMMON_RECORD_HEADER*) + ((char *)Record + Record->ucRecordSize); + } ++ ++ RADEONApplyATOMQuirks(pScrn, i); + } ++ ++ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { ++ if (info->BiosConnector[i].valid) { ++ for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { ++ if (info->BiosConnector[j].valid && (i != j) ) { ++ if (info->BiosConnector[i].i2c_line_mux == info->BiosConnector[j].i2c_line_mux) { ++ info->BiosConnector[i].shared_ddc = TRUE; ++ info->BiosConnector[j].shared_ddc = TRUE; ++ } ++ } ++ } ++ } ++ } ++ ++ return TRUE; ++} ++ ++Bool +RADEONGetATOMLVDSInfo(xf86OutputPtr output) +{ + ScrnInfoPtr pScrn = output->scrn; @@ -6866,45 +9667,62 @@ index 20aa722..851014b 100644 + radeon_output->HBlank, radeon_output->HOverPlus, radeon_output->HSyncWidth, + radeon_output->VBlank, radeon_output->VOverPlus, radeon_output->VSyncWidth); + -+ return TRUE; -+} -+ -+Bool - RADEONGetATOMTVInfo(xf86OutputPtr output) - { - ScrnInfoPtr pScrn = output->scrn; -@@ -1751,6 +1860,30 @@ static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index) - } - } + return TRUE; + } -+ /* Falcon NW laptop lists vga ddc line for LVDS */ -+ if ((info->Chipset == PCI_CHIP_RV410_5653) && -+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && -+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0291)) { -+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS) { -+ info->BiosConnector[index].ddc_i2c.valid = FALSE; -+ } -+ } -+ -+ /* Funky macbooks */ -+ if ((info->Chipset == PCI_CHIP_RV530_71C5) && -+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x106b) && -+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0080)) { -+ if ((index == ATOM_DEVICE_CRT1_INDEX) || -+ (index == ATOM_DEVICE_CRT2_INDEX) || -+ (index == ATOM_DEVICE_DFP2_INDEX)) -+ info->BiosConnector[index].valid = FALSE; -+ -+ if (index == ATOM_DEVICE_DFP1_INDEX) { -+ info->BiosConnector[index].DACType = DAC_TVDAC; -+ info->BiosConnector[index].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); -+ } -+ } -+ +@@ -1737,21 +1936,7 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ + return TRUE; } +-static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index) +-{ +- RADEONInfoPtr info = RADEONPTR (pScrn); + +- /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ +- if ((info->Chipset == PCI_CHIP_RS690_791E) && +- (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) && +- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x826d)) { +- if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) && +- (info->BiosConnector[index].TMDSType == TMDS_LVTMA)) { +- info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; +- } +- } +- +-} + Bool -@@ -2027,9 +2160,12 @@ RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle, + RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1796,6 +1981,8 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + #endif + + info->BiosConnector[i].valid = TRUE; ++ info->BiosConnector[i].load_detection = TRUE; ++ info->BiosConnector[i].shared_ddc = FALSE; + info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; + info->BiosConnector[i].devices = (1 << i); + info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType; +@@ -1867,9 +2054,8 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + info->BiosConnector[i].hpd_mask = 0; + break; + } +- } else { ++ } else + info->BiosConnector[i].hpd_mask = 0; +- } + + RADEONApplyATOMQuirks(pScrn, i); + +@@ -1895,6 +2081,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + info->BiosConnector[j].DACType = info->BiosConnector[i].DACType; + info->BiosConnector[j].devices |= info->BiosConnector[i].devices; + info->BiosConnector[i].valid = FALSE; ++ } else { ++ info->BiosConnector[i].shared_ddc = TRUE; ++ info->BiosConnector[j].shared_ddc = TRUE; + } + /* other possible combos? */ + } +@@ -2027,9 +2216,12 @@ RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle, VOID* CailAllocateMemory(VOID *CAIL,UINT16 size) { @@ -6918,7 +9736,7 @@ index 20aa722..851014b 100644 } VOID -@@ -2256,4 +2392,15 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m +@@ -2256,4 +2448,15 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m } @@ -6970,9 +9788,18 @@ index 3e7ae01..bed1471 100644 diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 529dda7..22bb5ed 100644 +index 529dda7..37954d3 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c +@@ -98,7 +98,7 @@ radeon_read_bios(ScrnInfoPtr pScrn) + } + + static Bool +-radeon_read_unposted_bios(ScrnInfoPtr pScrn) ++radeon_read_disabled_bios(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); @@ -266,6 +266,26 @@ radeon_read_unposted_bios(ScrnInfoPtr pScrn) return ret; } @@ -7000,23 +9827,19 @@ index 529dda7..22bb5ed 100644 /* Read the Video BIOS block and the FP registers (if applicable). */ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) -@@ -273,6 +293,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) - RADEONInfoPtr info = RADEONPTR(pScrn); - int tmp; - unsigned short dptr; -+ Bool posted = TRUE; - - #ifdef XSERVER_LIBPCIACCESS - int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; -@@ -291,6 +312,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -289,9 +309,8 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + info->BIOSAddr = pInt10->BIOSseg << 4; + (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), RADEON_VBIOS_SIZE); - } else if (!radeon_read_bios(pScrn)) { - (void)radeon_read_unposted_bios(pScrn); -+ posted = FALSE; - } +- } else if (!radeon_read_bios(pScrn)) { +- (void)radeon_read_unposted_bios(pScrn); +- } ++ } else if (!radeon_read_bios(pScrn)) ++ (void)radeon_read_disabled_bios(pScrn); } -@@ -326,7 +348,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { +@@ -326,7 +345,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->VBIOS = NULL; return FALSE; } @@ -7025,7 +9848,7 @@ index 529dda7..22bb5ed 100644 tmp = info->ROMHeaderStart + 4; if ((RADEON_BIOS8(tmp) == 'A' && RADEON_BIOS8(tmp+1) == 'T' && -@@ -344,51 +366,65 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -344,51 +363,62 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->IsAtomBios ? "ATOM":"Legacy"); if (info->IsAtomBios) { @@ -7094,11 +9917,7 @@ index 529dda7..22bb5ed 100644 + * so let's work around this for now by only POSTing if none of the + * CRTCs are enabled + */ -+ if ((!posted) && info->VBIOS) { -+ posted = radeon_card_posted(pScrn); -+ } -+ -+ if ((!posted) && info->VBIOS) { ++ if ((!radeon_card_posted(pScrn)) && info->VBIOS) { + if (info->IsAtomBios) { + if (!rhdAtomASICInit(info->atomBIOS)) + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, @@ -7109,6 +9928,7 @@ index 529dda7..22bb5ed 100644 - /* non-primary card may need posting */ - if (!pInt10) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via BIOS tables\n"); ++ /* FIX ME */ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); RADEONGetBIOSInitTableOffsets(pScrn); RADEONPostCardFromBIOSTables(pScrn); @@ -7120,7 +9940,7 @@ index 529dda7..22bb5ed 100644 return TRUE; } -@@ -397,7 +433,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -397,7 +427,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR (pScrn); if (!info->VBIOS) return FALSE; @@ -7129,7 +9949,7 @@ index 529dda7..22bb5ed 100644 if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) return TRUE; -@@ -411,28 +447,41 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) +@@ -411,28 +441,41 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) { RADEONInfoPtr info = RADEONPTR (pScrn); @@ -7188,7 +10008,7 @@ index 529dda7..22bb5ed 100644 } /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, -@@ -454,6 +503,16 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) +@@ -454,6 +497,26 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) } } @@ -7202,10 +10022,20 @@ index 529dda7..22bb5ed 100644 + } + } + ++ /* r200 card with primary dac routed to both VGA and DVI - disable load detection ++ * otherwise you end up detecing load if either port is attached ++ */ ++ if (info->Chipset == PCI_CHIP_R200_QL && ++ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1569 && ++ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x514c && ++ info->BiosConnector[index].DACType == DAC_PRIMARY) { ++ info->BiosConnector[index].load_detection = FALSE; ++ } ++ } static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) -@@ -479,7 +538,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -479,7 +542,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) ConnectorType = (tmp >> 12) & 0xf; switch (ConnectorType) { case CONNECTOR_PROPRIETARY_LEGACY: @@ -7214,7 +10044,7 @@ index 529dda7..22bb5ed 100644 break; case CONNECTOR_CRT_LEGACY: info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; -@@ -528,10 +587,6 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -528,15 +591,16 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) else info->BiosConnector[i].DACType = DAC_PRIMARY; @@ -7225,19 +10055,27 @@ index 529dda7..22bb5ed 100644 if ((tmp >> 4) & 0x1) info->BiosConnector[i].TMDSType = TMDS_EXT; else -@@ -560,7 +615,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + info->BiosConnector[i].TMDSType = TMDS_INT; + ++ if (info->BiosConnector[i].DACType == DAC_TVDAC) ++ info->BiosConnector[i].load_detection = FALSE; ++ else ++ info->BiosConnector[i].load_detection = TRUE; ++ + RADEONApplyLegacyQuirks(pScrn, i); + + } +@@ -560,7 +624,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) } /* check LVDS table */ - if (info->IsMobility) { -+ /* RS4xx can be mobile or desktop so check the connectors */ -+ if (info->IsMobility || -+ info->ChipFamily == CHIP_FAMILY_RS400 || -+ info->ChipFamily == CHIP_FAMILY_RS480) { ++ /* IGP can be mobile or desktop so check the connectors */ ++ if (info->IsMobility || info->IsIGP) { offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); if (offset) { info->BiosConnector[4].valid = TRUE; -@@ -591,10 +649,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -591,10 +656,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) break; case DDC_LCD: info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); @@ -7252,7 +10090,7 @@ index 529dda7..22bb5ed 100644 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); -@@ -602,10 +660,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -602,10 +667,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) break; case DDC_GPIO: info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); @@ -7267,7 +10105,26 @@ index 529dda7..22bb5ed 100644 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); -@@ -917,30 +975,9 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output) +@@ -618,9 +683,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); + } + } +- } else { ++ } else + info->BiosConnector[4].ddc_i2c.valid = FALSE; +- } + } + } + +@@ -633,6 +697,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + /* assume s-video for now */ + info->BiosConnector[5].ConnectorType = CONNECTOR_STV; + info->BiosConnector[5].DACType = DAC_TVDAC; ++ info->BiosConnector[5].load_detection = FALSE; + info->BiosConnector[5].TMDSType = TMDS_NONE; + info->BiosConnector[5].ddc_i2c.valid = FALSE; + } +@@ -917,30 +982,9 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output) if (!info->VBIOS) return FALSE; @@ -7301,16 +10158,70 @@ index 529dda7..22bb5ed 100644 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); -@@ -963,7 +1000,7 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output) - radeon_output->PanelYRes = RADEON_BIOS16(tmp+27); - xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", - radeon_output->PanelXRes, radeon_output->PanelYRes); -- +@@ -963,7 +1007,7 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output) + radeon_output->PanelYRes = RADEON_BIOS16(tmp+27); + xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", + radeon_output->PanelXRes, radeon_output->PanelYRes); +- ++ + radeon_output->PanelPwrDly = RADEON_BIOS16(tmp+44); + if (radeon_output->PanelPwrDly > 2000 || radeon_output->PanelPwrDly < 0) + radeon_output->PanelPwrDly = 2000; +@@ -1018,39 +1062,27 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output) + return TRUE; + } + +-Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) ++xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) + { + ScrnInfoPtr pScrn = output->scrn; +- RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned long tmp; +- char EDID[256]; ++ unsigned char edid[256]; ++ xf86MonPtr mon = NULL; + +- if (!info->VBIOS) return FALSE; ++ if (!info->VBIOS) ++ return mon; + +- if (info->IsAtomBios) { +- /* Not yet */ +- return FALSE; +- } else { +- if (!(tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c))) { +- return FALSE; ++ if (!info->IsAtomBios) { ++ tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c); ++ if (tmp) { ++ memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256); ++ if (edid[1] == 0xff) ++ mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); + } +- +- memcpy(EDID, (char*)(info->VBIOS + tmp), 256); +- +- radeon_output->DotClock = (*(uint16_t*)(EDID+54)) * 10; +- radeon_output->PanelXRes = (*(uint8_t*)(EDID+56)) + ((*(uint8_t*)(EDID+58))>>4)*256; +- radeon_output->HBlank = (*(uint8_t*)(EDID+57)) + ((*(uint8_t*)(EDID+58)) & 0xf)*256; +- radeon_output->HOverPlus = (*(uint8_t*)(EDID+62)) + ((*(uint8_t*)(EDID+65)>>6)*256); +- radeon_output->HSyncWidth = (*(uint8_t*)(EDID+63)) + (((*(uint8_t*)(EDID+65)>>4) & 3)*256); +- radeon_output->PanelYRes = (*(uint8_t*)(EDID+59)) + ((*(uint8_t*)(EDID+61))>>4)*256; +- radeon_output->VBlank = ((*(uint8_t*)(EDID+60)) + ((*(uint8_t*)(EDID+61)) & 0xf)*256); +- radeon_output->VOverPlus = (((*(uint8_t*)(EDID+64))>>4) + (((*(uint8_t*)(EDID+65)>>2) & 3)*16)); +- radeon_output->VSyncWidth = (((*(uint8_t*)(EDID+64)) & 0xf) + ((*(uint8_t*)(EDID+65)) & 3)*256); +- radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(uint8_t*)(EDID+71);*/ +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); + } +- return TRUE; + - radeon_output->PanelPwrDly = RADEON_BIOS16(tmp+44); - if (radeon_output->PanelPwrDly > 2000 || radeon_output->PanelPwrDly < 0) - radeon_output->PanelPwrDly = 2000; -@@ -1118,6 +1155,50 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) ++ return mon; + } + + Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1118,6 +1150,50 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) return FALSE; } @@ -7361,7 +10272,7 @@ index 529dda7..22bb5ed 100644 Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) { ScrnInfoPtr pScrn = output->scrn; -@@ -1129,6 +1210,52 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1129,6 +1205,52 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) if (info->IsAtomBios) { return FALSE; @@ -7414,7 +10325,7 @@ index 529dda7..22bb5ed 100644 } else { offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); if (offset) { -@@ -1148,10 +1275,11 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1148,10 +1270,11 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); else if (gpio_reg == 4) radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); @@ -7428,7 +10339,7 @@ index 529dda7..22bb5ed 100644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown gpio reg: %d\n", gpio_reg); return FALSE; -@@ -1179,12 +1307,82 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1179,12 +1302,82 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) unsigned char *RADEONMMIO = info->MMIO; RADEONOutputPrivatePtr radeon_output = output->driver_private; int offset, index, id; @@ -7512,7 +10423,7 @@ index 529dda7..22bb5ed 100644 } else { offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); if (offset) { -@@ -1194,24 +1392,24 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1194,24 +1387,24 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) index += 2; switch(id >> 13) { case 0: @@ -7547,7 +10458,7 @@ index 529dda7..22bb5ed 100644 break; case 4: val = RADEON_BIOS16(index); -@@ -1221,15 +1419,15 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1221,15 +1414,15 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) break; case 5: reg = id & 0x1fff; @@ -7571,7 +10482,7 @@ index 529dda7..22bb5ed 100644 case 6: reg = id & 0x1fff; diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index ed3174a..daaf717 100644 +index ed3174a..627520b 100644 --- a/src/radeon_chipinfo_gen.h +++ b/src/radeon_chipinfo_gen.h @@ -1,6 +1,7 @@ @@ -7582,26 +10493,71 @@ index ed3174a..daaf717 100644 { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, -@@ -250,6 +251,9 @@ RADEONCardInfo RADEONCards[] = { +@@ -250,6 +251,27 @@ RADEONCardInfo RADEONCards[] = { { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, + { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9441, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x9444, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x9446, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x944A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, ++ { 0x944B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, ++ { 0x944C, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x944E, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x9450, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x9452, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, ++ { 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, ++ { 0x9487, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, ++ { 0x948F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, ++ { 0x9490, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, ++ { 0x9498, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, ++ { 0x949C, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, ++ { 0x949E, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, ++ { 0x949F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, -@@ -267,6 +271,7 @@ RADEONCardInfo RADEONCards[] = { +@@ -267,6 +289,13 @@ RADEONCardInfo RADEONCards[] = { { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, + { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x9540, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, ++ { 0x9541, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, ++ { 0x954E, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, ++ { 0x954F, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, ++ { 0x9552, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, ++ { 0x9553, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, +@@ -279,11 +308,12 @@ RADEONCardInfo RADEONCards[] = { + { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, + { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, + { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x9592, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, + { 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, +- { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, +- { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, + { 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, + { 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, ++ { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, ++ { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, + { 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, + { 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, + { 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, +@@ -298,4 +328,5 @@ RADEONCardInfo RADEONCards[] = { + { 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, + { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, + { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, ++ { 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, + }; diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index d1761d2..79b094a 100644 +index d1761d2..b8a8a65 100644 --- a/src/radeon_chipset_gen.h +++ b/src/radeon_chipset_gen.h @@ -1,6 +1,7 @@ @@ -7612,24 +10568,99 @@ index d1761d2..79b094a 100644 { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, -@@ -250,6 +251,9 @@ static SymTabRec RADEONChipsets[] = { +@@ -226,7 +227,7 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" }, + { PCI_CHIP_RV570_7289, "ATI RV570" }, + { PCI_CHIP_RV570_728B, "ATI RV570" }, +- { PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" }, ++ { PCI_CHIP_RV570_728C, "ATI FireGL V7400" }, + { PCI_CHIP_RV560_7290, "ATI RV560" }, + { PCI_CHIP_RV560_7291, "ATI Radeon X1650" }, + { PCI_CHIP_RV560_7293, "ATI Radeon X1650" }, +@@ -250,13 +251,34 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, + { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" }, + { PCI_CHIP_RV770_9441, "ATI Radeon HD 4870 x2" }, + { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" }, ++ { PCI_CHIP_RV770_9444, "ATI FirePro V8750 (FireGL)" }, ++ { PCI_CHIP_RV770_9446, "ATI FirePro V7760 (FireGL)" }, ++ { PCI_CHIP_RV770_944A, "ATI Mobility RADEON HD 4850" }, ++ { PCI_CHIP_RV770_944B, "ATI Mobility RADEON HD 4850 X2" }, ++ { PCI_CHIP_RV770_944C, "ATI Radeon 4800 Series" }, ++ { PCI_CHIP_RV770_944E, "ATI FirePro RV770" }, ++ { PCI_CHIP_RV770_9450, "AMD FireStream 9270" }, ++ { PCI_CHIP_RV770_9452, "AMD FireStream 9250" }, ++ { PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" }, ++ { PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" }, ++ { PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" }, ++ { PCI_CHIP_RV730_9487, "ATI Radeon RV730 (AGP)" }, ++ { PCI_CHIP_RV730_948F, "ATI Radeon RV730 (AGP)" }, ++ { PCI_CHIP_RV730_9490, "ATI RV730XT [Radeon HD 4670]" }, ++ { PCI_CHIP_RV730_9498, "ATI RV730 PRO [Radeon HD 4650]" }, ++ { PCI_CHIP_RV730_949C, "ATI FirePro V7750 (FireGL)" }, ++ { PCI_CHIP_RV730_949E, "ATI FirePro V5700 (FireGL)" }, ++ { PCI_CHIP_RV730_949F, "ATI FirePro V3750 (FireGL)" }, { PCI_CHIP_RV610_94C0, "ATI RV610" }, { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, -@@ -267,6 +271,7 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV610_94C4, "ATI Radeon HD 2400 PRO AGP" }, + { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" }, + { PCI_CHIP_RV610_94C6, "ATI RV610" }, +- { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" }, ++ { PCI_CHIP_RV610_94C7, "ATI Radeon HD 2350" }, + { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" }, + { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, + { PCI_CHIP_RV610_94CB, "ATI RADEON E2400" }, +@@ -267,6 +289,13 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV670_9507, "ATI RV670" }, { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, + { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" }, ++ { PCI_CHIP_RV710_9540, "ATI Radeon HD 4550" }, ++ { PCI_CHIP_RV710_9541, "ATI Radeon RV710" }, ++ { PCI_CHIP_RV710_954E, "ATI Radeon RV710" }, ++ { PCI_CHIP_RV710_954F, "ATI Radeon HD 4350" }, ++ { PCI_CHIP_RV710_9552, "ATI Mobility Radeon 4300 Series" }, ++ { PCI_CHIP_RV710_9553, "ATI Mobility Radeon 4500 Series" }, { PCI_CHIP_RV630_9580, "ATI RV630" }, { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, +@@ -279,24 +308,26 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, + { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, + { PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" }, ++ { PCI_CHIP_RV710_9592, "ATI Radeon RV710" }, + { PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" }, +- { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, +- { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, + { PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" }, + { PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" }, ++ { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, ++ { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, + { PCI_CHIP_RV620_95CD, "ATI FireMV 2450" }, + { PCI_CHIP_RV620_95CE, "ATI FireMV 2260" }, + { PCI_CHIP_RV620_95CF, "ATI FireMV 2260" }, +- { PCI_CHIP_RV635_9590, "ATI ATI Radeon HD 3600 Series" }, +- { PCI_CHIP_RV635_9596, "ATI ATI Radeon HD 3650 AGP" }, +- { PCI_CHIP_RV635_9597, "ATI ATI Radeon HD 3600 PRO" }, +- { PCI_CHIP_RV635_9598, "ATI ATI Radeon HD 3600 XT" }, +- { PCI_CHIP_RV635_9599, "ATI ATI Radeon HD 3600 PRO" }, ++ { PCI_CHIP_RV635_9590, "ATI Radeon HD 3600 Series" }, ++ { PCI_CHIP_RV635_9596, "ATI Radeon HD 3650 AGP" }, ++ { PCI_CHIP_RV635_9597, "ATI Radeon HD 3600 PRO" }, ++ { PCI_CHIP_RV635_9598, "ATI Radeon HD 3600 XT" }, ++ { PCI_CHIP_RV635_9599, "ATI Radeon HD 3600 PRO" }, + { PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" }, + { PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" }, + { PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" }, + { PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" }, + { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, + { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, ++ { PCI_CHIP_RS780_9614, "ATI Radeon HD 3300 Graphics" }, + { -1, NULL } + }; diff --git a/src/radeon_common.h b/src/radeon_common.h deleted file mode 100644 index 193c1f9..0000000 @@ -8133,7 +11164,7 @@ index 193c1f9..0000000 - -#endif diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index 58fe306..dba197e 100644 +index 58fe306..0a9f9db 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -58,7 +58,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) @@ -8226,46 +11257,168 @@ index 58fe306..dba197e 100644 BEGIN_ACCEL(13); OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); /* PVS inst 0 */ -@@ -498,14 +500,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - if (IS_R300_3D) { - BEGIN_ACCEL(2); - /* tex inst for src texture */ -- OUT_ACCEL_REG(R300_US_TEX_INST_0, -+ OUT_ACCEL_REG(R300_US_TEX_INST(0), - (R300_TEX_SRC_ADDR(0) | - R300_TEX_DST_ADDR(0) | - R300_TEX_ID(0) | - R300_TEX_INST(R300_TEX_INST_LD))); - - /* tex inst for mask texture */ -- OUT_ACCEL_REG(R300_US_TEX_INST_1, -+ OUT_ACCEL_REG(R300_US_TEX_INST(1), - (R300_TEX_SRC_ADDR(1) | - R300_TEX_DST_ADDR(1) | - R300_TEX_ID(1) | -@@ -514,9 +516,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -494,48 +496,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) } + FINISH_ACCEL(); - if (IS_R300_3D) { +- /* pre-load FS tex instructions */ +- if (IS_R300_3D) { +- BEGIN_ACCEL(2); +- /* tex inst for src texture */ +- OUT_ACCEL_REG(R300_US_TEX_INST_0, +- (R300_TEX_SRC_ADDR(0) | +- R300_TEX_DST_ADDR(0) | +- R300_TEX_ID(0) | +- R300_TEX_INST(R300_TEX_INST_LD))); +- +- /* tex inst for mask texture */ +- OUT_ACCEL_REG(R300_US_TEX_INST_1, +- (R300_TEX_SRC_ADDR(1) | +- R300_TEX_DST_ADDR(1) | +- R300_TEX_ID(1) | +- R300_TEX_INST(R300_TEX_INST_LD))); +- FINISH_ACCEL(); +- } +- +- if (IS_R300_3D) { - BEGIN_ACCEL(9); -+ BEGIN_ACCEL(8); - OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); +- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); - OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ - OUT_ACCEL_REG(R300_US_CODE_ADDR_0, - (R300_ALU_START(0) | - R300_ALU_SIZE(0) | -@@ -533,9 +534,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - R300_TEX_START(0) | - R300_TEX_SIZE(0))); - } else { +- OUT_ACCEL_REG(R300_US_CODE_ADDR_0, +- (R300_ALU_START(0) | +- R300_ALU_SIZE(0) | +- R300_TEX_START(0) | +- R300_TEX_SIZE(0))); +- OUT_ACCEL_REG(R300_US_CODE_ADDR_1, +- (R300_ALU_START(0) | +- R300_ALU_SIZE(0) | +- R300_TEX_START(0) | +- R300_TEX_SIZE(0))); +- OUT_ACCEL_REG(R300_US_CODE_ADDR_2, +- (R300_ALU_START(0) | +- R300_ALU_SIZE(0) | +- R300_TEX_START(0) | +- R300_TEX_SIZE(0))); +- } else { - BEGIN_ACCEL(7); ++ if (IS_R300_3D) ++ BEGIN_ACCEL(4); ++ else { + BEGIN_ACCEL(6); OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); - OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ OUT_ACCEL_REG(R500_US_FC_CTRL, 0); } OUT_ACCEL_REG(R300_US_W_FMT, 0); -@@ -687,14 +687,14 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) +@@ -583,13 +548,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); + FINISH_ACCEL(); + +- BEGIN_ACCEL(7); ++ BEGIN_ACCEL(5); + OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); +- OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | +- (0 << R300_SCISSOR_Y_SHIFT))); +- OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | +- (8191 << R300_SCISSOR_Y_SHIFT))); +- + if (IS_R300_3D) { + /* clip has offset 1440 */ + OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | +@@ -610,7 +570,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + +- BEGIN_ACCEL(7); ++ BEGIN_ACCEL(6); + if (info->ChipFamily == CHIP_FAMILY_RS300) { + OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); + } else { +@@ -619,7 +579,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + OUT_ACCEL_REG(R200_PP_CNTL_X, 0); + OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); +- OUT_ACCEL_REG(R200_RE_CNTL, 0x0); + OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | + R200_VAP_VF_MAX_VTX_NUM); +@@ -667,6 +626,75 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + + } + ++/* inserts a wait for vline in the command stream */ ++void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, ++ int crtc, int start, int stop, Bool enable) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++ uint32_t offset; ++ ACCEL_PREAMBLE(); ++ ++ if (!enable) ++ return; ++ ++ if ((crtc < 0) || (crtc > 1)) ++ return; ++ ++ if (stop < start) ++ return; ++ ++ if (!xf86_config->crtc[crtc]->enabled) ++ return; ++ ++#ifdef USE_EXA ++ if (info->useEXA) ++ offset = exaGetPixmapOffset(pPix); ++ else ++#endif ++ offset = pPix->devPrivate.ptr - info->FB; ++ ++ /* if drawing to front buffer */ ++ if (offset != 0) ++ return; ++ ++ start = max(start, 0); ++ stop = max(stop, xf86_config->crtc[crtc]->mode.VDisplay); ++ ++ if (start > xf86_config->crtc[crtc]->mode.VDisplay) ++ return; ++ ++ BEGIN_ACCEL(2); ++ ++ if (IS_AVIVO_VARIANT) { ++ RADEONCrtcPrivatePtr radeon_crtc = xf86_config->crtc[crtc]->driver_private; ++ ++ OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset, ++ ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | ++ (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | ++ AVIVO_D1MODE_VLINE_INV)); ++ } else { ++ if (crtc == 0) ++ OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, ++ ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | ++ (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | ++ RADEON_CRTC_GUI_TRIG_VLINE_INV)); ++ else ++ OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE, ++ ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | ++ (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | ++ RADEON_CRTC_GUI_TRIG_VLINE_INV)); ++ } ++ ++ if (crtc == 0) ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | ++ RADEON_ENG_DISPLAY_SELECT_CRTC0)); ++ else ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | ++ RADEON_ENG_DISPLAY_SELECT_CRTC1)); ++ ++ FINISH_ACCEL(); ++} + + /* MMIO: + * +@@ -687,14 +715,14 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) #ifdef ACCEL_CP /* Make sure the CP is idle first */ @@ -8282,8 +11435,18 @@ index 58fe306..dba197e 100644 if (ret && ret != -EBUSY) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: CP idle %d\n", __FUNCTION__, ret); +@@ -722,6 +750,9 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) + INREG(RADEON_RBBM_STATUS)); + #endif + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return; ++ + /* Wait for the engine to go idle */ + RADEONWaitForFifoFunction(pScrn, 64); + diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index c63b650..9040bae 100644 +index c63b650..e0875a4 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -48,8 +48,7 @@ @@ -8449,7 +11612,7 @@ index c63b650..9040bae 100644 return info->FB + rotate_offset; } -@@ -523,26 +460,16 @@ static void +@@ -523,29 +460,67 @@ static void radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) { ScrnInfoPtr pScrn = crtc->scrn; @@ -8471,17 +11634,73 @@ index c63b650..9040bae 100644 - if (!info->useEXA) { - xf86FreeOffscreenLinear(radeon_crtc->rotate_mem_xaa); - radeon_crtc->rotate_mem_xaa = NULL; -- } --#endif /* USE_XAA */ + radeon_legacy_free_memory(pScrn, radeon_crtc->crtc_rotate_mem); + radeon_crtc->crtc_rotate_mem = NULL; - } ++ } ++ ++} ++ ++#if XF86_CRTC_VERSION >= 2 ++#include "radeon_atombios.h" ++ ++extern AtomBiosResult ++atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); ++extern void ++RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, ++ int x, int y); ++extern void ++RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, ++ int x, int y); ++extern void ++RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, ++ RADEONSavePtr restore); ++extern void ++RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, ++ RADEONSavePtr restore); ++ ++static void ++radeon_crtc_set_origin(xf86CrtcPtr crtc, int x, int y) ++{ ++ ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; + ++ if (IS_AVIVO_VARIANT) { ++ atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); ++ atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); ++ } else { ++ switch (radeon_crtc->crtc_id) { ++ case 0: ++ RADEONInitCrtcBase(crtc, info->ModeReg, x, y); ++ RADEONRestoreCrtcBase(pScrn, info->ModeReg); ++ break; ++ case 1: ++ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); ++ RADEONRestoreCrtc2Base(pScrn, info->ModeReg); ++ break; ++ default: ++ break; + } +-#endif /* USE_XAA */ + } } ++#endif ++ - static const xf86CrtcFuncsRec radeon_crtc_funcs = { -@@ -567,6 +494,43 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { +-static const xf86CrtcFuncsRec radeon_crtc_funcs = { ++static xf86CrtcFuncsRec radeon_crtc_funcs = { + .dpms = radeon_crtc_dpms, + .save = NULL, /* XXX */ + .restore = NULL, /* XXX */ +@@ -565,13 +540,60 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { + .hide_cursor = radeon_crtc_hide_cursor, + .load_cursor_argb = radeon_crtc_load_cursor_argb, .destroy = NULL, /* XXX */ ++#if XF86_CRTC_VERSION >= 2 ++ .set_origin = radeon_crtc_set_origin, ++#endif }; +void @@ -8524,7 +11743,19 @@ index c63b650..9040bae 100644 Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -@@ -791,7 +755,7 @@ RADEONSetTiling(ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR(pScrn); + ++ if ((info->ChipFamily < CHIP_FAMILY_R600) && ++ (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE))) { ++ radeon_crtc_funcs.shadow_create = radeon_crtc_shadow_create; ++ radeon_crtc_funcs.shadow_allocate = radeon_crtc_shadow_allocate; ++ radeon_crtc_funcs.shadow_destroy = radeon_crtc_shadow_destroy; ++ } ++ + if (mask & 1) { + if (pRADEONEnt->Controller[0]) + return TRUE; +@@ -791,7 +813,7 @@ RADEONSetTiling(ScrnInfoPtr pScrn) #ifdef XF86DRI if (info->directRenderingEnabled && (info->tilingEnabled != can_tile)) { @@ -8534,10 +11765,10 @@ index c63b650..9040bae 100644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[drm] failed changing tiling status\n"); diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c -index c4472db..08bfddf 100644 +index c4472db..0fcdcf0 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c -@@ -209,21 +209,23 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) +@@ -209,21 +209,21 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1; if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1; @@ -8560,15 +11791,13 @@ index c4472db..08bfddf 100644 OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); avivo_lock_cursor(crtc, FALSE); } else { -+ if (mode->Flags & V_INTERLACE) -+ y /= 2; -+ else if (mode->Flags & V_DBLSCAN) ++ if (mode->Flags & V_DBLSCAN) + y *= 2; + if (crtc_id == 0) { OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK | (xorigin << 16) -@@ -325,49 +327,32 @@ Bool RADEONCursorInit(ScreenPtr pScreen) +@@ -325,49 +325,32 @@ Bool RADEONCursorInit(ScreenPtr pScreen) int width_bytes; int height; int size_bytes; @@ -8733,7 +11962,7 @@ index d623fe4..6b0fabe 100644 if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) RADEON_MARK_SYNC(info, pScrn); diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index 0fc03e4..5542d2b 100644 +index 0fc03e4..7c317e6 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -46,6 +46,7 @@ @@ -8977,7 +12206,7 @@ index 0fc03e4..5542d2b 100644 #endif /* USE_XAA */ } -@@ -692,36 +696,36 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info) +@@ -692,36 +696,83 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info) { int s, l; @@ -9016,6 +12245,53 @@ index 0fc03e4..5542d2b 100644 + info->dri->log2GARTTexGran = l; } ++/* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with ++ * the standard AGPMode settings, so we detect and handle these ++ * on a case-by-base basis with quirks. To see if an AGPMode is valid, test ++ * it by setting Option "AGPMode" "1" (or "2", or "4" or "8"). */ ++typedef struct { ++ unsigned int hostbridgeVendor; ++ unsigned int hostbridgeDevice; ++ unsigned int chipVendor; ++ unsigned int chipDevice; ++ unsigned int subsysVendor; ++ unsigned int subsysDevice; ++ unsigned int defaultMode; ++} radeon_agpmode_quirk, *radeon_agpmode_quirk_ptr; ++ ++/* Keep sorted by hostbridge vendor and device */ ++static radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { ++ ++ /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */ ++ { PCI_VENDOR_INTEL,0x2570, PCI_VENDOR_ATI,0x4a4e, PCI_VENDOR_DELL,0x5106, 4 }, ++ /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */ ++ { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4c59, 0x1014,0x052f, 1}, ++ /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ ++ { PCI_VENDOR_INTEL,0x3575, PCI_VENDOR_ATI,0x4c59, PCI_VENDOR_DELL,0x00e3, 2 }, ++ /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ ++ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1025,0x0061, 1 }, ++ /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */ ++ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1025,0x0064, 1 }, ++ /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */ ++ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1043,0x1942, 1 }, ++ /* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */ ++ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4c66, 0x1028,0x0149, 1 }, ++ ++ /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (LP: #133192) */ ++ { 0x1849,0x3189, PCI_VENDOR_ATI,0x5960, 0x1787, 0x5960, 4}, ++ ++ /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */ ++ { 0x1106,0x0305, PCI_VENDOR_ATI,0x514c, 0x1002,0x013a, 2 }, ++ /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */ ++ { 0x1106,0x3189, PCI_VENDOR_ATI,0x514d, 0x174b,0x7149, 4 }, ++ /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */ ++ { 0x1106,0x0691, PCI_VENDOR_ATI,0x5960, 0x1043,0x0054, 2 }, ++ /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */ ++ { 0x1106,0x0204, PCI_VENDOR_ATI,0x5960, 0x17af,0x2020, 4 }, ++ ++ { 0, 0, 0, 0, 0, 0, 0 }, ++}; ++ /* Set AGP transfer mode according to requests and constraints */ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) { @@ -9029,8 +12305,25 @@ index 0fc03e4..5542d2b 100644 /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with pcie-agp rialto bridge chip - use the one from bridge which must match */ uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; -@@ -739,26 +743,26 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -737,28 +788,43 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) + else defaultMode = 1; + } ++ /* Apply AGPMode Quirks */ ++ radeon_agpmode_quirk_ptr p = radeon_agpmode_quirk_list; ++ while (p && p->chipDevice != 0) { ++ if (vendor == p->hostbridgeVendor && ++ device == p->hostbridgeDevice && ++ PCI_DEV_VENDOR_ID(info->PciInfo) == p->chipVendor && ++ PCI_DEV_DEVICE_ID(info->PciInfo) == p->chipDevice && ++ PCI_SUB_VENDOR_ID(info->PciInfo) == p->subsysVendor && ++ PCI_SUB_DEVICE_ID(info->PciInfo) == p->subsysDevice) ++ { ++ defaultMode = p->defaultMode; ++ } ++ ++p; ++ } ++ from = X_DEFAULT; - if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) { @@ -9065,7 +12358,7 @@ index 0fc03e4..5542d2b 100644 case 8: mode |= RADEON_AGPv3_8X_MODE; break; case 4: default: mode |= RADEON_AGPv3_4X_MODE; } -@@ -766,7 +770,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -766,7 +832,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) * currently these bits are not used in all tested cards. */ } else { @@ -9074,7 +12367,7 @@ index 0fc03e4..5542d2b 100644 case 4: mode |= RADEON_AGP_4X_MODE; case 2: mode |= RADEON_AGP_2X_MODE; case 1: default: mode |= RADEON_AGP_1X_MODE; -@@ -800,9 +804,9 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -800,9 +866,9 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) PCI_DEV_VENDOR_ID(info->PciInfo), PCI_DEV_DEVICE_ID(info->PciInfo)); @@ -9086,7 +12379,7 @@ index 0fc03e4..5542d2b 100644 return FALSE; } -@@ -829,15 +833,15 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -829,15 +895,15 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen) * agp_base_2 ? */ if (info->ChipFamily == CHIP_FAMILY_RV515) @@ -9106,7 +12399,7 @@ index 0fc03e4..5542d2b 100644 } /* Initialize the AGP state. Request memory for use in AGP space, and -@@ -847,7 +851,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -847,7 +913,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) { int ret; @@ -9115,7 +12408,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_WARNING, "[agp] AGP not available\n"); return FALSE; } -@@ -857,101 +861,101 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -857,101 +923,103 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) RADEONDRIInitGARTValues(info); @@ -9131,7 +12424,8 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] %d kB allocated with handle 0x%08x\n", - info->gartSize*1024, info->agpMemHandle); -+ info->dri->gartSize*1024, info->dri->agpMemHandle); ++ info->dri->gartSize*1024, ++ (unsigned int)info->dri->agpMemHandle); - if (drmAgpBind(info->drmFD, - info->agpMemHandle, info->gartOffset) < 0) { @@ -9155,7 +12449,8 @@ index 0fc03e4..5542d2b 100644 } xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] ring handle = 0x%08x\n", info->ringHandle); -+ "[agp] ring handle = 0x%08x\n", info->dri->ringHandle); ++ "[agp] ring handle = 0x%08x\n", ++ (unsigned int)info->dri->ringHandle); - if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, - &info->ring) < 0) { @@ -9180,7 +12475,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] ring read ptr handle = 0x%08x\n", - info->ringReadPtrHandle); -+ info->dri->ringReadPtrHandle); ++ (unsigned int)info->dri->ringReadPtrHandle); - if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, - &info->ringReadPtr) < 0) { @@ -9206,7 +12501,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] vertex/indirect buffers handle = 0x%08x\n", - info->bufHandle); -+ info->dri->bufHandle); ++ (unsigned int)info->dri->bufHandle); - if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, - &info->buf) < 0) { @@ -9232,7 +12527,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] GART texture map handle = 0x%08x\n", - info->gartTexHandle); -+ info->dri->gartTexHandle); ++ (unsigned int)info->dri->gartTexHandle); - if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize, - &info->gartTex) < 0) { @@ -9249,7 +12544,7 @@ index 0fc03e4..5542d2b 100644 RADEONSetAgpBase(info, pScreen); -@@ -966,104 +970,104 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -966,104 +1034,106 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) int ret; int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL; @@ -9264,7 +12559,8 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] %d kB allocated with handle 0x%08x\n", - info->gartSize*1024, info->pciMemHandle); -+ info->dri->gartSize*1024, info->dri->pciMemHandle); ++ info->dri->gartSize*1024, ++ (unsigned int)info->dri->pciMemHandle); RADEONDRIInitGARTValues(info); @@ -9278,7 +12574,8 @@ index 0fc03e4..5542d2b 100644 } xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] ring handle = 0x%08x\n", info->ringHandle); -+ "[pci] ring handle = 0x%08x\n", info->dri->ringHandle); ++ "[pci] ring handle = 0x%08x\n", ++ (unsigned int)info->dri->ringHandle); - if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, - &info->ring) < 0) { @@ -9307,7 +12604,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] ring read ptr handle = 0x%08x\n", - info->ringReadPtrHandle); -+ info->dri->ringReadPtrHandle); ++ (unsigned int)info->dri->ringReadPtrHandle); - if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, - &info->ringReadPtr) < 0) { @@ -9337,7 +12634,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] vertex/indirect buffers handle = 0x%08x\n", - info->bufHandle); -+ info->dri->bufHandle); ++ (unsigned int)info->dri->bufHandle); - if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, - &info->buf) < 0) { @@ -9367,7 +12664,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] GART texture map handle = 0x%08x\n", - info->gartTexHandle); -+ info->dri->gartTexHandle); ++ (unsigned int)info->dri->gartTexHandle); - if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize, - &info->gartTex) < 0) { @@ -9384,7 +12681,7 @@ index 0fc03e4..5542d2b 100644 return TRUE; } -@@ -1074,13 +1078,13 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1074,13 +1144,14 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) { /* Map registers */ @@ -9398,11 +12695,12 @@ index 0fc03e4..5542d2b 100644 } xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] register handle = 0x%08x\n", info->registerHandle); -+ "[drm] register handle = 0x%08x\n", info->dri->registerHandle); ++ "[drm] register handle = 0x%08x\n", ++ (unsigned int)info->dri->registerHandle); return TRUE; } -@@ -1090,43 +1094,43 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1090,43 +1161,43 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; int cpp = info->CurrentLayout.pixel_bytes; @@ -9473,7 +12771,7 @@ index 0fc03e4..5542d2b 100644 return FALSE; /* DRM_RADEON_CP_INIT does an engine reset, which resets some engine -@@ -1140,21 +1144,21 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1140,21 +1211,21 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen) { @@ -9499,7 +12797,7 @@ index 0fc03e4..5542d2b 100644 } } -@@ -1164,29 +1168,29 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1164,29 +1235,29 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen) static Bool RADEONDRIBufInit(RADEONInfoPtr info, ScreenPtr pScreen) { /* Initialize vertex buffers */ @@ -9538,7 +12836,7 @@ index 0fc03e4..5542d2b 100644 return TRUE; } -@@ -1195,29 +1199,35 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1195,29 +1266,35 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -9581,7 +12879,7 @@ index 0fc03e4..5542d2b 100644 } -@@ -1233,7 +1243,7 @@ static void RADEONDRICPInit(ScrnInfoPtr pScrn) +@@ -1233,7 +1310,7 @@ static void RADEONDRICPInit(ScrnInfoPtr pScrn) RADEONCP_START(pScrn, info); #ifdef USE_XAA if (!info->useEXA) @@ -9590,7 +12888,7 @@ index 0fc03e4..5542d2b 100644 #endif } -@@ -1274,16 +1284,16 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1274,16 +1351,16 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) /* Check the lib version */ if (xf86LoaderCheckSymbol("drmGetLibVersion")) @@ -9611,7 +12909,7 @@ index 0fc03e4..5542d2b 100644 /* incompatible drm library version */ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] RADEONDRIGetVersion failed because of a " -@@ -1291,11 +1301,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1291,11 +1368,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) "[dri] libdrm.a module version is %d.%d.%d but " "version 1.2.x is needed.\n" "[dri] Disabling DRI.\n", @@ -9628,7 +12926,7 @@ index 0fc03e4..5542d2b 100644 return FALSE; } -@@ -1322,9 +1332,9 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1322,9 +1399,9 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) } /* Get DRM version & close DRM */ @@ -9640,7 +12938,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] RADEONDRIGetVersion failed to get the DRM version\n" "[dri] Disabling DRI.\n"); -@@ -1344,10 +1354,10 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1344,10 +1421,10 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) } /* We don't, bummer ! */ @@ -9655,7 +12953,7 @@ index 0fc03e4..5542d2b 100644 /* Incompatible drm version */ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] RADEONDRIGetVersion failed because of a version " -@@ -1355,13 +1365,13 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1355,13 +1432,13 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) "[dri] radeon.o kernel module version is %d.%d.%d " "but version 1.%d.%d or newer is needed.\n" "[dri] Disabling DRI.\n", @@ -9674,7 +12972,7 @@ index 0fc03e4..5542d2b 100644 return FALSE; } -@@ -1377,7 +1387,7 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1377,7 +1454,7 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) if (!info->want_vblank_interrupts) on = FALSE; @@ -9683,7 +12981,7 @@ index 0fc03e4..5542d2b 100644 if (on) { if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled) value = DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2; -@@ -1406,7 +1416,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1406,7 +1483,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) DRIInfoPtr pDRIInfo; RADEONDRIPtr pRADEONDRI; @@ -9692,7 +12990,7 @@ index 0fc03e4..5542d2b 100644 switch (info->CurrentLayout.pixel_code) { case 8: -@@ -1432,7 +1442,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1432,7 +1509,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) */ if (!(pDRIInfo = DRICreateInfoRec())) return FALSE; @@ -9701,7 +12999,7 @@ index 0fc03e4..5542d2b 100644 pDRIInfo->drmDriverName = RADEON_DRIVER_NAME; if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) { -@@ -1453,11 +1463,10 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1453,11 +1530,10 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) PCI_DEV_DEV(info->PciInfo), PCI_DEV_FUNC(info->PciInfo)); } @@ -9717,7 +13015,7 @@ index 0fc03e4..5542d2b 100644 pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; pDRIInfo->frameBufferStride = (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); -@@ -1487,7 +1496,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1487,7 +1563,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) /* For now the mapping works by using a fixed size defined * in the SAREA header */ @@ -9726,7 +13024,7 @@ index 0fc03e4..5542d2b 100644 ErrorF("Data does not fit in SAREA\n"); return FALSE; } -@@ -1495,8 +1504,8 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1495,8 +1571,8 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) #endif if (!(pRADEONDRI = (RADEONDRIPtr)xcalloc(sizeof(RADEONDRIRec),1))) { @@ -9737,7 +13035,7 @@ index 0fc03e4..5542d2b 100644 return FALSE; } pDRIInfo->devPrivate = pRADEONDRI; -@@ -1538,7 +1547,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1538,7 +1614,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) } #endif @@ -9746,7 +13044,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_ERROR, "[dri] DRIScreenInit failed. Disabling DRI.\n"); xfree(pDRIInfo->devPrivate); -@@ -1581,7 +1590,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1581,7 +1657,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) void *scratch_ptr; int scratch_int; @@ -9755,7 +13053,7 @@ index 0fc03e4..5542d2b 100644 &scratch_int, &scratch_int, &scratch_int, &scratch_int, &scratch_ptr); -@@ -1605,7 +1614,7 @@ static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -1605,7 +1681,7 @@ static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) RADEONDRICloseScreen(pScreen); @@ -9764,7 +13062,7 @@ index 0fc03e4..5542d2b 100644 return (*pScreen->CloseScreen)(scrnIndex, pScreen); } -@@ -1617,11 +1626,11 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1617,11 +1693,11 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9779,7 +13077,7 @@ index 0fc03e4..5542d2b 100644 /* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit * because *DRIKernelInit requires that the hardware lock is held by -@@ -1655,10 +1664,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1655,10 +1731,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) RADEONDRICPInit(pScrn); /* Initialize the SAREA private data structure */ @@ -9792,7 +13090,7 @@ index 0fc03e4..5542d2b 100644 pRADEONDRI->deviceID = info->Chipset; pRADEONDRI->width = pScrn->virtualX; -@@ -1667,40 +1676,40 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1667,40 +1743,40 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) pRADEONDRI->bpp = pScrn->bitsPerPixel; pRADEONDRI->IsPCI = (info->cardType!=CARD_AGP); @@ -9853,7 +13151,7 @@ index 0fc03e4..5542d2b 100644 pScreen->CloseScreen = RADEONDRIDoCloseScreen; /* disable vblank at startup */ -@@ -1721,7 +1730,7 @@ void RADEONDRIResume(ScreenPtr pScreen) +@@ -1721,7 +1797,7 @@ void RADEONDRIResume(ScreenPtr pScreen) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9862,7 +13160,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_INFO, "[RESUME] Attempting to re-init Radeon hardware.\n"); } else { -@@ -1738,7 +1747,7 @@ void RADEONDRIResume(ScreenPtr pScreen) +@@ -1738,7 +1814,7 @@ void RADEONDRIResume(ScreenPtr pScreen) RADEONSetAgpBase(info, pScreen); } @@ -9871,7 +13169,7 @@ index 0fc03e4..5542d2b 100644 if (_ret) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: CP resume %d\n", __FUNCTION__, _ret); -@@ -1777,86 +1786,86 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1777,86 +1853,86 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -10005,7 +13303,7 @@ index 0fc03e4..5542d2b 100644 } } -@@ -1885,24 +1894,24 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -1885,24 +1961,24 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) RADEONInfoPtr info = RADEONPTR(pScrn); int i, num; ScreenPtr pScreen = pScrn->pScreen; @@ -10034,7 +13332,7 @@ index 0fc03e4..5542d2b 100644 num = REGION_NUM_RECTS(®ion); -@@ -1919,9 +1928,9 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -1919,9 +1995,9 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) uint32_t src_pitch_offset, dst_pitch_offset, datatype; RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset); @@ -10046,7 +13344,7 @@ index 0fc03e4..5542d2b 100644 RADEONDoPrepareCopyCP(pScrn, src_pitch_offset, dst_pitch_offset, datatype, GXcopy, ~0); -@@ -1931,13 +1940,14 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -1931,13 +2007,14 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) #ifdef USE_XAA if (!info->useEXA) { /* Make sure accel has been properly inited */ @@ -10066,7 +13364,7 @@ index 0fc03e4..5542d2b 100644 } #endif -@@ -1954,23 +1964,23 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -1954,23 +2031,23 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) #ifdef USE_XAA if (!info->useEXA) { @@ -10097,7 +13395,7 @@ index 0fc03e4..5542d2b 100644 } #endif /* DAMAGE */ -@@ -1981,13 +1991,13 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen) +@@ -1981,13 +2058,13 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -10114,7 +13412,7 @@ index 0fc03e4..5542d2b 100644 RADEONDRIRefreshArea(pScrn, pReg); REGION_DESTROY(pScreen, pReg); } -@@ -2000,9 +2010,9 @@ static void RADEONDisablePageFlip(ScreenPtr pScreen) +@@ -2000,9 +2077,9 @@ static void RADEONDisablePageFlip(ScreenPtr pScreen) * -- Field in sarea, plus bumping the window counters. * -- DRM needs to cope with Front-to-Back swapbuffers. */ @@ -10126,7 +13424,7 @@ index 0fc03e4..5542d2b 100644 } static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen) -@@ -2034,9 +2044,9 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) +@@ -2034,9 +2111,9 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) * first so we always start with all free offscreen memory, except * maybe for Xv */ @@ -10139,7 +13437,7 @@ index 0fc03e4..5542d2b 100644 } xf86PurgeUnlockedOffscreenAreas(pScreen); -@@ -2047,7 +2057,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) +@@ -2047,7 +2124,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) * FIXME: This is hideous. What about telling xv "oh btw you have no memory * any more?" -- anholt */ @@ -10148,7 +13446,7 @@ index 0fc03e4..5542d2b 100644 RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr; xf86FreeOffscreenLinear((FBLinearPtr)portPriv->video_memory); portPriv->video_memory = NULL; -@@ -2061,29 +2071,29 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) +@@ -2061,29 +2138,29 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) */ fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth, height @@ -10191,7 +13489,7 @@ index 0fc03e4..5542d2b 100644 xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen " "area for depth buffer and textures, you might " "experience screen corruption\n"); -@@ -2092,7 +2102,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) +@@ -2092,7 +2169,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen) } #endif /* USE_XAA */ @@ -10200,7 +13498,7 @@ index 0fc03e4..5542d2b 100644 RADEONChangeSurfaces(pScrn); RADEONEnablePageFlip(pScreen); -@@ -2108,19 +2118,19 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) +@@ -2108,19 +2185,19 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -10224,7 +13522,7 @@ index 0fc03e4..5542d2b 100644 } #endif } else { -@@ -2131,10 +2141,10 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) +@@ -2131,10 +2208,10 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) #ifdef USE_XAA if (!info->useEXA) @@ -10237,7 +13535,7 @@ index 0fc03e4..5542d2b 100644 RADEONChangeSurfaces(pScrn); -@@ -2154,8 +2164,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num) +@@ -2154,8 +2231,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -10248,7 +13546,7 @@ index 0fc03e4..5542d2b 100644 if (num > 0) { int i; -@@ -2164,8 +2174,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num) +@@ -2164,8 +2241,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num) WindowPtr pWin = ppWin[i]; if (pWin) { @@ -10259,7 +13557,7 @@ index 0fc03e4..5542d2b 100644 } } } -@@ -2178,24 +2188,24 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen) +@@ -2178,24 +2255,24 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen) RADEONInfoPtr info = RADEONPTR(pScrn); if (info->cardType != CARD_PCIE || @@ -10291,7 +13589,7 @@ index 0fc03e4..5542d2b 100644 } -@@ -2207,7 +2217,7 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn) +@@ -2207,7 +2284,7 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn) int ret_size; int num_pages; @@ -10300,7 +13598,7 @@ index 0fc03e4..5542d2b 100644 ret_size = num_pages * sizeof(unsigned int); -@@ -2216,14 +2226,14 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn) +@@ -2216,14 +2293,14 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn) int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) { @@ -10415,7 +13713,7 @@ index fcde08e..0000000 - -#endif diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index f18ad99..c759bd6 100644 +index f18ad99..d414854 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -79,7 +79,7 @@ @@ -10427,6 +13725,31 @@ index f18ad99..c759bd6 100644 #include "sarea.h" #endif +@@ -152,7 +152,6 @@ static const OptionInfoRec RADEONOptions[] = { + { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, + #endif + #endif +- { OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, +@@ -192,6 +191,7 @@ static const OptionInfoRec RADEONOptions[] = { + { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, ++ { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, + { -1, NULL, OPTV_NONE, {0}, FALSE } + }; + +@@ -429,7 +429,7 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR(pScrn); + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); ++ "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); + + #ifndef XSERVER_LIBPCIACCESS + @@ -498,7 +498,7 @@ static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) void RADEONPllErrataAfterIndex(RADEONInfoPtr info) { @@ -10517,7 +13840,67 @@ index f18ad99..c759bd6 100644 #endif /* XF86DRI */ /* Set HDP_APER_CNTL only on cards that are known not to be broken, -@@ -1893,20 +1906,6 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1675,6 +1688,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + info->IsDellServer = FALSE; + info->HasSingleDAC = FALSE; + info->InternalTVOut = TRUE; ++ info->get_hardcoded_edid_from_bios = FALSE; + + for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { + if (info->Chipset == RADEONCards[i].pci_device_id) { +@@ -1692,6 +1706,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + switch (info->Chipset) { + case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ + case PCI_CHIP_RN50_5969: ++ /* Some Sun servers have a hardcoded edid so KVMs work properly */ ++ if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133)) ++ info->get_hardcoded_edid_from_bios = TRUE; + case PCI_CHIP_RV100_QY: + case PCI_CHIP_RV100_QZ: + /* DELL triple-head configuration. */ +@@ -1732,11 +1750,11 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + } + + from = X_PROBED; +- info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; ++ info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; + pScrn->memPhysBase = info->LinearAddr; + if (dev->MemBase) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Linear address override, using 0x%016lx instead of 0x%016lx\n", ++ "Linear address override, using 0x%016lx instead of 0x%016llx\n", + dev->MemBase, + info->LinearAddr); + info->LinearAddr = dev->MemBase; +@@ -1747,7 +1765,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + return FALSE; + } + xf86DrvMsg(pScrn->scrnIndex, from, +- "Linear framebuffer at 0x%016lx\n", info->LinearAddr); ++ "Linear framebuffer at 0x%016llx\n", info->LinearAddr); + + #ifndef XSERVER_LIBPCIACCESS + /* BIOS */ +@@ -1756,14 +1774,14 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + if (dev->BiosBase) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "BIOS address override, using 0x%08lx instead of 0x%08lx\n", +- dev->BiosBase, +- info->BIOSAddr); ++ (unsigned long)dev->BiosBase, ++ (unsigned long)info->BIOSAddr); + info->BIOSAddr = dev->BiosBase; + from = X_CONFIG; + } + if (info->BIOSAddr) { + xf86DrvMsg(pScrn->scrnIndex, from, +- "BIOS at 0x%08lx\n", info->BIOSAddr); ++ "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); + } + #endif + +@@ -1893,20 +1911,6 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) return FALSE; } @@ -10538,7 +13921,7 @@ index f18ad99..c759bd6 100644 return TRUE; } -@@ -1960,6 +1959,25 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -1960,6 +1964,25 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) char *optstr; #endif @@ -10564,7 +13947,7 @@ index f18ad99..c759bd6 100644 info->useEXA = FALSE; if (info->ChipFamily >= CHIP_FAMILY_R600) { -@@ -2032,16 +2050,22 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2032,16 +2055,22 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) { @@ -10588,7 +13971,7 @@ index f18ad99..c759bd6 100644 /* don't need int10 on atom cards. * in theory all radeons, but the older stuff * isn't 100% yet -@@ -2087,10 +2111,19 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2087,17 +2116,26 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) info->directRenderingEnabled = FALSE; info->directRenderingInited = FALSE; @@ -10612,7 +13995,16 @@ index f18ad99..c759bd6 100644 if (xf86IsEntityShared(info->pEnt->index)) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -@@ -2106,19 +2139,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) + "Direct Rendering Disabled -- " +- "Dual-head configuration is not working with " ++ "Zaphod Dual-head configuration is not working with " + "DRI at present.\n" +- "Please use the radeon MergedFB option if you " ++ "Please use the xrandr 1.2 if you " + "want Dual-head with DRI.\n"); + return FALSE; + } +@@ -2106,19 +2144,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) if (info->Chipset == PCI_CHIP_RN50_515E || info->Chipset == PCI_CHIP_RN50_5969 || @@ -10634,7 +14026,7 @@ index f18ad99..c759bd6 100644 return FALSE; } } -@@ -2136,18 +2166,26 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2136,18 +2171,26 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) return FALSE; } @@ -10667,7 +14059,7 @@ index f18ad99..c759bd6 100644 if (info->Chipset == PCI_CHIP_RS400_5A41 || info->Chipset == PCI_CHIP_RS400_5A42 || -@@ -2158,7 +2196,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2158,7 +2201,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) info->Chipset == PCI_CHIP_RS482_5974 || info->Chipset == PCI_CHIP_RS485_5975) { @@ -10676,7 +14068,7 @@ index f18ad99..c759bd6 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); return FALSE; -@@ -2167,25 +2205,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2167,25 +2210,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) "Direct rendering experimental on RS400/Xpress 200 enabled\n"); } @@ -10714,7 +14106,7 @@ index f18ad99..c759bd6 100644 case 4: case 8: case 16: -@@ -2197,24 +2232,24 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2197,24 +2237,24 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) default: xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -10745,7 +14137,7 @@ index f18ad99..c759bd6 100644 case 32: case 64: case 128: -@@ -2223,63 +2258,63 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2223,63 +2263,63 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) default: xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Illegal pci aper size: %d MB\n", @@ -10827,7 +14219,7 @@ index f18ad99..c759bd6 100644 reason = " on r5xx and newer chips.\n"; } else { reason = ""; -@@ -2292,7 +2327,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2292,7 +2332,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) #endif xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", @@ -10836,7 +14228,7 @@ index f18ad99..c759bd6 100644 info->DMAForXv = TRUE; from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) -@@ -2332,15 +2367,15 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2332,15 +2372,15 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) #ifdef XF86DRI if (info->directRenderingEnabled && @@ -10856,7 +14248,33 @@ index f18ad99..c759bd6 100644 info->allowColorTiling = FALSE; return; } -@@ -2994,7 +3029,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, +@@ -2707,11 +2747,14 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), + PCI_DEV_DEV(info->PciInfo), + PCI_DEV_FUNC(info->PciInfo)); +- info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffUL; ++ info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; + info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", ++ (unsigned long long)PCI_REGION_BASE(info->PciInfo, ++ 2, REGION_MEM)); + if (info->pEnt->device->IOBase) { + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, +- "MMIO address override, using 0x%08lx instead of 0x%08lx\n", ++ "MMIO address override, using 0x%08lx instead of 0x%016llx\n", + info->pEnt->device->IOBase, + info->MMIOAddr); + info->MMIOAddr = info->pEnt->device->IOBase; +@@ -2720,7 +2763,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + goto fail1; + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "MMIO registers at 0x%016lx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); ++ "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); + + if(!RADEONMapMMIO(pScrn)) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +@@ -2994,7 +3037,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, int c; #ifdef XF86DRI @@ -10865,7 +14283,7 @@ index f18ad99..c759bd6 100644 #endif if (info->accelOn && pScrn->pScreen) -@@ -3058,7 +3093,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, +@@ -3058,7 +3101,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, } #ifdef XF86DRI @@ -10874,7 +14292,7 @@ index f18ad99..c759bd6 100644 #endif } -@@ -3077,12 +3112,12 @@ static void RADEONBlockHandler(int i, pointer blockData, +@@ -3077,12 +3120,12 @@ static void RADEONBlockHandler(int i, pointer blockData, (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); #if defined(RENDER) && defined(USE_XAA) @@ -10890,7 +14308,7 @@ index f18ad99..c759bd6 100644 #endif } -@@ -3175,17 +3210,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3175,17 +3218,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->accelOn = FALSE; #ifdef USE_XAA @@ -10911,7 +14329,7 @@ index f18ad99..c759bd6 100644 #else xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONScreenInit %lx %ld\n", -@@ -3194,8 +3229,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3194,8 +3237,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (!RADEONMapMem(pScrn)) return FALSE; #ifdef XF86DRI @@ -10922,7 +14340,7 @@ index f18ad99..c759bd6 100644 #endif info->PaletteSavedOnVT = FALSE; -@@ -3249,21 +3284,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3249,21 +3292,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->directRenderingEnabled) { MessageType from; @@ -10949,7 +14367,7 @@ index f18ad99..c759bd6 100644 } -@@ -3276,7 +3311,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3276,7 +3319,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONInitMemoryMap(pScrn); /* empty the surfaces */ @@ -10958,7 +14376,7 @@ index f18ad99..c759bd6 100644 unsigned char *RADEONMMIO = info->MMIO; unsigned int j; for (j = 0; j < 8; j++) { -@@ -3288,14 +3323,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3288,14 +3331,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #ifdef XF86DRI /* Depth moves are disabled by default since they are extremely slow */ @@ -10977,7 +14395,7 @@ index f18ad99..c759bd6 100644 } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Depth moves disabled by default\n"); -@@ -3331,15 +3366,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3331,15 +3374,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, * default, can be overridden with Option "FBTexPercent". * Round down to a whole number of texture regions. */ @@ -10998,7 +14416,7 @@ index f18ad99..c759bd6 100644 } } } -@@ -3356,19 +3391,19 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3356,19 +3399,19 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #if defined(XF86DRI) && defined(USE_XAA) if (!info->useEXA && hasDRI) { @@ -11024,7 +14442,7 @@ index f18ad99..c759bd6 100644 } #endif -@@ -3377,8 +3412,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3377,8 +3420,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, return FALSE; #endif @@ -11036,7 +14454,7 @@ index f18ad99..c759bd6 100644 /* Setup DRI after visuals have been established, but before fbScreenInit is * called. fbScreenInit will eventually call the driver's InitGLXVisuals -@@ -3408,18 +3444,18 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3408,18 +3452,18 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } /* Tell DRI about new memory map */ @@ -11058,7 +14476,7 @@ index f18ad99..c759bd6 100644 if (info->r600_shadow_fb) { info->fb_shadow = xcalloc(1, pScrn->displayWidth * pScrn->virtualY * -@@ -3473,18 +3509,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3473,18 +3517,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; PictureSetSubpixelOrder (pScreen, subPixelOrder); @@ -11083,7 +14501,7 @@ index f18ad99..c759bd6 100644 /* Backing store setup */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -3495,14 +3529,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3495,14 +3537,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* DRI finalisation */ #ifdef XF86DRI if (info->directRenderingEnabled && info->cardType==CARD_PCIE && @@ -11102,7 +14520,7 @@ index f18ad99..c759bd6 100644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[drm] failed set pci gart table size\n"); } -@@ -3519,10 +3553,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3519,10 +3561,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, */ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); @@ -11113,7 +14531,7 @@ index f18ad99..c759bd6 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); /* we might already be in tiled mode, tell drm about it */ -@@ -3620,6 +3650,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3620,6 +3658,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } @@ -11124,7 +14542,7 @@ index f18ad99..c759bd6 100644 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ /* Wrap CloseScreen */ info->CloseScreen = pScreen->CloseScreen; -@@ -3910,7 +3944,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -3910,7 +3952,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) else info->fbLocation = (info->mc_fb_location & 0xffff) << 16; @@ -11133,7 +14551,7 @@ index f18ad99..c759bd6 100644 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); RADEONInitMemMapRegisters(pScrn, save, info); -@@ -3920,14 +3954,14 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -3920,14 +3962,14 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) #ifdef USE_EXA if (info->accelDFS) { @@ -11150,7 +14568,7 @@ index f18ad99..c759bd6 100644 sizeof(gp)) < 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to determine GART area MC location, not using " -@@ -4011,35 +4045,35 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4011,35 +4053,35 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) } #ifdef XF86DRI if (info->directRenderingInited) { @@ -11197,7 +14615,7 @@ index f18ad99..c759bd6 100644 drmsurfalloc.flags = swap_pattern; if (info->tilingEnabled) { -@@ -4048,15 +4082,15 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4048,15 +4090,15 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) else drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; } @@ -11217,7 +14635,7 @@ index f18ad99..c759bd6 100644 &drmsurfalloc, sizeof(drmsurfalloc)); if (retvalue < 0) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -@@ -4081,18 +4115,18 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4081,18 +4123,18 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) } /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ @@ -11240,7 +14658,7 @@ index f18ad99..c759bd6 100644 &drmsurfalloc, sizeof(drmsurfalloc)); if (retvalue < 0) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -@@ -4178,6 +4212,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4178,6 +4220,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); @@ -11248,7 +14666,7 @@ index f18ad99..c759bd6 100644 state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); -@@ -4233,8 +4268,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4233,8 +4276,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); @@ -11259,7 +14677,7 @@ index f18ad99..c759bd6 100644 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); -@@ -4272,8 +4309,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4272,8 +4317,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); @@ -11270,7 +14688,7 @@ index f18ad99..c759bd6 100644 if (IS_DCE3_VARIANT) { /* save DVOA regs */ -@@ -4477,14 +4516,71 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4477,14 +4524,71 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) struct avivo_state *state = &restore->avivo; int i, j; @@ -11347,7 +14765,7 @@ index f18ad99..c759bd6 100644 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); -@@ -4504,7 +4600,9 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4504,7 +4608,9 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); @@ -11357,7 +14775,7 @@ index f18ad99..c759bd6 100644 OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); -@@ -4519,29 +4617,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4519,29 +4625,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); @@ -11388,7 +14806,7 @@ index f18ad99..c759bd6 100644 OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); -@@ -4557,29 +4638,11 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4557,29 +4646,11 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); @@ -11418,7 +14836,7 @@ index f18ad99..c759bd6 100644 if (IS_DCE3_VARIANT) { /* DVOA regs */ OUTREG(0x7080, state->dvoa[0]); -@@ -4699,7 +4762,7 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4699,7 +4770,7 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) } j = 0; @@ -11427,7 +14845,7 @@ index f18ad99..c759bd6 100644 for (i = 0x7800; i <= 0x782c; i += 4) { OUTREG(i, state->daca[j]); OUTREG((i + 0x200), state->dacb[j]); -@@ -4766,8 +4829,31 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4766,8 +4837,31 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(0x6e30, state->dxscl[6]); OUTREG(0x6e34, state->dxscl[7]); @@ -11459,7 +14877,7 @@ index f18ad99..c759bd6 100644 } static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) -@@ -5045,7 +5131,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5045,7 +5139,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) Bool tilingOld = info->tilingEnabled; Bool ret; #ifdef XF86DRI @@ -11468,7 +14886,7 @@ index f18ad99..c759bd6 100644 if (CPStarted) { DRILock(pScrn->pScreen, 0); -@@ -5060,7 +5146,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5060,7 +5154,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; #ifdef XF86DRI if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { @@ -11477,7 +14895,7 @@ index f18ad99..c759bd6 100644 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[drm] failed changing tiling status\n"); -@@ -5170,7 +5256,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) +@@ -5170,7 +5264,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) unsigned char *RADEONMMIO = info->MMIO; int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; #ifdef XF86DRI @@ -11486,7 +14904,7 @@ index f18ad99..c759bd6 100644 XF86DRISAREAPtr pSAREA; #endif -@@ -5209,7 +5295,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) +@@ -5209,7 +5303,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) #if 0 /* try to get rid of flickering when scrolling at least for 2d */ #ifdef XF86DRI @@ -11495,7 +14913,7 @@ index f18ad99..c759bd6 100644 #endif crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; #endif -@@ -5266,7 +5352,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) +@@ -5266,7 +5360,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) } if (pSAREAPriv->pfCurrentPage == 1) { @@ -11504,7 +14922,7 @@ index f18ad99..c759bd6 100644 } } #endif -@@ -5290,7 +5376,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5290,7 +5384,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) xf86CrtcPtr crtc = output->crtc; #ifdef XF86DRI @@ -11513,7 +14931,7 @@ index f18ad99..c759bd6 100644 #endif if (info->accelOn) -@@ -5307,7 +5393,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5307,7 +5401,7 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) #ifdef XF86DRI @@ -11522,7 +14940,7 @@ index f18ad99..c759bd6 100644 #endif } -@@ -5318,26 +5404,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5318,26 +5412,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -11551,7 +14969,7 @@ index f18ad99..c759bd6 100644 pInt = xf86InitInt10 (info->pEnt->index); if (pInt) { pInt->num = 0xe6; -@@ -5382,10 +5460,10 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5382,10 +5468,10 @@ Bool RADEONEnterVT(int scrnIndex, int flags) #ifdef XF86DRI if (info->directRenderingEnabled) { if (info->cardType == CARD_PCIE && @@ -11564,7 +14982,7 @@ index f18ad99..c759bd6 100644 } /* get the DRI back into shape after resume */ -@@ -5433,18 +5511,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5433,18 +5519,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) RADEONCP_STOP(pScrn, info); if (info->cardType == CARD_PCIE && @@ -11590,7 +15008,7 @@ index f18ad99..c759bd6 100644 i = 0; -@@ -5501,12 +5579,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5501,12 +5587,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #ifdef XF86DRI #ifdef DAMAGE @@ -11607,7 +15025,7 @@ index f18ad99..c759bd6 100644 } #endif -@@ -5514,9 +5592,9 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5514,9 +5600,9 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #endif #ifdef USE_XAA @@ -11620,7 +15038,7 @@ index f18ad99..c759bd6 100644 } #endif /* USE_XAA */ -@@ -5527,21 +5605,21 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5527,21 +5613,21 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Disposing accel...\n"); #ifdef USE_EXA @@ -11653,7 +15071,7 @@ index f18ad99..c759bd6 100644 diff --git a/src/radeon_drm.h b/src/radeon_drm.h new file mode 100644 -index 0000000..66cefb7 +index 0000000..54bc234 --- /dev/null +++ b/src/radeon_drm.h @@ -0,0 +1,756 @@ @@ -12203,8 +15621,8 @@ index 0000000..66cefb7 + unsigned int depth_offset, depth_pitch; + + /* DEPRECATED commented out below to allow for -Werror build */ -+ unsigned long fb_offset /*DEPRECATED*/; /* deprecated, driver asks hardware */ -+ unsigned long mmio_offset /*DEPRECATED*/; /* deprecated, driver asks hardware */ ++ unsigned long fb_offset; /* deprecated, driver asks hardware */ ++ unsigned long mmio_offset; /* deprecated, driver asks hardware */ + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; @@ -12240,7 +15658,7 @@ index 0000000..66cefb7 + unsigned int clear_depth; + unsigned int color_mask; + unsigned int depth_mask; /* misnamed field: should be stencil */ -+ drm_radeon_clear_rect_t __user *depth_boxes; ++ drm_radeon_clear_rect_t *depth_boxes; +} drm_radeon_clear_t; + +typedef struct drm_radeon_vertex { @@ -12266,9 +15684,9 @@ index 0000000..66cefb7 + int idx; /* Index of vertex buffer */ + int discard; /* Client finished with buffer? */ + int nr_states; -+ drm_radeon_state_t __user *state; ++ drm_radeon_state_t *state; + int nr_prims; -+ drm_radeon_prim_t __user *prim; ++ drm_radeon_prim_t *prim; +} drm_radeon_vertex2_t; + +/* v1.3 - obsoletes drm_radeon_vertex2 @@ -12283,15 +15701,15 @@ index 0000000..66cefb7 + */ +typedef struct drm_radeon_cmd_buffer { + int bufsz; -+ char __user *buf; ++ char *buf; + int nbox; -+ struct drm_clip_rect __user *boxes; ++ struct drm_clip_rect *boxes; +} drm_radeon_cmd_buffer_t; + +typedef struct drm_radeon_tex_image { + unsigned int x, y; /* Blit coordinates */ + unsigned int width, height; -+ const void __user *data; ++ const void *data; +} drm_radeon_tex_image_t; + +typedef struct drm_radeon_texture { @@ -12300,11 +15718,11 @@ index 0000000..66cefb7 + int format; + int width; /* Texture image coordinates */ + int height; -+ drm_radeon_tex_image_t __user *image; ++ drm_radeon_tex_image_t *image; +} drm_radeon_texture_t; + +typedef struct drm_radeon_stipple { -+ unsigned int __user *mask; ++ unsigned int *mask; +} drm_radeon_stipple_t; + +typedef struct drm_radeon_indirect { @@ -12345,7 +15763,7 @@ index 0000000..66cefb7 + +typedef struct drm_radeon_getparam { + int param; -+ void __user *value; ++ void *value; +} drm_radeon_getparam_t; + +/* 1.6: Set up a memory manager for regions of shared memory: @@ -12357,7 +15775,7 @@ index 0000000..66cefb7 + int region; + int alignment; + int size; -+ int __user *region_offset; /* offset from start of fb or GART */ ++ int *region_offset; /* offset from start of fb or GART */ +} drm_radeon_mem_alloc_t; + +typedef struct drm_radeon_mem_free { @@ -12374,7 +15792,7 @@ index 0000000..66cefb7 +/* 1.6: Userspace can request & wait on irq's: + */ +typedef struct drm_radeon_irq_emit { -+ int __user *irq_seq; ++ int *irq_seq; +} drm_radeon_irq_emit_t; + +typedef struct drm_radeon_irq_wait { @@ -12414,7 +15832,7 @@ index 0000000..66cefb7 + +#endif diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index f461f3c..0f86fdd 100644 +index f461f3c..c4bc1bb 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -36,14 +36,11 @@ @@ -12446,7 +15864,41 @@ index f461f3c..0f86fdd 100644 RADEON_FALLBACK(("Bad offset 0x%08x\n", offset)); pitch = pitch >> 6; -@@ -237,14 +234,14 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) +@@ -195,6 +192,33 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) + return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); + } + ++/* ++ * Used for vblank render stalling. ++ * Ideally we'd have one pixmap per crtc. ++ * syncing per-blit is unrealistic so, ++ * we sync to whichever crtc has a larger area. ++ */ ++int RADEONBiggerCrtcArea(PixmapPtr pPix) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++ int c, crtc_num = -1, area = 0; ++ ++ for (c = 0; c < xf86_config->num_crtc; c++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[c]; ++ ++ if (!crtc->enabled) ++ continue; ++ ++ if ((crtc->mode.HDisplay * crtc->mode.VDisplay) > area) { ++ area = crtc->mode.HDisplay * crtc->mode.VDisplay; ++ crtc_num = c; ++ } ++ } ++ ++ return crtc_num; ++} ++ + #if X_BYTE_ORDER == X_BIG_ENDIAN + + static unsigned long swapper_surfaces[3]; +@@ -237,14 +261,14 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) } #if defined(XF86DRI) if (info->directRenderingEnabled && info->allowColorTiling) { @@ -12463,7 +15915,7 @@ index f461f3c..0f86fdd 100644 &drmsurfalloc, sizeof(drmsurfalloc)); if (rc < 0) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -@@ -280,10 +277,10 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -280,10 +304,10 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) return; #if defined(XF86DRI) if (info->directRenderingEnabled && info->allowColorTiling) { @@ -12476,42 +15928,48 @@ index f461f3c..0f86fdd 100644 &drmsurffree, sizeof(drmsurffree)); swapper_surfaces[index] = 0; return; -@@ -302,7 +299,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) - do { \ - uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ +@@ -298,40 +322,6 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) + + #endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ + +-#define RADEON_SWITCH_TO_2D() \ +-do { \ +- uint32_t wait_until = 0; \ +- BEGIN_ACCEL(1); \ - switch (info->engineMode) { \ -+ switch (info->accel_state->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \ - case EXA_ENGINEMODE_3D: \ -@@ -312,14 +309,14 @@ do { \ - } \ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ - FINISH_ACCEL(); \ +- case EXA_ENGINEMODE_UNKNOWN: \ +- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \ +- case EXA_ENGINEMODE_3D: \ +- wait_until |= RADEON_WAIT_3D_IDLECLEAN; \ +- case EXA_ENGINEMODE_2D: \ +- break; \ +- } \ +- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ +- FINISH_ACCEL(); \ - info->engineMode = EXA_ENGINEMODE_2D; \ -+ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ - } while (0); - - #define RADEON_SWITCH_TO_3D() \ - do { \ - uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ +-} while (0); +- +-#define RADEON_SWITCH_TO_3D() \ +-do { \ +- uint32_t wait_until = 0; \ +- BEGIN_ACCEL(1); \ - switch (info->engineMode) { \ -+ switch (info->accel_state->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ - case EXA_ENGINEMODE_2D: \ -@@ -329,7 +326,7 @@ do { \ - } \ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ - FINISH_ACCEL(); \ +- case EXA_ENGINEMODE_UNKNOWN: \ +- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ +- case EXA_ENGINEMODE_2D: \ +- wait_until |= RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE; \ +- case EXA_ENGINEMODE_3D: \ +- break; \ +- } \ +- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ +- FINISH_ACCEL(); \ - info->engineMode = EXA_ENGINEMODE_3D; \ -+ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ - } while (0); - +-} while (0); +- #define ENTER_DRAW(x) TRACE -@@ -352,6 +349,7 @@ do { \ + #define LEAVE_DRAW(x) TRACE + /***********************************************************************/ +@@ -352,6 +342,7 @@ do { \ #undef ACCEL_PREAMBLE #undef BEGIN_ACCEL #undef OUT_ACCEL_REG @@ -12519,7 +15977,7 @@ index f461f3c..0f86fdd 100644 #undef FINISH_ACCEL #ifdef XF86DRI -@@ -371,6 +369,13 @@ do { \ +@@ -371,6 +362,13 @@ do { \ #endif #include "radeon_exa_funcs.c" @@ -12533,7 +15991,7 @@ index f461f3c..0f86fdd 100644 #endif /* XF86DRI */ /* -@@ -386,12 +391,12 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -386,12 +384,12 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) int screen_size; int byteStride = pScrn->displayWidth * cpp; @@ -12549,7 +16007,7 @@ index f461f3c..0f86fdd 100644 return FALSE; /* Need to adjust screen size for 16 line tiles, and then make it align to. -@@ -402,53 +407,52 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -402,53 +400,52 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) else screen_size = pScrn->virtualY * byteStride; @@ -12631,7 +16089,7 @@ index f461f3c..0f86fdd 100644 /* Reserve a static area for the back buffer the same size as the * visible screen. XXX: This would be better initialized in ati_dri.c -@@ -456,49 +460,49 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -456,49 +453,49 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) * don't last through VT switches, while the kernel's understanding of * offscreen locations does. */ @@ -12704,7 +16162,7 @@ index f461f3c..0f86fdd 100644 } } else #endif /* XF86DRI */ -@@ -508,8 +512,8 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -508,8 +505,8 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Will use %ld kb for X Server offscreen at offset 0x%08lx\n", @@ -12716,7 +16174,7 @@ index f461f3c..0f86fdd 100644 return TRUE; } diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 56de23e..62224d0 100644 +index 56de23e..55710ff 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -65,7 +65,7 @@ FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen) @@ -12744,7 +16202,16 @@ index 56de23e..62224d0 100644 } static Bool -@@ -172,8 +172,8 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, +@@ -129,6 +129,8 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) + + TRACE; + ++ FUNC_NAME(RADEONWaitForVLine)(pScrn, pPix, RADEONBiggerCrtcArea(pPix), y1, y2, info->accel_state->vsync); ++ + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DST_Y_X, (y1 << 16) | x1); + OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1)); +@@ -172,8 +174,8 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, RADEON_GMC_CLR_CMP_CNTL_DIS); OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); OUT_ACCEL_REG(RADEON_DP_CNTL, @@ -12755,7 +16222,7 @@ index 56de23e..62224d0 100644 OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset); OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset); FINISH_ACCEL(); -@@ -190,8 +190,8 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -190,8 +192,8 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, TRACE; @@ -12766,7 +16233,7 @@ index 56de23e..62224d0 100644 if (pDst->drawable.bitsPerPixel == 24) RADEON_FALLBACK(("24bpp unsupported")); -@@ -219,11 +219,11 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, +@@ -219,15 +221,17 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, TRACE; @@ -12780,7 +16247,32 @@ index 56de23e..62224d0 100644 srcY += h - 1; dstY += h - 1; } -@@ -401,9 +401,9 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + ++ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), dstY, dstY + h, info->accel_state->vsync); ++ + BEGIN_ACCEL(3); + + OUT_ACCEL_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX); +@@ -264,7 +268,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + unsigned int hpass; + uint32_t buf_pitch, dst_pitch_off; + #endif +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; + unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | +@@ -284,6 +288,9 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + ACCEL_PREAMBLE(); + + RADEON_SWITCH_TO_2D(); ++ ++ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), y, y + h, info->accel_state->vsync); ++ + while ((buf = RADEONHostDataBlit(pScrn, + cpp, w, dst_pitch_off, &buf_pitch, + x, &y, (unsigned int*)&h, &hpass)) != 0) { +@@ -401,9 +408,9 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8; int hpass = min(h, scratch->total/2 / scratch_pitch); uint32_t scratch_pitch_offset = scratch_pitch << 16 @@ -12792,7 +16284,7 @@ index 56de23e..62224d0 100644 ACCEL_PREAMBLE(); RADEON_SWITCH_TO_2D(); -@@ -450,7 +450,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -450,7 +457,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, * we'd really need is a way to reliably wait for the host interface * to be done with pushing the data to the host. */ @@ -12801,7 +16293,7 @@ index 56de23e..62224d0 100644 && (i++ < RADEON_TIMEOUT)) ; -@@ -473,10 +473,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -473,10 +480,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, indirect.start = indirect.end = 0; indirect.discard = 1; @@ -12815,7 +16307,7 @@ index 56de23e..62224d0 100644 return TRUE; } -@@ -522,35 +522,35 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -522,35 +529,35 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) { RINFO_FROM_SCREEN(pScreen); @@ -12869,7 +16361,7 @@ index 56de23e..62224d0 100644 #ifdef RENDER if (info->RenderAccel) { -@@ -565,11 +565,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -565,11 +572,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R300/R400/R500 type cards.\n"); @@ -12885,7 +16377,7 @@ index 56de23e..62224d0 100644 } else xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n"); } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || -@@ -578,19 +578,19 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -578,19 +585,19 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) (info->ChipFamily == CHIP_FAMILY_R200)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R200 type cards.\n"); @@ -12913,7 +16405,7 @@ index 56de23e..62224d0 100644 } } #endif -@@ -598,17 +598,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -598,17 +605,23 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) #if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); @@ -12927,6 +16419,12 @@ index 56de23e..62224d0 100644 #endif - info->exa->maxY = 8192; + info->accel_state->exa->maxY = 8192; ++ ++ if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n"); ++ info->accel_state->vsync = TRUE; ++ } else ++ info->accel_state->vsync = FALSE; RADEONEngineInit(pScrn); @@ -12938,7 +16436,7 @@ index 56de23e..62224d0 100644 } exaMarkSync(pScreen); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 4736e4f..97199ae 100644 +index 4736e4f..55e55be 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -56,15 +56,6 @@ @@ -13037,12 +16535,14 @@ index 4736e4f..97199ae 100644 TRACE; - if (!info->XInited3D) -+ if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - +- RADEONInit3DEngine(pScrn); +- if (!RADEONGetDestFormat(pDstPicture, &dst_format)) return FALSE; ++ if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha) ++ RADEON_FALLBACK("Can't dst alpha blend A8\n"); ++ if (pMask) - has_mask = TRUE; + info->accel_state->has_mask = TRUE; @@ -13052,7 +16552,16 @@ index 4736e4f..97199ae 100644 pixel_shift = pDst->drawable.bitsPerPixel >> 4; -@@ -569,7 +565,7 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, +@@ -560,6 +556,8 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, + if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) + return FALSE; + ++ RADEON_SWITCH_TO_3D(); ++ + if (!FUNC_NAME(R100TextureSetup)(pSrcPicture, pSrc, 0)) + return FALSE; + pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; +@@ -569,11 +567,9 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, return FALSE; pp_cntl |= RADEON_TEX_1_ENABLE; } else { @@ -13060,7 +16569,11 @@ index 4736e4f..97199ae 100644 + info->accel_state->is_transform[1] = FALSE; } - RADEON_SWITCH_TO_3D(); +- RADEON_SWITCH_TO_3D(); +- + BEGIN_ACCEL(8); + OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl); + OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE); @@ -670,7 +666,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, uint32_t txfilter, txformat, txoffset, txpitch; int w = pPict->pDrawable->width; @@ -13101,12 +16614,14 @@ index 4736e4f..97199ae 100644 TRACE; - if (!info->XInited3D) -+ if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - +- RADEONInit3DEngine(pScrn); +- if (!RADEONGetDestFormat(pDstPicture, &dst_format)) return FALSE; ++ if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha) ++ RADEON_FALLBACK("Can't dst alpha blend A8\n"); ++ if (pMask) - has_mask = TRUE; + info->accel_state->has_mask = TRUE; @@ -13116,7 +16631,16 @@ index 4736e4f..97199ae 100644 pixel_shift = pDst->drawable.bitsPerPixel >> 4; -@@ -866,7 +863,7 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -857,6 +854,8 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, + if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) + return FALSE; + ++ RADEON_SWITCH_TO_3D(); ++ + if (!FUNC_NAME(R200TextureSetup)(pSrcPicture, pSrc, 0)) + return FALSE; + pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; +@@ -866,11 +865,9 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, return FALSE; pp_cntl |= RADEON_TEX_1_ENABLE; } else { @@ -13124,7 +16648,11 @@ index 4736e4f..97199ae 100644 + info->accel_state->is_transform[1] = FALSE; } - RADEON_SWITCH_TO_3D(); +- RADEON_SWITCH_TO_3D(); +- + BEGIN_ACCEL(11); + + OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl); @@ -1045,15 +1042,15 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, */ txformat0 |= R300_TXPITCH_EN; @@ -13159,14 +16687,13 @@ index 4736e4f..97199ae 100644 } return TRUE; -@@ -1191,16 +1188,16 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1191,16 +1188,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, TRACE; - if (!info->XInited3D) -+ if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - +- RADEONInit3DEngine(pScrn); +- if (!R300GetDestFormat(pDstPicture, &dst_format)) return FALSE; @@ -13179,7 +16706,16 @@ index 4736e4f..97199ae 100644 pixel_shift = pDst->drawable.bitsPerPixel >> 4; -@@ -1230,13 +1227,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1221,6 +1215,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) + return FALSE; + ++ RADEON_SWITCH_TO_3D(); ++ + if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0)) + return FALSE; + txenable = R300_TEX_0_ENABLE; +@@ -1230,13 +1226,11 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, return FALSE; txenable |= R300_TEX_1_ENABLE; } else { @@ -13187,15 +16723,15 @@ index 4736e4f..97199ae 100644 + info->accel_state->is_transform[1] = FALSE; } - RADEON_SWITCH_TO_3D(); - +- RADEON_SWITCH_TO_3D(); +- /* setup the VAP */ - if (info->has_tcl) { + if (info->accel_state->has_tcl) { if (pMask) BEGIN_ACCEL(8); else -@@ -1296,7 +1293,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1296,7 +1290,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, * - Xv * Here we select the offset of the vertex program we want to use */ @@ -13204,24 +16740,76 @@ index 4736e4f..97199ae 100644 if (pMask) { OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, ((0 << R300_PVS_FIRST_INST_SHIFT) | -@@ -1419,7 +1416,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1419,8 +1413,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, /* setup the rasterizer, load FS */ - BEGIN_ACCEL(9); -+ BEGIN_ACCEL(10); if (pMask) { ++ BEGIN_ACCEL(16); /* 4 components: 2 for tex0, 2 for tex1 */ OUT_ACCEL_REG(R300_RS_COUNT, -@@ -1461,6 +1458,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | +@@ -1440,7 +1434,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + R300_TEX_START(0) | + R300_TEX_SIZE(1) | + R300_RGBA_OUT)); ++ ++ + } else { ++ BEGIN_ACCEL(15); + /* 2 components: 2 for tex0 */ + OUT_ACCEL_REG(R300_RS_COUNT, + ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | +@@ -1459,13 +1456,45 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + R300_TEX_START(0) | + R300_TEX_SIZE(0) | R300_RGBA_OUT)); ++ } ++ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, ++ (R300_ALU_START(0) | ++ R300_ALU_SIZE(0) | ++ R300_TEX_START(0) | ++ R300_TEX_SIZE(0))); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, ++ (R300_ALU_START(0) | ++ R300_ALU_SIZE(0) | ++ R300_TEX_START(0) | ++ R300_TEX_SIZE(0))); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, ++ (R300_ALU_START(0) | ++ R300_ALU_SIZE(0) | ++ R300_TEX_START(0) | ++ R300_TEX_SIZE(0))); ++ + OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ /* shader output swizzling */ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); -@@ -1474,7 +1472,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +- /* tex inst for src texture is pre-loaded in RADEONInit3DEngine() */ +- /* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */ ++ /* tex inst for src texture */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(0), ++ (R300_TEX_SRC_ADDR(0) | ++ R300_TEX_DST_ADDR(0) | ++ R300_TEX_ID(0) | ++ R300_TEX_INST(R300_TEX_INST_LD))); ++ ++ if (pMask) { ++ /* tex inst for mask texture */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(1), ++ (R300_TEX_SRC_ADDR(1) | ++ R300_TEX_DST_ADDR(1) | ++ R300_TEX_ID(1) | ++ R300_TEX_INST(R300_TEX_INST_LD))); ++ } + + /* RGB inst + * temp addresses for texture inputs +@@ -1474,7 +1503,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, * R300_ALU_RGB_OMASK - output components to write * R300_ALU_RGB_TARGET_A - render target */ @@ -13230,7 +16818,7 @@ index 4736e4f..97199ae 100644 (R300_ALU_RGB_ADDR0(0) | R300_ALU_RGB_ADDR1(1) | R300_ALU_RGB_ADDR2(0) | -@@ -1486,7 +1484,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1486,7 +1515,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, /* RGB inst * ALU operation */ @@ -13239,7 +16827,7 @@ index 4736e4f..97199ae 100644 (R300_ALU_RGB_SEL_A(src_color) | R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | R300_ALU_RGB_SEL_B(mask_color) | -@@ -1503,7 +1501,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1503,7 +1532,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, * R300_ALU_ALPHA_OMASK - output components to write * R300_ALU_ALPHA_TARGET_A - render target */ @@ -13248,7 +16836,7 @@ index 4736e4f..97199ae 100644 (R300_ALU_ALPHA_ADDR0(0) | R300_ALU_ALPHA_ADDR1(1) | R300_ALU_ALPHA_ADDR2(0) | -@@ -1514,7 +1512,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1514,7 +1543,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, /* Alpha inst * ALU operation */ @@ -13257,7 +16845,7 @@ index 4736e4f..97199ae 100644 (R300_ALU_ALPHA_SEL_A(src_alpha) | R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | R300_ALU_ALPHA_SEL_B(mask_alpha) | -@@ -1633,7 +1631,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1633,7 +1662,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, break; } @@ -13266,7 +16854,7 @@ index 4736e4f..97199ae 100644 if (pMask) { /* 4 components: 2 for tex0, 2 for tex1 */ OUT_ACCEL_REG(R300_RS_COUNT, -@@ -1662,12 +1660,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1662,12 +1691,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); } @@ -13281,7 +16869,7 @@ index 4736e4f..97199ae 100644 /* tex inst for src texture */ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_RGB_WMASK_R | -@@ -1739,7 +1738,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1739,7 +1769,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); } else { BEGIN_ACCEL(13); @@ -13290,7 +16878,41 @@ index 4736e4f..97199ae 100644 /* tex inst for src texture */ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | -@@ -1936,20 +1935,20 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +@@ -1830,6 +1860,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + FINISH_ACCEL(); + } + ++ /* Clear out scissoring */ ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | ++ (0 << R300_SCISSOR_Y_SHIFT))); ++ OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | ++ (8191 << R300_SCISSOR_Y_SHIFT))); ++ FINISH_ACCEL(); ++ + BEGIN_ACCEL(3); + + OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); +@@ -1840,11 +1878,16 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + + FINISH_ACCEL(); + ++ BEGIN_ACCEL(1); ++ if (info->accel_state->has_mask) ++ OUT_ACCEL_REG(R300_VAP_VTX_SIZE, 6); ++ else ++ OUT_ACCEL_REG(R300_VAP_VTX_SIZE, 4); ++ FINISH_ACCEL(); ++ + return TRUE; + } + +-#define VTX_COUNT_MASK 6 +-#define VTX_COUNT 4 + + #ifdef ACCEL_CP + +@@ -1936,100 +1979,107 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, maskBottomRight.x = IntToxFixed(maskX + w); maskBottomRight.y = IntToxFixed(maskY + h); @@ -13318,11 +16940,19 @@ index 4736e4f..97199ae 100644 } - if (has_mask) +- vtx_count = VTX_COUNT_MASK; + if (info->accel_state->has_mask) - vtx_count = VTX_COUNT_MASK; ++ vtx_count = 6; else - vtx_count = VTX_COUNT; -@@ -1962,21 +1961,21 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +- vtx_count = VTX_COUNT; ++ vtx_count = 4; + +- if (IS_R300_3D || IS_R500_3D) { +- BEGIN_ACCEL(1); +- OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); +- FINISH_ACCEL(); +- } ++ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, RADEONBiggerCrtcArea(pDst), dstY, dstY + h, info->accel_state->vsync); #ifdef ACCEL_CP if (info->ChipFamily < CHIP_FAMILY_R200) { @@ -13345,27 +16975,36 @@ index 4736e4f..97199ae 100644 RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); +- } else { +- if (IS_R300_3D || IS_R500_3D) +- BEGIN_RING(4 * vtx_count + 4); +- else +- BEGIN_RING(4 * vtx_count + 2); +- + (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - } else { - if (IS_R300_3D || IS_R500_3D) - BEGIN_RING(4 * vtx_count + 4); -@@ -1985,7 +1984,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, - ++ } else if (IS_R300_3D || IS_R500_3D) { ++ BEGIN_RING(4 * vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 4 * vtx_count)); - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | + OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ++ } else { ++ BEGIN_RING(3 * vtx_count + 2); ++ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, ++ 3 * vtx_count)); ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | ++ RADEON_CP_VC_CNTL_PRIM_WALK_RING | ++ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } -@@ -1993,43 +1992,49 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + #else /* ACCEL_CP */ if (IS_R300_3D || IS_R500_3D) BEGIN_ACCEL(2 + vtx_count * 4); -+ else if (info->ChipFamily < CHIP_FAMILY_R200) -+ BEGIN_ACCEL(1 + vtx_count * 3); else - BEGIN_ACCEL(1 + vtx_count * 4); +- BEGIN_ACCEL(1 + vtx_count * 4); ++ BEGIN_ACCEL(1 + vtx_count * 3); - if (info->ChipFamily < CHIP_FAMILY_R200) { - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | @@ -13376,12 +17015,16 @@ index 4736e4f..97199ae 100644 - 4 << RADEON_VF_NUM_VERTICES_SHIFT)); - } else { + (3 << RADEON_VF_NUM_VERTICES_SHIFT))); -+ else ++ else if (IS_R300_3D || IS_R500_3D) OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | RADEON_VF_PRIM_WALK_DATA | - 4 << RADEON_VF_NUM_VERTICES_SHIFT)); - } + (4 << RADEON_VF_NUM_VERTICES_SHIFT))); ++ else ++ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | ++ RADEON_VF_PRIM_WALK_DATA | ++ (3 << RADEON_VF_NUM_VERTICES_SHIFT))); + #endif @@ -13390,7 +17033,7 @@ index 4736e4f..97199ae 100644 - xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], - xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); + if (info->accel_state->has_mask) { -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { ++ if (IS_R300_3D || IS_R500_3D) { + VTX_OUT_MASK((float)dstX, (float)dstY, + xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0], + xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1], xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1]); @@ -13413,7 +17056,7 @@ index 4736e4f..97199ae 100644 } else { - VTX_OUT((float)dstX, (float)dstY, - xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { ++ if (IS_R300_3D || IS_R500_3D) { + VTX_OUT((float)dstX, (float)dstY, + xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]); + } @@ -13429,7 +17072,7 @@ index 4736e4f..97199ae 100644 } if (IS_R300_3D || IS_R500_3D) -@@ -2055,8 +2060,9 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -2055,8 +2105,9 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, { int tileSrcY, tileMaskY, tileDstY; int remainingHeight; @@ -13441,7 +17084,7 @@ index 4736e4f..97199ae 100644 FUNC_NAME(RadeonCompositeTile)(pDst, srcX, srcY, maskX, maskY, -@@ -2067,7 +2073,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -2067,7 +2118,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, /* Tiling logic borrowed from exaFillRegionTiled */ @@ -13450,7 +17093,7 @@ index 4736e4f..97199ae 100644 tileMaskY = maskY; tileDstY = dstY; -@@ -2075,18 +2081,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -2075,18 +2126,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, while (remainingHeight > 0) { int remainingWidth = width; int tileSrcX, tileMaskX, tileDstX; @@ -13472,6 +17115,16 @@ index 4736e4f..97199ae 100644 if (w > remainingWidth) w = remainingWidth; remainingWidth -= w; +@@ -2115,7 +2166,8 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) + ENTER_DRAW(0); + + if (IS_R300_3D || IS_R500_3D) { +- BEGIN_ACCEL(2); ++ BEGIN_ACCEL(3); ++ OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); + OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); + } else + BEGIN_ACCEL(1); diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c new file mode 100644 index 0000000..2a9ee94 @@ -13632,8 +17285,91 @@ index afe442e..f19bc3e 100644 #define RADEON_BIOS8(v) (info->VBIOS[v]) #define RADEON_BIOS16(v) (info->VBIOS[v] | \ (info->VBIOS[(v) + 1] << 8)) +diff --git a/src/radeon_modes.c b/src/radeon_modes.c +index 2c72395..5cd4e29 100644 +--- a/src/radeon_modes.c ++++ b/src/radeon_modes.c +@@ -186,6 +186,65 @@ static DisplayModePtr RADEONFPNativeMode(xf86OutputPtr output) + return new; + } + ++#if defined(__powerpc__) ++/* Apple eMacs need special modes for the internal CRT, e.g., ++ * Modeline "640x480" 62.12 640 680 752 864 480 481 484 521 +HSync +Vsync ++ * Modeline "800x600" 76.84 800 848 936 1072 600 601 604 640 +HSync +Vsync ++ * Modeline "1024x768" 99.07 1024 1088 1200 1376 768 769 772 809 +HSync +Vsync ++ * Modeline "1152x864" 112.36 1152 1224 1352 1552 864 865 868 905 +HSync +Vsync ++ * Modeline "1280x960" 124.54 1280 1368 1504 1728 960 961 964 1001 +HSync +Vsync ++ */ ++static DisplayModePtr RADEONeMacModes(xf86OutputPtr output) ++{ ++ ScrnInfoPtr pScrn = output->scrn; ++ DisplayModePtr last=NULL, new=NULL, first=NULL; ++ int i, *modep; ++ static const char *modenames[5] = { ++ "640x480", "800x600", "1024x768", "1152x864", "1280x960" ++ }; ++ static int modes[9*5] = { ++ 62120, 640, 680, 752, 864, 480, 481, 484, 521, ++ 76840, 800, 848, 936, 1072, 600, 601, 604, 640, ++ 99070, 1024, 1088, 1200, 1376, 768, 769, 772, 809, ++ 112360, 1152, 1224, 1352, 1552, 864, 865, 868, 905, ++ 124540, 1280, 1368, 1504, 1728, 960, 961, 964, 1001 ++ }; ++ modep = modes; ++ ++ for (i=0; i<5; i++) { ++ new = xnfcalloc(1, sizeof (DisplayModeRec)); ++ if (new) { ++ new->name = xnfalloc(strlen(modenames[i]) + 1); ++ strcpy(new->name, modenames[i]); ++ new->Clock = *modep++; ++ ++ new->HDisplay = *modep++; ++ new->HSyncStart = *modep++; ++ new->HSyncEnd = *modep++; ++ new->HTotal = *modep++; ++ ++ new->VDisplay = *modep++; ++ new->VSyncStart = *modep++; ++ new->VSyncEnd = *modep++; ++ new->VTotal = *modep++; ++ ++ new->Flags = 0; ++ new->type = M_T_DRIVER; ++ if (i==2) ++ new->type |= M_T_PREFERRED; ++ new->next = NULL; ++ new->prev = last; ++ if (last) last->next = new; ++ last = new; ++ if (!first) first = new; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added eMac mode %s\n", modenames[i]); ++ } ++ } ++ ++ return first; ++} ++#endif ++ + /* this function is basically a hack to add the screen modes */ + static void RADEONAddScreenModes(xf86OutputPtr output, DisplayModePtr *modeList) + { +@@ -284,6 +343,12 @@ RADEONProbeOutputModes(xf86OutputPtr output) + } else { + if (output->MonInfo) + modes = xf86OutputGetEDIDModes (output); ++#if defined(__powerpc__) ++ if ((info->MacModel == RADEON_MAC_EMAC) && ++ (radeon_output->DACType == DAC_PRIMARY) && ++ (modes == NULL)) ++ modes = RADEONeMacModes(output); ++#endif + if (modes == NULL) { + if ((radeon_output->type == OUTPUT_LVDS) && info->IsAtomBios) { + atomBiosResult = RHDAtomBiosFunc(pScrn->scrnIndex, diff --git a/src/radeon_output.c b/src/radeon_output.c -index 7b89d66..8c794fb 100644 +index 7b89d66..5924c81 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -173,9 +173,6 @@ static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = @@ -13744,7 +17480,7 @@ index 7b89d66..8c794fb 100644 static RADEONMonitorType radeon_ddc_connected(xf86OutputPtr output) { -@@ -304,8 +221,20 @@ radeon_ddc_connected(xf86OutputPtr output) +@@ -304,11 +221,28 @@ radeon_ddc_connected(xf86OutputPtr output) xf86MonPtr MonInfo = NULL; RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -13758,16 +17494,26 @@ index 7b89d66..8c794fb 100644 + (radeon_output->ddc_i2c.mask_clk_reg == RADEON_GPIO_VGA_DDC) && + info->IsAtomBios) + MonInfo = radeon_atom_get_edid(output); -+ else { ++ else if (info->get_hardcoded_edid_from_bios) { ++ MonInfo = RADEONGetHardCodedEDIDFromBIOS(output); ++ if (MonInfo == NULL) { ++ RADEONI2CDoLock(output, TRUE); ++ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); ++ RADEONI2CDoLock(output, FALSE); ++ } ++ } else { + RADEONI2CDoLock(output, TRUE); + MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); + RADEONI2CDoLock(output, FALSE); + } + } if (MonInfo) { - if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) - xf86OutputSetEDID(output, MonInfo); -@@ -317,13 +246,14 @@ radeon_ddc_connected(xf86OutputPtr output) +- if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) +- xf86OutputSetEDID(output, MonInfo); + if (radeon_output->type == OUTPUT_LVDS) + MonType = MT_LCD; + else if (radeon_output->type == OUTPUT_DVI_D) +@@ -317,13 +251,32 @@ radeon_ddc_connected(xf86OutputPtr output) MonType = MT_DFP; else if (radeon_output->type == OUTPUT_DP) MonType = MT_DFP; @@ -13777,6 +17523,24 @@ index 7b89d66..8c794fb 100644 MonType = MT_DFP; else MonType = MT_CRT; ++ ++ if (radeon_output->shared_ddc) { ++ if (radeon_output->type == OUTPUT_VGA) { ++ if (MonInfo->rawData[0x14] & 0x80) /* if it's digital and VGA */ ++ MonType = MT_NONE; ++ else ++ MonType = MT_CRT; ++ } else { ++ if (MonInfo->rawData[0x14] & 0x80) /* if it's digital and DVI/HDMI/etc. */ ++ MonType = MT_DFP; ++ else ++ MonType = MT_NONE; ++ } ++ } ++ ++ if (MonType != MT_NONE) ++ if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) ++ xf86OutputSetEDID(output, MonInfo); } else MonType = MT_NONE; - @@ -13784,7 +17548,20 @@ index 7b89d66..8c794fb 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); -@@ -537,7 +467,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, +@@ -524,6 +477,12 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, + + radeon_output->Flags &= ~RADEON_USE_RMX; + ++ /* ++ * Refresh the Crtc values without INTERLACE_HALVE_V ++ * Should we use output->scrn->adjustFlags like xf86RandRModeConvert() does? ++ */ ++ xf86SetModeCrtc(adjusted_mode, 0); ++ + /* decide if we are using RMX */ + if ((radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) + && radeon_output->rmx_type != RMX_OFF) { +@@ -537,7 +496,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, if (IS_AVIVO_VARIANT) { /* set to the panel's native mode */ adjusted_mode->HDisplay = radeon_output->PanelXRes; @@ -13793,14 +17570,14 @@ index 7b89d66..8c794fb 100644 adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank; adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus; adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + radeon_output->HSyncWidth; -@@ -580,12 +510,20 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, +@@ -580,12 +539,20 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, } } + if (IS_AVIVO_VARIANT) { + /* hw bug */ + if ((mode->Flags & V_INTERLACE) -+ && (mode->CrtcVSyncStart < (mode->CrtcVDisplay + 2))) ++ && (adjusted_mode->CrtcVSyncStart < (adjusted_mode->CrtcVDisplay + 2))) + adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2; + } + @@ -13814,7 +17591,7 @@ index 7b89d66..8c794fb 100644 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); int o; -@@ -595,9 +533,12 @@ radeon_mode_prepare(xf86OutputPtr output) +@@ -595,9 +562,12 @@ radeon_mode_prepare(xf86OutputPtr output) continue; else if (loop_output->crtc) { xf86CrtcPtr other_crtc = loop_output->crtc; @@ -13828,7 +17605,7 @@ index 7b89d66..8c794fb 100644 } } } -@@ -625,6 +566,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, +@@ -625,6 +595,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, static void radeon_mode_commit(xf86OutputPtr output) { @@ -13836,7 +17613,7 @@ index 7b89d66..8c794fb 100644 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); int o; -@@ -634,9 +576,12 @@ radeon_mode_commit(xf86OutputPtr output) +@@ -634,9 +605,12 @@ radeon_mode_commit(xf86OutputPtr output) continue; else if (loop_output->crtc) { xf86CrtcPtr other_crtc = loop_output->crtc; @@ -13850,7 +17627,7 @@ index 7b89d66..8c794fb 100644 } } } -@@ -1201,8 +1146,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1201,8 +1175,7 @@ radeon_create_resources(xf86OutputPtr output) } } @@ -13860,16 +17637,16 @@ index 7b89d66..8c794fb 100644 coherent_mode_atom = MAKE_ATOM("coherent_mode"); range[0] = 0; /* off */ -@@ -1214,7 +1158,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1214,7 +1187,7 @@ radeon_create_resources(xf86OutputPtr output) "RRConfigureOutputProperty error, %d\n", err); } - data = 1; /* use coherent mode by default */ -+ data = 0; /* coherent mode off by default */ ++ data = 1; /* coherent mode on by default */ err = RRChangeOutputProperty(output->randr_output, coherent_mode_atom, XA_INTEGER, 32, PropModeReplace, 1, &data, -@@ -1682,8 +1626,8 @@ Bool AVIVOI2CReset(ScrnInfoPtr pScrn) +@@ -1682,8 +1655,8 @@ Bool AVIVOI2CReset(ScrnInfoPtr pScrn) } #endif @@ -13880,7 +17657,7 @@ index 7b89d66..8c794fb 100644 { ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -1692,19 +1636,29 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) +@@ -1692,19 +1665,29 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) unsigned char *RADEONMMIO = info->MMIO; uint32_t temp; @@ -13916,7 +17693,7 @@ index 7b89d66..8c794fb 100644 OUTREG(pRADEONI2CBus->mask_data_reg, temp); temp = INREG(pRADEONI2CBus->mask_data_reg); -@@ -1786,8 +1740,12 @@ legacy_setup_i2c_bus(int ddc_line) +@@ -1786,8 +1769,12 @@ legacy_setup_i2c_bus(int ddc_line) { RADEONI2CBusRec i2c; @@ -13931,7 +17708,7 @@ index 7b89d66..8c794fb 100644 i2c.put_clk_mask = RADEON_GPIO_EN_1; i2c.put_data_mask = RADEON_GPIO_EN_0; i2c.get_clk_mask = RADEON_GPIO_Y_1; -@@ -1796,6 +1754,8 @@ legacy_setup_i2c_bus(int ddc_line) +@@ -1796,6 +1783,8 @@ legacy_setup_i2c_bus(int ddc_line) (ddc_line == RADEON_MDGPIO_EN_REG)) { i2c.mask_clk_reg = ddc_line; i2c.mask_data_reg = ddc_line; @@ -13940,7 +17717,7 @@ index 7b89d66..8c794fb 100644 i2c.put_clk_reg = ddc_line; i2c.put_data_reg = ddc_line; i2c.get_clk_reg = ddc_line + 4; -@@ -1803,6 +1763,8 @@ legacy_setup_i2c_bus(int ddc_line) +@@ -1803,6 +1792,8 @@ legacy_setup_i2c_bus(int ddc_line) } else { i2c.mask_clk_reg = ddc_line; i2c.mask_data_reg = ddc_line; @@ -13949,7 +17726,7 @@ index 7b89d66..8c794fb 100644 i2c.put_clk_reg = ddc_line; i2c.put_data_reg = ddc_line; i2c.get_clk_reg = ddc_line; -@@ -1822,6 +1784,8 @@ atom_setup_i2c_bus(int ddc_line) +@@ -1822,6 +1813,8 @@ atom_setup_i2c_bus(int ddc_line) { RADEONI2CBusRec i2c; @@ -13958,7 +17735,7 @@ index 7b89d66..8c794fb 100644 if (ddc_line == AVIVO_GPIO_0) { i2c.put_clk_mask = (1 << 19); i2c.put_data_mask = (1 << 18); -@@ -1829,6 +1793,8 @@ atom_setup_i2c_bus(int ddc_line) +@@ -1829,6 +1822,8 @@ atom_setup_i2c_bus(int ddc_line) i2c.get_data_mask = (1 << 18); i2c.mask_clk_mask = (1 << 19); i2c.mask_data_mask = (1 << 18); @@ -13967,7 +17744,7 @@ index 7b89d66..8c794fb 100644 } else { i2c.put_clk_mask = (1 << 0); i2c.put_data_mask = (1 << 8); -@@ -1836,9 +1802,13 @@ atom_setup_i2c_bus(int ddc_line) +@@ -1836,9 +1831,13 @@ atom_setup_i2c_bus(int ddc_line) i2c.get_data_mask = (1 << 8); i2c.mask_clk_mask = (1 << 0); i2c.mask_data_mask = (1 << 8); @@ -13981,7 +17758,58 @@ index 7b89d66..8c794fb 100644 i2c.put_clk_reg = ddc_line + 0x8; i2c.put_data_reg = ddc_line + 0x8; i2c.get_clk_reg = ddc_line + 0xc; -@@ -2301,13 +2271,13 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2175,17 +2174,9 @@ void RADEONInitConnector(xf86OutputPtr output) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; + +- if (info->IsAtomBios && +- ((radeon_output->DACType == DAC_PRIMARY) || +- (radeon_output->DACType == DAC_TVDAC))) ++ if ((radeon_output->DACType == DAC_TVDAC) && ++ xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE)) + radeon_output->load_detection = 1; +- else if (radeon_output->DACType == DAC_PRIMARY) +- radeon_output->load_detection = 1; /* primary dac, only drives vga */ +- else if ((radeon_output->DACType == DAC_TVDAC) && +- (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE))) +- radeon_output->load_detection = 1; /* shared tvdac between vga/dvi/tv */ +- else +- radeon_output->load_detection = 0; + + if (radeon_output->type == OUTPUT_LVDS) { + radeon_output->rmx_type = RMX_FULL; +@@ -2248,12 +2239,14 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); + info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].load_detection = FALSE; + info->BiosConnector[1].TMDSType = TMDS_NONE; + info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[1].valid = TRUE; + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; + info->BiosConnector[2].TMDSType = TMDS_NONE; + info->BiosConnector[2].ddc_i2c.valid = FALSE; + info->BiosConnector[2].valid = TRUE; +@@ -2273,6 +2266,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; + info->BiosConnector[2].TMDSType = TMDS_NONE; + info->BiosConnector[2].ddc_i2c.valid = FALSE; + info->BiosConnector[2].valid = TRUE; +@@ -2293,6 +2287,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; + info->BiosConnector[2].TMDSType = TMDS_NONE; + info->BiosConnector[2].ddc_i2c.valid = FALSE; + info->BiosConnector[2].valid = TRUE; +@@ -2301,17 +2296,18 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); info->BiosConnector[0].DACType = DAC_NONE; info->BiosConnector[0].TMDSType = TMDS_NONE; @@ -13998,7 +17826,133 @@ index 7b89d66..8c794fb 100644 info->BiosConnector[1].valid = TRUE; info->BiosConnector[2].ConnectorType = CONNECTOR_STV; -@@ -2677,7 +2647,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; + info->BiosConnector[2].TMDSType = TMDS_NONE; + info->BiosConnector[2].ddc_i2c.valid = FALSE; + info->BiosConnector[2].valid = TRUE; +@@ -2319,12 +2315,14 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + case RADEON_MAC_MINI_EXTERNAL: + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); + info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].load_detection = FALSE; + info->BiosConnector[0].TMDSType = TMDS_EXT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; + info->BiosConnector[0].valid = TRUE; + + info->BiosConnector[1].ConnectorType = CONNECTOR_STV; + info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].load_detection = FALSE; + info->BiosConnector[1].TMDSType = TMDS_NONE; + info->BiosConnector[1].ddc_i2c.valid = FALSE; + info->BiosConnector[1].valid = TRUE; +@@ -2332,12 +2330,14 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + case RADEON_MAC_MINI_INTERNAL: + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); + info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].load_detection = FALSE; + info->BiosConnector[0].TMDSType = TMDS_INT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; + info->BiosConnector[0].valid = TRUE; + + info->BiosConnector[1].ConnectorType = CONNECTOR_STV; + info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].load_detection = FALSE; + info->BiosConnector[1].TMDSType = TMDS_NONE; + info->BiosConnector[1].ddc_i2c.valid = FALSE; + info->BiosConnector[1].valid = TRUE; +@@ -2351,12 +2351,39 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); + info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].load_detection = FALSE; ++ info->BiosConnector[1].TMDSType = TMDS_NONE; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[1].valid = TRUE; ++ ++ info->BiosConnector[2].ConnectorType = CONNECTOR_STV; ++ info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; ++ info->BiosConnector[2].TMDSType = TMDS_NONE; ++ info->BiosConnector[2].ddc_i2c.valid = FALSE; ++ info->BiosConnector[2].valid = TRUE; ++ return TRUE; ++ case RADEON_MAC_EMAC: ++ /* eMac G4 800/1.0 with radeon 7500, no EDID on internal monitor ++ * later eMac's (G4 1.25/1.42) with radeon 9200 and 9600 may have ++ * different ddc setups. need to verify ++ */ ++ info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); ++ info->BiosConnector[0].DACType = DAC_PRIMARY; ++ info->BiosConnector[0].TMDSType = TMDS_NONE; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[0].valid = TRUE; ++ ++ info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); ++ info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].load_detection = FALSE; + info->BiosConnector[1].TMDSType = TMDS_NONE; + info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[1].valid = TRUE; + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; + info->BiosConnector[2].TMDSType = TMDS_NONE; + info->BiosConnector[2].ddc_i2c.valid = FALSE; + info->BiosConnector[2].valid = TRUE; +@@ -2437,6 +2464,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + else + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); + info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].load_detection = FALSE; + info->BiosConnector[1].TMDSType = TMDS_NONE; + info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[1].valid = TRUE; +@@ -2466,6 +2494,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + else + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); + info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].load_detection = FALSE; + info->BiosConnector[0].TMDSType = TMDS_NONE; + info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[0].valid = TRUE; +@@ -2481,6 +2510,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + } else { + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); + info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].load_detection = FALSE; + info->BiosConnector[0].TMDSType = TMDS_INT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; + info->BiosConnector[0].valid = TRUE; +@@ -2504,6 +2534,7 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + if (info->InternalTVOut) { + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].load_detection = FALSE; + info->BiosConnector[2].TMDSType = TMDS_NONE; + info->BiosConnector[2].ddc_i2c.valid = FALSE; + info->BiosConnector[2].valid = TRUE; +@@ -2537,7 +2568,7 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) + * Unforunately, there doesn't seem to be any good way to figure it out. + */ + +- /* ++ /* + * PowerBook5,[1-5]: external tmds, single-link + * PowerBook5,[789]: external tmds, dual-link + * PowerBook5,6: external tmds, single-link or dual-link +@@ -2595,6 +2626,9 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) + } else if (strstr(cpuline, "iMac G5 (iSight)")) { + ret = RADEON_MAC_IMAC_G5_ISIGHT; + break; ++ } else if (strstr(cpuline, "eMac")) { ++ ret = RADEON_MAC_EMAC; ++ break; + } + + /* No known PowerMac model detected */ +@@ -2677,7 +2711,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); @@ -14006,7 +17960,25 @@ index 7b89d66..8c794fb 100644 xf86OutputPtr output; char *optstr; int i = 0; -@@ -2742,13 +2711,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2691,6 +2724,8 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + */ + for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + info->BiosConnector[i].valid = FALSE; ++ info->BiosConnector[i].load_detection = TRUE; ++ info->BiosConnector[i].shared_ddc = FALSE; + info->BiosConnector[i].ddc_i2c.valid = FALSE; + info->BiosConnector[i].DACType = DAC_NONE; + info->BiosConnector[i].TMDSType = TMDS_NONE; +@@ -2721,6 +2756,8 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + info->MacModel = RADEON_MAC_MINI_EXTERNAL; + else if (!strncmp("imac-g5-isight", optstr, strlen("imac-g5-isight"))) + info->MacModel = RADEON_MAC_IMAC_G5_ISIGHT; ++ else if (!strncmp("emac", optstr, strlen("emac"))) ++ info->MacModel = RADEON_MAC_EMAC; + else { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid Mac Model: %s\n", optstr); + } +@@ -2742,13 +2779,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) RADEONSetupGenericConnectors(pScrn); } @@ -14020,8 +17992,29 @@ index 7b89d66..8c794fb 100644 /* parse connector table option */ optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE); +@@ -2773,6 +2803,11 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + return FALSE; + } + ++ if (info->BiosConnector[0].DACType == DAC_TVDAC) ++ info->BiosConnector[0].load_detection = FALSE; ++ if (info->BiosConnector[1].DACType == DAC_TVDAC) ++ info->BiosConnector[1].load_detection = FALSE; ++ + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(ddc_line[0]); + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(ddc_line[1]); + } +@@ -2821,6 +2856,8 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + radeon_output->output_id = info->BiosConnector[i].output_id; + radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c; + radeon_output->igp_lane_info = info->BiosConnector[i].igp_lane_info; ++ radeon_output->shared_ddc = info->BiosConnector[i].shared_ddc; ++ radeon_output->load_detection = info->BiosConnector[i].load_detection; + + if (radeon_output->ConnectorType == CONNECTOR_DVI_D) + radeon_output->DACType = DAC_NONE; diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index 39adb5e..ff1801f 100644 +index 39adb5e..525eafa 100644 --- a/src/radeon_pci_chipset_gen.h +++ b/src/radeon_pci_chipset_gen.h @@ -1,6 +1,7 @@ @@ -14032,26 +18025,72 @@ index 39adb5e..ff1801f 100644 { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, -@@ -250,6 +251,9 @@ PciChipsets RADEONPciChipsets[] = { +@@ -250,6 +251,27 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA }, { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA }, { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9441, PCI_CHIP_RV770_9441, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9444, PCI_CHIP_RV770_9444, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9446, PCI_CHIP_RV770_9446, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_944A, PCI_CHIP_RV770_944A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_944B, PCI_CHIP_RV770_944B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_944C, PCI_CHIP_RV770_944C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_944E, PCI_CHIP_RV770_944E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9450, PCI_CHIP_RV770_9450, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9452, PCI_CHIP_RV770_9452, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_9487, PCI_CHIP_RV730_9487, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_948F, PCI_CHIP_RV730_948F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_9490, PCI_CHIP_RV730_9490, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_9498, PCI_CHIP_RV730_9498, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_949C, PCI_CHIP_RV730_949C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_949E, PCI_CHIP_RV730_949E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV730_949F, PCI_CHIP_RV730_949F, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA }, -@@ -267,6 +271,7 @@ PciChipsets RADEONPciChipsets[] = { +@@ -267,6 +289,13 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA }, { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, + { PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_9540, PCI_CHIP_RV710_9540, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_9541, PCI_CHIP_RV710_9541, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_954E, PCI_CHIP_RV710_954E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_954F, PCI_CHIP_RV710_954F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_9552, PCI_CHIP_RV710_9552, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_9553, PCI_CHIP_RV710_9553, RES_SHARED_VGA }, { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, +@@ -279,11 +308,12 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, + { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, + { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV710_9592, PCI_CHIP_RV710_9592, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA }, +- { PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA }, +- { PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA }, ++ { PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA }, ++ { PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA }, +@@ -298,5 +328,6 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA }, + { PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA }, + { PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA }, ++ { PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA }, + { -1, -1, RES_UNDEFINED } + }; diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h -index d81cbe3..d650f9f 100644 +index d81cbe3..878fe56 100644 --- a/src/radeon_pci_device_match_gen.h +++ b/src/radeon_pci_device_match_gen.h @@ -1,6 +1,7 @@ @@ -14062,29 +18101,109 @@ index d81cbe3..d650f9f 100644 ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ), -@@ -250,6 +251,9 @@ static const struct pci_id_match radeon_device_match[] = { +@@ -250,6 +251,27 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9441, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9444, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9446, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_944A, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_944B, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_944C, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_944E, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9450, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9452, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9487, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_948F, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9490, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9498, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_949C, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_949E, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV730_949F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ), -@@ -267,6 +271,7 @@ static const struct pci_id_match radeon_device_match[] = { +@@ -267,6 +289,13 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9540, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9541, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_954E, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_954F, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9552, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9553, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ), +@@ -279,11 +308,12 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9592, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ), +- ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ), +- ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ), +@@ -298,5 +328,6 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ), + { 0, 0, 0 } + }; +diff --git a/src/radeon_probe.c b/src/radeon_probe.c +index 5d2eb43..041bab6 100644 +--- a/src/radeon_probe.c ++++ b/src/radeon_probe.c +@@ -44,8 +44,6 @@ + #include "atipcirename.h" + + #include "xf86.h" +-#define _XF86MISC_SERVER_ +-#include + #include "xf86Resources.h" + + #include "radeon_chipset_gen.h" diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index 24af52b..c14241e 100644 +index 24af52b..5cd610c 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h -@@ -166,6 +166,8 @@ typedef struct +@@ -41,9 +41,6 @@ + #include "xf86DDC.h" + #include "randrstr.h" + +-#define _XF86MISC_SERVER_ +-#include +- + #include "xf86Crtc.h" + + #ifdef USE_EXA +@@ -105,7 +102,9 @@ typedef enum + TMDS_EXT = 2, + TMDS_LVTMA = 3, + TMDS_DDIA = 4, +- TMDS_UNIPHY = 5 ++ TMDS_UNIPHY = 5, ++ TMDS_UNIPHY1 = 6, ++ TMDS_UNIPHY2 = 7 + } RADEONTmdsType; + + typedef enum +@@ -166,6 +165,8 @@ typedef struct Bool valid; uint32_t mask_clk_reg; uint32_t mask_data_reg; @@ -14093,7 +18212,7 @@ index 24af52b..c14241e 100644 uint32_t put_clk_reg; uint32_t put_data_reg; uint32_t get_clk_reg; -@@ -176,15 +178,15 @@ typedef struct +@@ -176,15 +177,15 @@ typedef struct uint32_t put_data_mask; uint32_t get_clk_mask; uint32_t get_data_mask; @@ -14115,7 +18234,17 @@ index 24af52b..c14241e 100644 int crtc_id; int binding; uint32_t cursor_offset; -@@ -235,8 +237,10 @@ typedef struct _RADEONOutputPrivateRec { +@@ -206,6 +207,9 @@ typedef struct { + int hpd_mask; + RADEONI2CBusRec ddc_i2c; + int igp_lane_info; ++ Bool shared_ddc; ++ int i2c_line_mux; ++ Bool load_detection; + } RADEONBIOSConnector; + + typedef struct _RADEONOutputPrivateRec { +@@ -235,8 +239,10 @@ typedef struct _RADEONOutputPrivateRec { int VSyncWidth; int VBlank; int Flags; /* Saved copy of mode flags */ @@ -14127,7 +18256,15 @@ index 24af52b..c14241e 100644 RADEONTMDSPll tmds_pll[4]; RADEONRMXType rmx_type; /* dvo */ -@@ -310,8 +314,10 @@ struct avivo_grph_state { +@@ -263,6 +269,7 @@ typedef struct _RADEONOutputPrivateRec { + int output_id; + int devices; + Bool enabled; ++ Bool shared_ddc; + } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; + + struct avivo_pll_state { +@@ -310,8 +317,10 @@ struct avivo_grph_state { uint32_t x_end; uint32_t y_end; @@ -14138,7 +18275,7 @@ index 24af52b..c14241e 100644 }; struct avivo_state -@@ -326,6 +332,7 @@ struct avivo_state +@@ -326,6 +335,7 @@ struct avivo_state uint32_t crtc_master_en; uint32_t crtc_tv_control; @@ -14147,10 +18284,20 @@ index 24af52b..c14241e 100644 struct avivo_pll_state pll1; struct avivo_pll_state pll2; diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 59e2f12..19f9869 100644 +index 59e2f12..92bbccc 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h -@@ -1032,6 +1032,10 @@ +@@ -401,6 +401,9 @@ + # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) + # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) + #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 ++# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0 ++# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16 ++# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15) + #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 + # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) + # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +@@ -1032,6 +1035,10 @@ #define RADEON_OV0_BASE_ADDR 0x43c #define RADEON_NB_TOM 0x15c #define R300_MC_INIT_MISC_LAT_TIMER 0x180 @@ -14161,7 +18308,36 @@ index 59e2f12..19f9869 100644 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ # define RADEON_FORCEON_MCLKA (1 << 16) # define RADEON_FORCEON_MCLKB (1 << 17) -@@ -3185,6 +3189,7 @@ +@@ -2283,6 +2290,14 @@ + # define R200_VTX_STQ3_D3D 0x00400000 + # define R200_VTX_STQ4_D3D 0x01000000 + # define R200_VTX_STQ5_D3D 0x04000000 ++#define R200_RE_SCISSOR_TL_0 0x1cd8 ++#define R200_RE_SCISSOR_BR_0 0x1cdc ++#define R200_RE_SCISSOR_TL_1 0x1ce0 ++#define R200_RE_SCISSOR_BR_1 0x1ce4 ++#define R200_RE_SCISSOR_TL_2 0x1ce8 ++#define R200_RE_SCISSOR_BR_2 0x1cec ++# define R200_SCISSOR_X_SHIFT 0 ++# define R200_SCISSOR_Y_SHIFT 16 + #define RADEON_SE_CNTL_STATUS 0x2140 + # define RADEON_VC_NO_SWAP (0 << 0) + # define RADEON_VC_16BIT_SWAP (1 << 0) +@@ -2582,6 +2597,13 @@ + # define R200_VC_NO_SWAP (0 << 0) + # define R200_VC_16BIT_SWAP (1 << 0) + # define R200_VC_32BIT_SWAP (2 << 0) ++#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 ++# define R200_EXCLUSIVE_SCISSOR_0 0x01000000 ++# define R200_EXCLUSIVE_SCISSOR_1 0x02000000 ++# define R200_EXCLUSIVE_SCISSOR_2 0x04000000 ++# define R200_SCISSOR_ENABLE_0 0x10000000 ++# define R200_SCISSOR_ENABLE_1 0x20000000 ++# define R200_SCISSOR_ENABLE_2 0x40000000 + #define R200_PP_TXFILTER_0 0x2c00 + #define R200_PP_TXFILTER_1 0x2c20 + #define R200_PP_TXFILTER_2 0x2c40 +@@ -3185,6 +3207,7 @@ #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a @@ -14169,7 +18345,7 @@ index 59e2f12..19f9869 100644 #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 -@@ -3418,6 +3423,7 @@ +@@ -3418,6 +3441,7 @@ #define RS690_MC_AGP_LOCATION 0x101 #define RS690_MC_AGP_BASE 0x102 #define RS690_MC_AGP_BASE_2 0x103 @@ -14177,7 +18353,7 @@ index 59e2f12..19f9869 100644 #define RS690_MC_STATUS 0x90 #define RS690_MC_STATUS_IDLE (1 << 0) -@@ -3431,12 +3437,13 @@ +@@ -3431,12 +3455,13 @@ #define RS600_MC_STATUS 0x0 #define RS600_MC_STATUS_IDLE (1 << 0) @@ -14197,7 +18373,7 @@ index 59e2f12..19f9869 100644 #define RV515_MC_FB_LOCATION 0x1 #define RV515_MC_AGP_LOCATION 0x2 -@@ -3598,8 +3605,20 @@ +@@ -3598,8 +3623,24 @@ #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 @@ -14217,10 +18393,14 @@ index 59e2f12..19f9869 100644 +#define AVIVO_D1MODE_DATA_FORMAT 0x6528 +# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) +#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c ++#define AVIVO_D1MODE_VLINE_START_END 0x6538 ++# define AVIVO_D1MODE_VLINE_START_SHIFT 0 ++# define AVIVO_D1MODE_VLINE_END_SHIFT 16 ++# define AVIVO_D1MODE_VLINE_INV (1 << 31) #define AVIVO_D1MODE_VIEWPORT_START 0x6580 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 -@@ -3651,6 +3670,8 @@ +@@ -3651,6 +3692,8 @@ #define AVIVO_D2CUR_SIZE 0x6c10 #define AVIVO_D2CUR_POSITION 0x6c14 @@ -14229,7 +18409,7 @@ index 59e2f12..19f9869 100644 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 -@@ -3658,6 +3679,7 @@ +@@ -3658,6 +3701,7 @@ #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 @@ -14237,7 +18417,7 @@ index 59e2f12..19f9869 100644 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 -@@ -3918,6 +3940,8 @@ +@@ -3918,6 +3962,8 @@ #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 @@ -14246,8 +18426,69 @@ index 59e2f12..19f9869 100644 #define R600_HDP_NONSURFACE_BASE 0x2c04 #define R600_BUS_CNTL 0x5420 -@@ -4234,7 +4258,7 @@ - #define R300_PVS_SRC_ADDR_SEL(x) (x << 29) +@@ -4119,7 +4165,7 @@ + #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 + /* PVS instructions */ + /* Opcode and dst instruction */ +-#define R300_PVS_DST_OPCODE(x) (x << 0) ++#define R300_PVS_DST_OPCODE(x) ((x) << 0) + /* Vector ops */ + # define R300_VECTOR_NO_OP 0 + # define R300_VE_DOT_PRODUCT 1 +@@ -4187,7 +4233,7 @@ + # define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 + #define R300_PVS_DST_MATH_INST (1 << 6) + #define R300_PVS_DST_MACRO_INST (1 << 7) +-#define R300_PVS_DST_REG_TYPE(x) (x << 8) ++#define R300_PVS_DST_REG_TYPE(x) ((x) << 8) + # define R300_PVS_DST_REG_TEMPORARY 0 + # define R300_PVS_DST_REG_A0 1 + # define R300_PVS_DST_REG_OUT 2 +@@ -4195,7 +4241,7 @@ + # define R300_PVS_DST_REG_ALT_TEMPORARY 4 + # define R300_PVS_DST_REG_INPUT 5 + #define R300_PVS_DST_ADDR_MODE_1 (1 << 12) +-#define R300_PVS_DST_OFFSET(x) (x << 13) ++#define R300_PVS_DST_OFFSET(x) ((x) << 13) + #define R300_PVS_DST_WE_X (1 << 20) + #define R300_PVS_DST_WE_Y (1 << 21) + #define R300_PVS_DST_WE_Z (1 << 22) +@@ -4205,10 +4251,10 @@ + #define R300_PVS_DST_PRED_ENABLE (1 << 26) + #define R300_PVS_DST_PRED_SENSE (1 << 27) + #define R300_PVS_DST_DUAL_MATH_OP (1 << 28) +-#define R300_PVS_DST_ADDR_SEL(x) (x << 29) ++#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29) + #define R300_PVS_DST_ADDR_MODE_0 (1 << 31) + /* src operand instruction */ +-#define R300_PVS_SRC_REG_TYPE(x) (x << 0) ++#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0) + # define R300_PVS_SRC_REG_TEMPORARY 0 + # define R300_PVS_SRC_REG_INPUT 1 + # define R300_PVS_SRC_REG_CONSTANT 2 +@@ -4216,11 +4262,11 @@ + #define R300_SPARE_0 (1 << 2) + #define R300_PVS_SRC_ABS_XYZW (1 << 3) + #define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) +-#define R300_PVS_SRC_OFFSET(x) (x << 5) +-#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13) +-#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16) +-#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19) +-#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22) ++#define R300_PVS_SRC_OFFSET(x) ((x) << 5) ++#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13) ++#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16) ++#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19) ++#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22) + # define R300_PVS_SRC_SELECT_X 0 + # define R300_PVS_SRC_SELECT_Y 1 + # define R300_PVS_SRC_SELECT_Z 2 +@@ -4231,10 +4277,10 @@ + #define R300_PVS_SRC_NEG_Y (1 << 26) + #define R300_PVS_SRC_NEG_Z (1 << 27) + #define R300_PVS_SRC_NEG_W (1 << 28) +-#define R300_PVS_SRC_ADDR_SEL(x) (x << 29) ++#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29) #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) -#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC @@ -14255,15 +18496,64 @@ index 59e2f12..19f9869 100644 #define R300_VAP_OUT_VTX_FMT_0 0x2090 # define R300_VTX_POS_PRESENT (1 << 0) # define R300_VTX_COLOR_0_PRESENT (1 << 1) -@@ -4322,6 +4346,7 @@ +@@ -4288,9 +4334,9 @@ + + #define R300_RS_IP_0 0x4310 + #define R300_RS_IP_1 0x4314 +-# define R300_RS_TEX_PTR(x) (x << 0) +-# define R300_RS_COL_PTR(x) (x << 6) +-# define R300_RS_COL_FMT(x) (x << 9) ++# define R300_RS_TEX_PTR(x) ((x) << 0) ++# define R300_RS_COL_PTR(x) ((x) << 6) ++# define R300_RS_COL_FMT(x) ((x) << 9) + # define R300_RS_COL_FMT_RGBA 0 + # define R300_RS_COL_FMT_RGB0 2 + # define R300_RS_COL_FMT_RGB1 3 +@@ -4300,10 +4346,10 @@ + # define R300_RS_COL_FMT_111A 8 + # define R300_RS_COL_FMT_1110 9 + # define R300_RS_COL_FMT_1111 10 +-# define R300_RS_SEL_S(x) (x << 13) +-# define R300_RS_SEL_T(x) (x << 16) +-# define R300_RS_SEL_R(x) (x << 19) +-# define R300_RS_SEL_Q(x) (x << 22) ++# define R300_RS_SEL_S(x) ((x) << 13) ++# define R300_RS_SEL_T(x) ((x) << 16) ++# define R300_RS_SEL_R(x) ((x) << 19) ++# define R300_RS_SEL_Q(x) ((x) << 22) + # define R300_RS_SEL_C0 0 + # define R300_RS_SEL_C1 1 + # define R300_RS_SEL_C2 2 +@@ -4311,20 +4357,21 @@ + # define R300_RS_SEL_K0 4 + # define R300_RS_SEL_K1 5 + #define R300_RS_INST_COUNT 0x4304 +-# define R300_INST_COUNT_RS(x) (x << 0) ++# define R300_INST_COUNT_RS(x) ((x) << 0) + # define R300_RS_W_EN (1 << 4) +-# define R300_TX_OFFSET_RS(x) (x << 5) ++# define R300_TX_OFFSET_RS(x) ((x) << 5) + #define R300_RS_INST_0 0x4330 + #define R300_RS_INST_1 0x4334 +-# define R300_INST_TEX_ID(x) (x << 0) ++# define R300_INST_TEX_ID(x) ((x) << 0) + # define R300_RS_INST_TEX_CN_WRITE (1 << 3) +-# define R300_INST_TEX_ADDR(x) (x << 6) ++# define R300_INST_TEX_ADDR(x) ((x) << 6) #define R300_TX_INVALTAGS 0x4100 #define R300_TX_FILTER0_0 0x4400 +-# define R300_TX_CLAMP_S(x) (x << 0) +-# define R300_TX_CLAMP_T(x) (x << 3) +-# define R300_TX_CLAMP_R(x) (x << 6) +#define R300_TX_FILTER0_1 0x4404 - # define R300_TX_CLAMP_S(x) (x << 0) - # define R300_TX_CLAMP_T(x) (x << 3) - # define R300_TX_CLAMP_R(x) (x << 6) -@@ -4339,7 +4364,9 @@ ++# define R300_TX_CLAMP_S(x) ((x) << 0) ++# define R300_TX_CLAMP_T(x) ((x) << 3) ++# define R300_TX_CLAMP_R(x) ((x) << 6) + # define R300_TX_CLAMP_WRAP 0 + # define R300_TX_CLAMP_MIRROR 1 + # define R300_TX_CLAMP_CLAMP_LAST 2 +@@ -4339,7 +4386,9 @@ # define R300_TX_MIN_FILTER_LINEAR (2 << 11) # define R300_TX_ID_SHIFT 28 #define R300_TX_FILTER1_0 0x4440 @@ -14273,7 +18563,7 @@ index 59e2f12..19f9869 100644 # define R300_TXWIDTH_SHIFT 0 # define R300_TXHEIGHT_SHIFT 11 # define R300_NUM_LEVELS_SHIFT 26 -@@ -4347,6 +4374,7 @@ +@@ -4347,6 +4396,7 @@ # define R300_TXPROJECTED (1 << 30) # define R300_TXPITCH_EN (1 << 31) #define R300_TX_FORMAT1_0 0x44c0 @@ -14281,7 +18571,7 @@ index 59e2f12..19f9869 100644 # define R300_TX_FORMAT_X8 0x0 # define R300_TX_FORMAT_X16 0x1 # define R300_TX_FORMAT_Y4X4 0x2 -@@ -4420,10 +4448,12 @@ +@@ -4420,10 +4470,12 @@ # define R300_TX_FORMAT_SWAP_YUV (1 << 24) #define R300_TX_FORMAT2_0 0x4500 @@ -14294,29 +18584,69 @@ index 59e2f12..19f9869 100644 # define R300_ENDIAN_SWAP_16_BIT (1 << 0) # define R300_ENDIAN_SWAP_32_BIT (2 << 0) # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) -@@ -4500,6 +4530,7 @@ +@@ -4483,15 +4535,15 @@ + # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) + #define R300_US_PIXSIZE 0x4604 + #define R300_US_CODE_OFFSET 0x4608 +-# define R300_ALU_CODE_OFFSET(x) (x << 0) +-# define R300_ALU_CODE_SIZE(x) (x << 6) +-# define R300_TEX_CODE_OFFSET(x) (x << 13) +-# define R300_TEX_CODE_SIZE(x) (x << 18) ++# define R300_ALU_CODE_OFFSET(x) ((x) << 0) ++# define R300_ALU_CODE_SIZE(x) ((x) << 6) ++# define R300_TEX_CODE_OFFSET(x) ((x) << 13) ++# define R300_TEX_CODE_SIZE(x) ((x) << 18) + #define R300_US_CODE_ADDR_0 0x4610 +-# define R300_ALU_START(x) (x << 0) +-# define R300_ALU_SIZE(x) (x << 6) +-# define R300_TEX_START(x) (x << 12) +-# define R300_TEX_SIZE(x) (x << 17) ++# define R300_ALU_START(x) ((x) << 0) ++# define R300_ALU_SIZE(x) ((x) << 6) ++# define R300_TEX_START(x) ((x) << 12) ++# define R300_TEX_SIZE(x) ((x) << 17) + # define R300_RGBA_OUT (1 << 22) + # define R300_W_OUT (1 << 23) + #define R300_US_CODE_ADDR_1 0x4614 +@@ -4500,10 +4552,11 @@ #define R300_US_TEX_INST_0 0x4620 #define R300_US_TEX_INST_1 0x4624 #define R300_US_TEX_INST_2 0x4628 +-# define R300_TEX_SRC_ADDR(x) (x << 0) +-# define R300_TEX_DST_ADDR(x) (x << 6) +-# define R300_TEX_ID(x) (x << 11) +-# define R300_TEX_INST(x) (x << 15) +#define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4) - # define R300_TEX_SRC_ADDR(x) (x << 0) - # define R300_TEX_DST_ADDR(x) (x << 6) - # define R300_TEX_ID(x) (x << 11) -@@ -4512,11 +4543,13 @@ ++# define R300_TEX_SRC_ADDR(x) ((x) << 0) ++# define R300_TEX_DST_ADDR(x) ((x) << 6) ++# define R300_TEX_ID(x) ((x) << 11) ++# define R300_TEX_INST(x) ((x) << 15) + # define R300_TEX_INST_NOP 0 + # define R300_TEX_INST_LD 1 + # define R300_TEX_INST_TEXKILL 2 +@@ -4512,20 +4565,23 @@ #define R300_US_ALU_RGB_ADDR_0 0x46c0 #define R300_US_ALU_RGB_ADDR_1 0x46c4 #define R300_US_ALU_RGB_ADDR_2 0x46c8 +#define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4) /* for ADDR0-2, values 0-31 specify a location in the pixel stack, values 32-63 specify a constant */ - # define R300_ALU_RGB_ADDR0(x) (x << 0) - # define R300_ALU_RGB_ADDR1(x) (x << 6) - # define R300_ALU_RGB_ADDR2(x) (x << 12) +-# define R300_ALU_RGB_ADDR0(x) (x << 0) +-# define R300_ALU_RGB_ADDR1(x) (x << 6) +-# define R300_ALU_RGB_ADDR2(x) (x << 12) ++# define R300_ALU_RGB_ADDR0(x) ((x) << 0) ++# define R300_ALU_RGB_ADDR1(x) ((x) << 6) ++# define R300_ALU_RGB_ADDR2(x) ((x) << 12) +# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5)) /* ADDRD - where on the pixel stack the result of this instruction will be written */ - # define R300_ALU_RGB_ADDRD(x) (x << 18) -@@ -4526,6 +4559,7 @@ +-# define R300_ALU_RGB_ADDRD(x) (x << 18) +-# define R300_ALU_RGB_WMASK(x) (x << 23) +-# define R300_ALU_RGB_OMASK(x) (x << 26) ++# define R300_ALU_RGB_ADDRD(x) ((x) << 18) ++# define R300_ALU_RGB_WMASK(x) ((x) << 23) ++# define R300_ALU_RGB_OMASK(x) ((x) << 26) + # define R300_ALU_RGB_MASK_NONE 0 # define R300_ALU_RGB_MASK_R 1 # define R300_ALU_RGB_MASK_G 2 # define R300_ALU_RGB_MASK_B 4 @@ -14324,37 +18654,130 @@ index 59e2f12..19f9869 100644 # define R300_ALU_RGB_TARGET_A (0 << 29) # define R300_ALU_RGB_TARGET_B (1 << 29) # define R300_ALU_RGB_TARGET_C (2 << 29) -@@ -4533,6 +4567,7 @@ +@@ -4533,7 +4589,8 @@ #define R300_US_ALU_RGB_INST_0 0x48c0 #define R300_US_ALU_RGB_INST_1 0x48c4 #define R300_US_ALU_RGB_INST_2 0x48c8 +-# define R300_ALU_RGB_SEL_A(x) (x << 0) +#define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4) - # define R300_ALU_RGB_SEL_A(x) (x << 0) ++# define R300_ALU_RGB_SEL_A(x) ((x) << 0) # define R300_ALU_RGB_SRC0_RGB 0 # define R300_ALU_RGB_SRC0_RRR 1 -@@ -4604,11 +4639,13 @@ + # define R300_ALU_RGB_SRC0_GGG 2 +@@ -4566,21 +4623,21 @@ + # define R300_ALU_RGB_SRC0_ABG 29 + # define R300_ALU_RGB_SRC1_ABG 30 + # define R300_ALU_RGB_SRC2_ABG 31 +-# define R300_ALU_RGB_MOD_A(x) (x << 5) ++# define R300_ALU_RGB_MOD_A(x) ((x) << 5) + # define R300_ALU_RGB_MOD_NOP 0 + # define R300_ALU_RGB_MOD_NEG 1 + # define R300_ALU_RGB_MOD_ABS 2 + # define R300_ALU_RGB_MOD_NAB 3 +-# define R300_ALU_RGB_SEL_B(x) (x << 7) +-# define R300_ALU_RGB_MOD_B(x) (x << 12) +-# define R300_ALU_RGB_SEL_C(x) (x << 14) +-# define R300_ALU_RGB_MOD_C(x) (x << 19) +-# define R300_ALU_RGB_SRCP_OP(x) (x << 21) ++# define R300_ALU_RGB_SEL_B(x) ((x) << 7) ++# define R300_ALU_RGB_MOD_B(x) ((x) << 12) ++# define R300_ALU_RGB_SEL_C(x) ((x) << 14) ++# define R300_ALU_RGB_MOD_C(x) ((x) << 19) ++# define R300_ALU_RGB_SRCP_OP(x) ((x) << 21) + # define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0 + # define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1 + # define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2 + # define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3 +-# define R300_ALU_RGB_OP(x) (x << 23) ++# define R300_ALU_RGB_OP(x) ((x) << 23) + # define R300_ALU_RGB_OP_MAD 0 + # define R300_ALU_RGB_OP_DP3 1 + # define R300_ALU_RGB_OP_DP4 2 +@@ -4591,7 +4648,7 @@ + # define R300_ALU_RGB_OP_CMP 8 + # define R300_ALU_RGB_OP_FRC 9 + # define R300_ALU_RGB_OP_SOP 10 +-# define R300_ALU_RGB_OMOD(x) (x << 27) ++# define R300_ALU_RGB_OMOD(x) ((x) << 27) + # define R300_ALU_RGB_OMOD_NONE 0 + # define R300_ALU_RGB_OMOD_MUL_2 1 + # define R300_ALU_RGB_OMOD_MUL_4 2 +@@ -4604,17 +4661,19 @@ #define R300_US_ALU_ALPHA_ADDR_0 0x47c0 #define R300_US_ALU_ALPHA_ADDR_1 0x47c4 #define R300_US_ALU_ALPHA_ADDR_2 0x47c8 +#define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4) /* for ADDR0-2, values 0-31 specify a location in the pixel stack, values 32-63 specify a constant */ - # define R300_ALU_ALPHA_ADDR0(x) (x << 0) - # define R300_ALU_ALPHA_ADDR1(x) (x << 6) - # define R300_ALU_ALPHA_ADDR2(x) (x << 12) +-# define R300_ALU_ALPHA_ADDR0(x) (x << 0) +-# define R300_ALU_ALPHA_ADDR1(x) (x << 6) +-# define R300_ALU_ALPHA_ADDR2(x) (x << 12) ++# define R300_ALU_ALPHA_ADDR0(x) ((x) << 0) ++# define R300_ALU_ALPHA_ADDR1(x) ((x) << 6) ++# define R300_ALU_ALPHA_ADDR2(x) ((x) << 12) +# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5)) /* ADDRD - where on the pixel stack the result of this instruction will be written */ - # define R300_ALU_ALPHA_ADDRD(x) (x << 18) -@@ -4624,6 +4661,7 @@ +-# define R300_ALU_ALPHA_ADDRD(x) (x << 18) +-# define R300_ALU_ALPHA_WMASK(x) (x << 23) +-# define R300_ALU_ALPHA_OMASK(x) (x << 24) +-# define R300_ALU_ALPHA_OMASK_W(x) (x << 27) ++# define R300_ALU_ALPHA_ADDRD(x) ((x) << 18) ++# define R300_ALU_ALPHA_WMASK(x) ((x) << 23) ++# define R300_ALU_ALPHA_OMASK(x) ((x) << 24) ++# define R300_ALU_ALPHA_OMASK_W(x) ((x) << 27) + # define R300_ALU_ALPHA_MASK_NONE 0 + # define R300_ALU_ALPHA_MASK_A 1 + # define R300_ALU_ALPHA_TARGET_A (0 << 25) +@@ -4624,7 +4683,8 @@ #define R300_US_ALU_ALPHA_INST_0 0x49c0 #define R300_US_ALU_ALPHA_INST_1 0x49c4 #define R300_US_ALU_ALPHA_INST_2 0x49c8 +-# define R300_ALU_ALPHA_SEL_A(x) (x << 0) +#define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4) - # define R300_ALU_ALPHA_SEL_A(x) (x << 0) ++# define R300_ALU_ALPHA_SEL_A(x) ((x) << 0) # define R300_ALU_ALPHA_SRC0_R 0 # define R300_ALU_ALPHA_SRC0_G 1 -@@ -4680,6 +4718,15 @@ + # define R300_ALU_ALPHA_SRC0_B 2 +@@ -4644,21 +4704,21 @@ + # define R300_ALU_ALPHA_0_0 16 + # define R300_ALU_ALPHA_1_0 17 + # define R300_ALU_ALPHA_0_5 18 +-# define R300_ALU_ALPHA_MOD_A(x) (x << 5) ++# define R300_ALU_ALPHA_MOD_A(x) ((x) << 5) + # define R300_ALU_ALPHA_MOD_NOP 0 + # define R300_ALU_ALPHA_MOD_NEG 1 + # define R300_ALU_ALPHA_MOD_ABS 2 + # define R300_ALU_ALPHA_MOD_NAB 3 +-# define R300_ALU_ALPHA_SEL_B(x) (x << 7) +-# define R300_ALU_ALPHA_MOD_B(x) (x << 12) +-# define R300_ALU_ALPHA_SEL_C(x) (x << 14) +-# define R300_ALU_ALPHA_MOD_C(x) (x << 19) +-# define R300_ALU_ALPHA_SRCP_OP(x) (x << 21) ++# define R300_ALU_ALPHA_SEL_B(x) ((x) << 7) ++# define R300_ALU_ALPHA_MOD_B(x) ((x) << 12) ++# define R300_ALU_ALPHA_SEL_C(x) ((x) << 14) ++# define R300_ALU_ALPHA_MOD_C(x) ((x) << 19) ++# define R300_ALU_ALPHA_SRCP_OP(x) ((x) << 21) + # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0 + # define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1 + # define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2 + # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3 +-# define R300_ALU_ALPHA_OP(x) (x << 23) ++# define R300_ALU_ALPHA_OP(x) ((x) << 23) + # define R300_ALU_ALPHA_OP_MAD 0 + # define R300_ALU_ALPHA_OP_DP 1 + # define R300_ALU_ALPHA_OP_MIN 2 +@@ -4670,7 +4730,7 @@ + # define R300_ALU_ALPHA_OP_LN2 9 + # define R300_ALU_ALPHA_OP_RCP 10 + # define R300_ALU_ALPHA_OP_RSQ 11 +-# define R300_ALU_ALPHA_OMOD(x) (x << 27) ++# define R300_ALU_ALPHA_OMOD(x) ((x) << 27) + # define R300_ALU_ALPHA_OMOD_NONE 0 + # define R300_ALU_ALPHA_OMOD_MUL_2 1 + # define R300_ALU_ALPHA_OMOD_MUL_4 2 +@@ -4680,6 +4740,15 @@ # define R300_ALU_ALPHA_OMOD_DIV_8 6 # define R300_ALU_ALPHA_CLAMP (1 << 30) @@ -14370,7 +18793,7 @@ index 59e2f12..19f9869 100644 #define R300_FG_DEPTH_SRC 0x4bd8 #define R300_FG_FOG_BLEND 0x4bc0 #define R300_FG_ALPHA_FUNC 0x4bd4 -@@ -4759,10 +4806,11 @@ +@@ -4759,10 +4828,11 @@ /* R500 US has to be loaded through an index/data pair */ #define R500_GA_US_VECTOR_INDEX 0x4250 @@ -14383,6 +18806,177 @@ index 59e2f12..19f9869 100644 #define R500_GA_US_VECTOR_DATA 0x4254 /* +@@ -4789,7 +4859,7 @@ + # define R500_ALPHA_OP_COS 13 + # define R500_ALPHA_OP_MDH 14 + # define R500_ALPHA_OP_MDV 15 +-# define R500_ALPHA_ADDRD(x) (x << 4) ++# define R500_ALPHA_ADDRD(x) ((x) << 4) + # define R500_ALPHA_ADDRD_REL (1 << 11) + # define R500_ALPHA_SEL_A_SRC0 (0 << 12) + # define R500_ALPHA_SEL_A_SRC1 (1 << 12) +@@ -4831,16 +4901,16 @@ + # define R500_ALPHA_OMOD_DIV_4 (5 << 26) + # define R500_ALPHA_OMOD_DIV_8 (6 << 26) + # define R500_ALPHA_OMOD_DISABLE (7 << 26) +-# define R500_ALPHA_TARGET(x) (x << 29) ++# define R500_ALPHA_TARGET(x) ((x) << 29) + # define R500_ALPHA_W_OMASK (1 << 31) + #define R500_US_ALU_ALPHA_ADDR_0 0x9800 +-# define R500_ALPHA_ADDR0(x) (x << 0) ++# define R500_ALPHA_ADDR0(x) ((x) << 0) + # define R500_ALPHA_ADDR0_CONST (1 << 8) + # define R500_ALPHA_ADDR0_REL (1 << 9) +-# define R500_ALPHA_ADDR1(x) (x << 10) ++# define R500_ALPHA_ADDR1(x) ((x) << 10) + # define R500_ALPHA_ADDR1_CONST (1 << 18) + # define R500_ALPHA_ADDR1_REL (1 << 19) +-# define R500_ALPHA_ADDR2(x) (x << 20) ++# define R500_ALPHA_ADDR2(x) ((x) << 20) + # define R500_ALPHA_ADDR2_CONST (1 << 28) + # define R500_ALPHA_ADDR2_REL (1 << 29) + # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) +@@ -4861,7 +4931,7 @@ + # define R500_ALU_RGBA_OP_SOP (10 << 0) + # define R500_ALU_RGBA_OP_MDH (11 << 0) + # define R500_ALU_RGBA_OP_MDV (12 << 0) +-# define R500_ALU_RGBA_ADDRD(x) (x << 4) ++# define R500_ALU_RGBA_ADDRD(x) ((x) << 4) + # define R500_ALU_RGBA_ADDRD_REL (1 << 11) + # define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) + # define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) +@@ -4984,16 +5054,16 @@ + # define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) + # define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) + # define R500_ALU_RGB_OMOD_DISABLE (7 << 26) +-# define R500_ALU_RGB_TARGET(x) (x << 29) ++# define R500_ALU_RGB_TARGET(x) ((x) << 29) + # define R500_ALU_RGB_WMASK (1 << 31) + #define R500_US_ALU_RGB_ADDR_0 0x9000 +-# define R500_RGB_ADDR0(x) (x << 0) ++# define R500_RGB_ADDR0(x) ((x) << 0) + # define R500_RGB_ADDR0_CONST (1 << 8) + # define R500_RGB_ADDR0_REL (1 << 9) +-# define R500_RGB_ADDR1(x) (x << 10) ++# define R500_RGB_ADDR1(x) ((x) << 10) + # define R500_RGB_ADDR1_CONST (1 << 18) + # define R500_RGB_ADDR1_REL (1 << 19) +-# define R500_RGB_ADDR2(x) (x << 20) ++# define R500_RGB_ADDR2(x) ((x) << 20) + # define R500_RGB_ADDR2_CONST (1 << 28) + # define R500_RGB_ADDR2_REL (1 << 29) + # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) +@@ -5046,19 +5116,19 @@ + # define R500_INST_STAT_WE_A (1 << 31) + /* note that these are 8 bit lengths, despite the offsets, at least for R500 */ + #define R500_US_CODE_ADDR 0x4630 +-# define R500_US_CODE_START_ADDR(x) (x << 0) +-# define R500_US_CODE_END_ADDR(x) (x << 16) ++# define R500_US_CODE_START_ADDR(x) ((x) << 0) ++# define R500_US_CODE_END_ADDR(x) ((x) << 16) + #define R500_US_CODE_OFFSET 0x4638 +-# define R500_US_CODE_OFFSET_ADDR(x) (x << 0) ++# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0) + #define R500_US_CODE_RANGE 0x4634 +-# define R500_US_CODE_RANGE_ADDR(x) (x << 0) +-# define R500_US_CODE_RANGE_SIZE(x) (x << 16) ++# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0) ++# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16) + #define R500_US_CONFIG 0x4600 + # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) + #define R500_US_FC_ADDR_0 0xa000 +-# define R500_FC_BOOL_ADDR(x) (x << 0) +-# define R500_FC_INT_ADDR(x) (x << 8) +-# define R500_FC_JUMP_ADDR(x) (x << 16) ++# define R500_FC_BOOL_ADDR(x) ((x) << 0) ++# define R500_FC_INT_ADDR(x) ((x) << 8) ++# define R500_FC_JUMP_ADDR(x) ((x) << 16) + # define R500_FC_JUMP_GLOBAL (1 << 31) + #define R500_US_FC_BOOL_CONST 0x4620 + # define R500_FC_KBOOL(x) (x) +@@ -5079,8 +5149,8 @@ + # define R500_FC_A_OP_NONE (0 << 6) + # define R500_FC_A_OP_POP (1 << 6) + # define R500_FC_A_OP_PUSH (2 << 6) +-# define R500_FC_JUMP_FUNC(x) (x << 8) +-# define R500_FC_B_POP_CNT(x) (x << 16) ++# define R500_FC_JUMP_FUNC(x) ((x) << 8) ++# define R500_FC_B_POP_CNT(x) ((x) << 16) + # define R500_FC_B_OP0_NONE (0 << 24) + # define R500_FC_B_OP0_DECR (1 << 24) + # define R500_FC_B_OP0_INCR (2 << 24) +@@ -5089,14 +5159,14 @@ + # define R500_FC_B_OP1_INCR (2 << 26) + # define R500_FC_IGNORE_UNCOVERED (1 << 28) + #define R500_US_FC_INT_CONST_0 0x4c00 +-# define R500_FC_INT_CONST_KR(x) (x << 0) +-# define R500_FC_INT_CONST_KG(x) (x << 8) +-# define R500_FC_INT_CONST_KB(x) (x << 16) ++# define R500_FC_INT_CONST_KR(x) ((x) << 0) ++# define R500_FC_INT_CONST_KG(x) ((x) << 8) ++# define R500_FC_INT_CONST_KB(x) ((x) << 16) + /* _0 through _15 */ + #define R500_US_FORMAT0_0 0x4640 +-# define R500_FORMAT_TXWIDTH(x) (x << 0) +-# define R500_FORMAT_TXHEIGHT(x) (x << 11) +-# define R500_FORMAT_TXDEPTH(x) (x << 22) ++# define R500_FORMAT_TXWIDTH(x) ((x) << 0) ++# define R500_FORMAT_TXHEIGHT(x) ((x) << 11) ++# define R500_FORMAT_TXDEPTH(x) ((x) << 22) + /* _0 through _3 */ + #define R500_US_OUT_FMT_0 0x46a4 + # define R500_OUT_FMT_C4_8 (0 << 0) +@@ -5137,12 +5207,12 @@ + # define R500_C3_SEL_R (1 << 14) + # define R500_C3_SEL_G (2 << 14) + # define R500_C3_SEL_B (3 << 14) +-# define R500_OUT_SIGN(x) (x << 16) ++# define R500_OUT_SIGN(x) ((x) << 16) + # define R500_ROUND_ADJ (1 << 20) + #define R500_US_PIXSIZE 0x4604 + # define R500_PIX_SIZE(x) (x) + #define R500_US_TEX_ADDR_0 0x9800 +-# define R500_TEX_SRC_ADDR(x) (x << 0) ++# define R500_TEX_SRC_ADDR(x) ((x) << 0) + # define R500_TEX_SRC_ADDR_REL (1 << 7) + # define R500_TEX_SRC_S_SWIZ_R (0 << 8) + # define R500_TEX_SRC_S_SWIZ_G (1 << 8) +@@ -5160,7 +5230,7 @@ + # define R500_TEX_SRC_Q_SWIZ_G (1 << 14) + # define R500_TEX_SRC_Q_SWIZ_B (2 << 14) + # define R500_TEX_SRC_Q_SWIZ_A (3 << 14) +-# define R500_TEX_DST_ADDR(x) (x << 16) ++# define R500_TEX_DST_ADDR(x) ((x) << 16) + # define R500_TEX_DST_ADDR_REL (1 << 23) + # define R500_TEX_DST_R_SWIZ_R (0 << 24) + # define R500_TEX_DST_R_SWIZ_G (1 << 24) +@@ -5179,7 +5249,7 @@ + # define R500_TEX_DST_A_SWIZ_B (2 << 30) + # define R500_TEX_DST_A_SWIZ_A (3 << 30) + #define R500_US_TEX_ADDR_DXDY_0 0xa000 +-# define R500_DX_ADDR(x) (x << 0) ++# define R500_DX_ADDR(x) ((x) << 0) + # define R500_DX_ADDR_REL (1 << 7) + # define R500_DX_S_SWIZ_R (0 << 8) + # define R500_DX_S_SWIZ_G (1 << 8) +@@ -5197,7 +5267,7 @@ + # define R500_DX_Q_SWIZ_G (1 << 14) + # define R500_DX_Q_SWIZ_B (2 << 14) + # define R500_DX_Q_SWIZ_A (3 << 14) +-# define R500_DY_ADDR(x) (x << 16) ++# define R500_DY_ADDR(x) ((x) << 16) + # define R500_DY_ADDR_REL (1 << 17) + # define R500_DY_S_SWIZ_R (0 << 24) + # define R500_DY_S_SWIZ_G (1 << 24) +@@ -5216,7 +5286,7 @@ + # define R500_DY_Q_SWIZ_B (2 << 30) + # define R500_DY_Q_SWIZ_A (3 << 30) + #define R500_US_TEX_INST_0 0x9000 +-# define R500_TEX_ID(x) (x << 16) ++# define R500_TEX_ID(x) ((x) << 16) + # define R500_TEX_INST_NOP (0 << 22) + # define R500_TEX_INST_LD (1 << 22) + # define R500_TEX_INST_TEXKILL (2 << 22) diff --git a/src/radeon_render.c b/src/radeon_render.c index dbd5b79..6668fe0 100644 --- a/src/radeon_render.c @@ -14791,12 +19385,39 @@ index 80333a4..0000000 - -#endif diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index cfa349d..c185b46 100644 +index cfa349d..7712344 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c -@@ -81,33 +81,43 @@ static __inline__ uint32_t F_TO_DW(float val) +@@ -80,34 +80,70 @@ static __inline__ uint32_t F_TO_DW(float val) + return tmp.l; } ++/* Borrowed from Mesa */ ++static __inline__ uint32_t F_TO_24(float val) ++{ ++ float mantissa; ++ int exponent; ++ uint32_t float24 = 0; ++ ++ if (val == 0.0) ++ return 0; ++ ++ mantissa = frexpf(val, &exponent); ++ ++ /* Handle -ve */ ++ if (mantissa < 0) { ++ float24 |= (1 << 23); ++ mantissa = mantissa * -1.0; ++ } ++ /* Handle exponent, bias of 63 */ ++ exponent += 62; ++ float24 |= (exponent << 16); ++ /* Kill 7 LSB of mantissa */ ++ float24 |= (F_TO_DW(mantissa) & 0x7FFFFF) >> 7; ++ ++ return float24; ++} ++ #define ACCEL_MMIO -#define VIDEO_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO -#define BEGIN_VIDEO(n) RADEONWaitForFifo(pScrn, (n)) @@ -14852,8 +19473,18 @@ index cfa349d..c185b46 100644 #endif /* XF86DRI */ static int -@@ -187,18 +197,30 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - dstPitch = (dstPitch + 15) & ~15; +@@ -178,27 +214,44 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + break; + } + +-#ifdef XF86DRI +- if (info->directRenderingEnabled && info->DMAForXv) +- /* The upload blit only supports multiples of 64 bytes */ +- dstPitch = (dstPitch + 63) & ~63; +- else +-#endif +- dstPitch = (dstPitch + 15) & ~15; ++ dstPitch = (dstPitch + 63) & ~63; if (pPriv->video_memory != NULL && size != pPriv->size) { - RADEONFreeMemory(pScrn, pPriv->video_memory); @@ -14872,9 +19503,20 @@ index cfa349d..c185b46 100644 return BadAlloc; } -+ /* Bicubic filter loading */ -+ if (!IS_R500_3D) ++ /* Bicubic filter setup */ ++ pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF); ++ if (!(IS_R300_3D || IS_R500_3D)) + pPriv->bicubic_enabled = FALSE; ++ if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) { ++ /* ++ * Applying the bicubic filter with a scale of less than 200% ++ * results in a blurred picture, so disable the filter. ++ */ ++ if ((src_w > drw_w / 2) || (src_h > drw_h / 2)) ++ pPriv->bicubic_enabled = FALSE; ++ } ++ ++ /* Bicubic filter loading */ + if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) { + pPriv->bicubic_offset = radeon_legacy_allocate_memory(pScrn, + &pPriv->bicubic_memory, @@ -14887,7 +19529,7 @@ index cfa349d..c185b46 100644 if (pDraw->type == DRAWABLE_WINDOW) pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw); else -@@ -267,6 +289,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -267,6 +320,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, break; } @@ -14898,26 +19540,36 @@ index cfa349d..c185b46 100644 /* update cliplist */ if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes); -@@ -320,12 +346,16 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] = +@@ -320,12 +377,26 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] = {15, TrueColor}, {16, TrueColor}, {24, TrueColor} }; -#define NUM_ATTRIBUTES 0 +#define NUM_ATTRIBUTES 1 ++ ++static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = ++{ ++ {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, ++ {0, 0, 0, NULL} ++}; ++ ++#define NUM_ATTRIBUTES_R300 2 -static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = -+static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = ++static XF86AttributeRec Attributes_r300[NUM_ATTRIBUTES_R300+1] = { -+ {XvSettable | XvGettable, 0, 1, "XV_BICUBIC"}, ++ {XvSettable | XvGettable, 0, 2, "XV_BICUBIC"}, ++ {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, + {0, 0, 0, NULL} }; +static Atom xvBicubic; ++static Atom xvVSync; + #define NUM_IMAGES 4 static XF86ImageRec Images[NUM_IMAGES] = -@@ -336,6 +366,44 @@ static XF86ImageRec Images[NUM_IMAGES] = +@@ -336,6 +407,48 @@ static XF86ImageRec Images[NUM_IMAGES] = XVIMAGE_UYVY }; @@ -14933,7 +19585,9 @@ index cfa349d..c185b46 100644 + if (info->accelOn) RADEON_SYNC(info, pScrn); + + if (attribute == xvBicubic) -+ *value = pPriv->bicubic_enabled ? 1 : 0; ++ *value = pPriv->bicubic_state; ++ else if (attribute == xvVSync) ++ *value = pPriv->vsync; + else + return BadMatch; + @@ -14952,7 +19606,9 @@ index cfa349d..c185b46 100644 + RADEON_SYNC(info, pScrn); + + if (attribute == xvBicubic) -+ pPriv->bicubic_enabled = ClipValue (value, 0, 1); ++ pPriv->bicubic_state = ClipValue (value, 0, 2); ++ else if (attribute == xvVSync) ++ pPriv->vsync = ClipValue (value, 0, 1); + else + return BadMatch; + @@ -14962,32 +19618,33 @@ index cfa349d..c185b46 100644 XF86VideoAdaptorPtr RADEONSetupImageTexturedVideo(ScreenPtr pScreen) { -@@ -351,6 +419,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) +@@ -351,6 +464,9 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) if (adapt == NULL) return NULL; + xvBicubic = MAKE_ATOM("XV_BICUBIC"); ++ xvVSync = MAKE_ATOM("XV_VSYNC"); + adapt->type = XvWindowMask | XvInputMask | XvImageMask; adapt->flags = 0; adapt->name = "Radeon Textured Video"; -@@ -367,8 +437,13 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) +@@ -367,8 +483,13 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) pPortPriv = (RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]); - adapt->nAttributes = NUM_ATTRIBUTES; - adapt->pAttributes = Attributes; -+ if (IS_R500_3D) { -+ adapt->nAttributes = NUM_ATTRIBUTES; -+ adapt->pAttributes = Attributes; ++ if (IS_R300_3D || IS_R500_3D) { ++ adapt->pAttributes = Attributes_r300; ++ adapt->nAttributes = NUM_ATTRIBUTES_R300; + } else { -+ adapt->nAttributes = 0; -+ adapt->pAttributes = NULL; ++ adapt->pAttributes = Attributes; ++ adapt->nAttributes = NUM_ATTRIBUTES; + } adapt->pImages = Images; adapt->nImages = NUM_IMAGES; adapt->PutVideo = NULL; -@@ -376,8 +451,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) +@@ -376,8 +497,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) adapt->GetVideo = NULL; adapt->GetStill = NULL; adapt->StopVideo = RADEONStopVideo; @@ -14998,25 +19655,25 @@ index cfa349d..c185b46 100644 adapt->QueryBestSize = RADEONQueryBestSize; adapt->PutImage = RADEONPutImageTextured; adapt->ReputImage = NULL; -@@ -390,6 +465,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) +@@ -390,6 +511,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) pPriv->videoStatus = 0; pPriv->currentBuffer = 0; pPriv->doubleBuffer = 0; -+ pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_RV515); ++ pPriv->bicubic_state = BICUBIC_AUTO; ++ pPriv->vsync = TRUE; /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */ REGION_NULL(pScreen, &pPriv->clip); diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index 277d9b2..c5ad0e1 100644 +index 277d9b2..410430c 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c -@@ -45,26 +45,47 @@ +@@ -45,26 +45,44 @@ #endif #endif -+#define VTX_DWORD_COUNT_FILTER 6 - #define VTX_DWORD_COUNT 4 - +-#define VTX_DWORD_COUNT 4 +- #ifdef ACCEL_CP +#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ @@ -15066,7 +19723,7 @@ index 277d9b2..c5ad0e1 100644 } while (0) #endif /* !ACCEL_CP */ -@@ -79,10 +100,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -79,10 +97,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv uint32_t dst_offset, dst_pitch, dst_format; uint32_t txenable, colorpitch; uint32_t blendcntl; @@ -15079,41 +19736,55 @@ index 277d9b2..c5ad0e1 100644 pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; -@@ -106,22 +127,27 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -106,22 +124,33 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv dstyoff = 0; #endif - if (!info->XInited3D) -+ if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); +- RADEONInit3DEngine(pScrn); ++#ifdef USE_EXA ++ if (info->useEXA) { ++ RADEON_SWITCH_TO_3D(); ++ } else ++#endif ++ { ++ BEGIN_ACCEL(2); ++ if (IS_R300_3D || IS_R500_3D) ++ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); ++ else ++ OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); ++ /* We must wait for 3d to idle, in case source was just written as a dest. */ ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_HOST_IDLECLEAN | ++ RADEON_WAIT_2D_IDLECLEAN | ++ RADEON_WAIT_3D_IDLECLEAN | ++ RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); ++ ++ if (!info->accel_state->XInited3D) ++ RADEONInit3DEngine(pScrn); ++ } - /* we can probably improve this */ +- /* we can probably improve this */ - BEGIN_VIDEO(2); -+ BEGIN_ACCEL(2); - if (IS_R300_3D || IS_R500_3D) +- if (IS_R300_3D || IS_R500_3D) - OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); ++ if (pPriv->bicubic_enabled) ++ vtx_count = 6; else - OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); -+ OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); - /* We must wait for 3d to idle, in case source was just written as a dest. */ +- /* We must wait for 3d to idle, in case source was just written as a dest. */ - OUT_VIDEO_REG(RADEON_WAIT_UNTIL, -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_HOST_IDLECLEAN | - RADEON_WAIT_2D_IDLECLEAN | - RADEON_WAIT_3D_IDLECLEAN | - RADEON_WAIT_DMA_GUI_IDLE); +- RADEON_WAIT_HOST_IDLECLEAN | +- RADEON_WAIT_2D_IDLECLEAN | +- RADEON_WAIT_3D_IDLECLEAN | +- RADEON_WAIT_DMA_GUI_IDLE); - FINISH_VIDEO(); -+ FINISH_ACCEL(); -+ -+ if (pPriv->bicubic_enabled) -+ vtx_count = VTX_DWORD_COUNT_FILTER; -+ else -+ vtx_count = VTX_DWORD_COUNT; ++ vtx_count = 4; if (IS_R300_3D || IS_R500_3D) { uint32_t output_fmt; -@@ -160,16 +186,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -160,16 +189,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | @@ -15137,7 +19808,7 @@ index 277d9b2..c5ad0e1 100644 /* pitch is in pixels */ txpitch = pPriv->src_pitch / 2; -@@ -183,22 +210,58 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -183,22 +213,58 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txoffset = pPriv->src_offset; @@ -15208,7 +19879,7 @@ index 277d9b2..c5ad0e1 100644 /* These registers define the number, type, and location of data submitted * to the PVS unit of GA input (when PVS is disabled) -@@ -213,56 +276,90 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -213,216 +279,1072 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv * Textures 0-7 * Fog */ @@ -15302,72 +19973,482 @@ index 277d9b2..c5ad0e1 100644 /* setup pixel shader */ if (IS_R300_3D) { - BEGIN_VIDEO(8); -+ BEGIN_ACCEL(9); - /* 2 components: 2 for tex0 */ +- /* 2 components: 2 for tex0 */ - OUT_VIDEO_REG(R300_RS_COUNT, -+ OUT_ACCEL_REG(R300_RS_COUNT, ++ if (pPriv->bicubic_enabled) { ++ BEGIN_ACCEL(79); ++ ++ /* 4 components: 2 for tex0 and 2 for tex1 */ ++ OUT_ACCEL_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | ++ R300_RS_COUNT_HIRES_EN)); ++ ++ /* R300_INST_COUNT_RS - highest RS instruction used */ ++ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6)); ++ ++ /* Pixel stack frame size. */ ++ OUT_ACCEL_REG(R300_US_PIXSIZE, 5); ++ ++ /* Indirection levels */ ++ OUT_ACCEL_REG(R300_US_CONFIG, ((2 << R300_NLEVEL_SHIFT) | ++ R300_FIRST_TEX)); ++ ++ /* Set nodes. */ ++ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | ++ R300_ALU_CODE_SIZE(14) | ++ R300_TEX_CODE_OFFSET(0) | ++ R300_TEX_CODE_SIZE(6))); ++ ++ /* Nodes are allocated highest first, but executed lowest first */ ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(0) | ++ R300_ALU_SIZE(0) | ++ R300_TEX_START(0) | ++ R300_TEX_SIZE(0))); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) | ++ R300_ALU_SIZE(9) | ++ R300_TEX_START(1) | ++ R300_TEX_SIZE(0))); ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(11) | ++ R300_ALU_SIZE(2) | ++ R300_TEX_START(2) | ++ R300_TEX_SIZE(3) | ++ R300_RGBA_OUT)); ++ ++ /* ** BICUBIC FP ** */ ++ ++ /* texcoord0 => temp0 ++ * texcoord1 => temp1 */ ++ ++ // first node ++ /* TEX temp2, temp1.rrr0, tex1, 1D */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(0), (R300_TEX_INST(R300_TEX_INST_LD) | ++ R300_TEX_ID(1) | ++ R300_TEX_SRC_ADDR(1) | ++ R300_TEX_DST_ADDR(2))); ++ ++ /* MOV temp1.r, temp1.ggg0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(1) | ++ R300_ALU_RGB_ADDRD(1) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDRD(1) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ ++ // second node ++ /* TEX temp1, temp1, tex1, 1D */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(1), (R300_TEX_INST(R300_TEX_INST_LD) | ++ R300_TEX_ID(1) | ++ R300_TEX_SRC_ADDR(1) | ++ R300_TEX_DST_ADDR(1))); ++ ++ /* MUL temp3.rg, temp2.ggg0, const0.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(2) | ++ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) | ++ R300_ALU_RGB_ADDRD(3) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ ++ /* MUL temp2.rg, temp2.rrr0, const0.rgb */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(2) | ++ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) | ++ R300_ALU_RGB_ADDRD(2) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(2) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* MAD temp4.rg, temp1.ggg0, const1.rgb, temp3.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(3), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(1) | ++ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | ++ R300_ALU_RGB_ADDR2(3) | ++ R300_ALU_RGB_ADDRD(4) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(4) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* MAD temp5.rg, temp1.ggg0, const1.rgb, temp2.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(4), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(1) | ++ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | ++ R300_ALU_RGB_ADDR2(2) | ++ R300_ALU_RGB_ADDRD(5) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(5) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* MAD temp3.rg, temp1.rrr0, const1.rgb, temp3.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(5), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(1) | ++ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | ++ R300_ALU_RGB_ADDR2(3) | ++ R300_ALU_RGB_ADDRD(3) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(3) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* MAD temp1.rg, temp1.rrr0, const1.rgb, temp2.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(1) | ++ R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) | ++ R300_ALU_RGB_ADDR2(2) | ++ R300_ALU_RGB_ADDRD(1) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* ADD temp1.rg, temp0.rgb0, temp1.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR2(1) | ++ R300_ALU_RGB_ADDRD(1) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* ADD temp2.rg, temp0.rgb0, temp3.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR2(3) | ++ R300_ALU_RGB_ADDRD(2) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* ADD temp3.rg, temp0.rgb0, temp5.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR2(5) | ++ R300_ALU_RGB_ADDRD(3) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ /* ADD temp0.rg, temp0.rgb0, temp4.rgb0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(10), (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR2(4) | ++ R300_ALU_RGB_ADDRD(0) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(10), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(10), (R300_ALU_ALPHA_ADDRD(0) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ ++ ++ // third node ++ /* TEX temp4, temp1.rg--, tex0, 1D */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(2), (R300_TEX_INST(R300_TEX_INST_LD) | ++ R300_TEX_ID(0) | ++ R300_TEX_SRC_ADDR(1) | ++ R300_TEX_DST_ADDR(4))); ++ ++ /* TEX temp3, temp3.rg--, tex0, 1D */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(3), (R300_TEX_INST(R300_TEX_INST_LD) | ++ R300_TEX_ID(0) | ++ R300_TEX_SRC_ADDR(3) | ++ R300_TEX_DST_ADDR(3))); ++ ++ /* TEX temp5, temp2.rg--, tex0, 1D */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(4), (R300_TEX_INST(R300_TEX_INST_LD) | ++ R300_TEX_ID(0) | ++ R300_TEX_SRC_ADDR(2) | ++ R300_TEX_DST_ADDR(5))); ++ ++ /* TEX temp0, temp0.rg--, tex0, 1D */ ++ OUT_ACCEL_REG(R300_US_TEX_INST(5), (R300_TEX_INST(R300_TEX_INST_LD) | ++ R300_TEX_ID(0) | ++ R300_TEX_SRC_ADDR(0) | ++ R300_TEX_DST_ADDR(0))); ++ ++ /* LRP temp3, temp1.bbbb, temp4, temp3 -> ++ * - PRESUB temps, temp4 - temp3 ++ * - MAD temp3, temp1.bbbb, temps, temp3 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(11), (R300_ALU_RGB_ADDR0(3) | ++ R300_ALU_RGB_ADDR1(4) | ++ R300_ALU_RGB_ADDR2(1) | ++ R300_ALU_RGB_ADDRD(3) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(11), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(11), (R300_ALU_ALPHA_ADDR0(3) | ++ R300_ALU_ALPHA_ADDR1(4) | ++ R300_ALU_ALPHA_ADDR2(1) | ++ R300_ALU_ALPHA_ADDRD(3) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A))); ++ ++ /* LRP temp0, temp1.bbbb, temp5, temp0 -> ++ * - PRESUB temps, temp5 - temp0 ++ * - MAD temp0, temp1.bbbb, temps, temp0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0) | ++ R300_ALU_RGB_INSERT_NOP)); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(12), (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR1(5) | ++ R300_ALU_RGB_ADDR2(1) | ++ R300_ALU_RGB_ADDRD(0) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(12), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(12), (R300_ALU_ALPHA_ADDR0(0) | ++ R300_ALU_ALPHA_ADDR1(5) | ++ R300_ALU_ALPHA_ADDR2(1) | ++ R300_ALU_ALPHA_ADDRD(0) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A))); ++ ++ /* LRP output, temp2.bbbb, temp3, temp0 -> ++ * - PRESUB temps, temp3 - temp0 ++ * - MAD output, temp2.bbbb, temps, temp0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(13), (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR1(3) | ++ R300_ALU_RGB_ADDR2(2) | ++ R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(13), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(13), (R300_ALU_ALPHA_ADDR0(0) | ++ R300_ALU_ALPHA_ADDR1(3) | ++ R300_ALU_ALPHA_ADDR2(2) | ++ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A))); ++ ++ /* Shader constants. */ ++ OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), F_TO_24(1.0/(float)pPriv->w)); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), 0); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), 0); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), 0); ++ ++ OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), 0); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), F_TO_24(1.0/(float)pPriv->h)); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), 0); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0); ++ ++ FINISH_ACCEL(); ++ } else { ++ BEGIN_ACCEL(11); ++ /* 2 components: 2 for tex0 */ ++ OUT_ACCEL_REG(R300_RS_COUNT, ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | R300_RS_COUNT_HIRES_EN)); - /* R300_INST_COUNT_RS - highest RS instruction used */ +- /* R300_INST_COUNT_RS - highest RS instruction used */ - OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); - +- - OUT_VIDEO_REG(R300_US_CODE_OFFSET, -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */ -+ -+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, - (R300_ALU_CODE_OFFSET(0) | - R300_ALU_CODE_SIZE(1) | - R300_TEX_CODE_OFFSET(0) | - R300_TEX_CODE_SIZE(1))); - +- (R300_ALU_CODE_OFFSET(0) | +- R300_ALU_CODE_SIZE(1) | +- R300_TEX_CODE_OFFSET(0) | +- R300_TEX_CODE_SIZE(1))); +- - OUT_VIDEO_REG(R300_US_CODE_ADDR_3, -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, - (R300_ALU_START(0) | - R300_ALU_SIZE(0) | - R300_TEX_START(0) | -@@ -273,7 +370,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - - /* ALU inst */ - /* RGB */ +- (R300_ALU_START(0) | +- R300_ALU_SIZE(0) | +- R300_TEX_START(0) | +- R300_TEX_SIZE(0) | +- R300_RGBA_OUT)); +- +- /* tex inst is preloaded in RADEONInit3DEngine() */ +- +- /* ALU inst */ +- /* RGB */ - OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, - (R300_ALU_RGB_ADDR0(0) | - R300_ALU_RGB_ADDR1(0) | - R300_ALU_RGB_ADDR2(0) | -@@ -282,7 +379,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - R300_ALU_RGB_MASK_G | - R300_ALU_RGB_MASK_B)) | - R300_ALU_RGB_TARGET_A)); +- (R300_ALU_RGB_ADDR0(0) | +- R300_ALU_RGB_ADDR1(0) | +- R300_ALU_RGB_ADDR2(0) | +- R300_ALU_RGB_ADDRD(0) | +- R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | +- R300_ALU_RGB_MASK_G | +- R300_ALU_RGB_MASK_B)) | +- R300_ALU_RGB_TARGET_A)); - OUT_VIDEO_REG(R300_US_ALU_RGB_INST_0, -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, - (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | - R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | - R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | -@@ -293,7 +390,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | - R300_ALU_RGB_CLAMP)); - /* Alpha */ +- (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | +- R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | +- R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | +- R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | +- R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | +- R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | +- R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | +- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | +- R300_ALU_RGB_CLAMP)); +- /* Alpha */ - OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0, -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, - (R300_ALU_ALPHA_ADDR0(0) | - R300_ALU_ALPHA_ADDR1(0) | - R300_ALU_ALPHA_ADDR2(0) | -@@ -301,7 +398,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | - R300_ALU_ALPHA_TARGET_A | - R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); +- (R300_ALU_ALPHA_ADDR0(0) | +- R300_ALU_ALPHA_ADDR1(0) | +- R300_ALU_ALPHA_ADDR2(0) | +- R300_ALU_ALPHA_ADDRD(0) | +- R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | +- R300_ALU_ALPHA_TARGET_A | +- R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); - OUT_VIDEO_REG(R300_US_ALU_ALPHA_INST_0, -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, - (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) | - R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | - R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) | -@@ -311,118 +408,591 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | - R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | - R300_ALU_ALPHA_CLAMP)); +- (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) | +- R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | +- R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) | +- R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | +- R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | +- R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | +- R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | +- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | +- R300_ALU_ALPHA_CLAMP)); - FINISH_VIDEO(); -+ FINISH_ACCEL(); ++ /* R300_INST_COUNT_RS - highest RS instruction used */ ++ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); ++ ++ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */ ++ ++ /* Indirection levels */ ++ OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) | ++ R300_FIRST_TEX)); ++ ++ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | ++ R300_ALU_CODE_SIZE(1) | ++ R300_TEX_CODE_OFFSET(0) | ++ R300_TEX_CODE_SIZE(1))); ++ ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | ++ R300_ALU_SIZE(0) | ++ R300_TEX_START(0) | ++ R300_TEX_SIZE(0) | ++ R300_RGBA_OUT)); ++ ++ /* tex inst */ ++ OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) | ++ R300_TEX_DST_ADDR(0) | ++ R300_TEX_ID(0) | ++ R300_TEX_INST(R300_TEX_INST_LD))); ++ ++ /* ALU inst */ ++ /* RGB */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, (R300_ALU_RGB_ADDR0(0) | ++ R300_ALU_RGB_ADDR1(0) | ++ R300_ALU_RGB_ADDR2(0) | ++ R300_ALU_RGB_ADDRD(0) | ++ R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | ++ R300_ALU_RGB_MASK_G | ++ R300_ALU_RGB_MASK_B)) | ++ R300_ALU_RGB_TARGET_A)); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | ++ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | ++ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | ++ R300_ALU_RGB_CLAMP)); ++ /* Alpha */ ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, (R300_ALU_ALPHA_ADDR0(0) | ++ R300_ALU_ALPHA_ADDR1(0) | ++ R300_ALU_ALPHA_ADDR2(0) | ++ R300_ALU_ALPHA_ADDRD(0) | ++ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | ++ R300_ALU_ALPHA_TARGET_A | ++ R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) | ++ R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) | ++ R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | ++ R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | ++ R300_ALU_ALPHA_CLAMP)); ++ FINISH_ACCEL(); ++ } } else { - BEGIN_VIDEO(18); - /* 2 components: 2 for tex0 */ @@ -15640,7 +20721,7 @@ index 277d9b2..c5ad0e1 100644 + R500_ALU_RGBA_B_SWIZ_R | + R500_ALU_RGBA_A_SWIZ_G)); + -+ /* TEX temp1, temp3.zwxy, tex0, 1D */ ++ /* TEX temp1, temp3.zwxy, tex0, 2D */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | @@ -15663,7 +20744,7 @@ index 277d9b2..c5ad0e1 100644 + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + -+ /* TEX temp3, temp3.xyzw, tex0, 1D */ ++ /* TEX temp3, temp3.xyzw, tex0, 2D */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | @@ -15688,7 +20769,7 @@ index 277d9b2..c5ad0e1 100644 + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + -+ /* MAD temp4, const1.0y0y, temp5.yyyy, temp4 */ ++ /* MAD temp4, const0.0y0y, temp5.yyyy, temp4 */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | + R500_INST_RGB_WMASK_R | + R500_INST_RGB_WMASK_G | @@ -15754,7 +20835,7 @@ index 277d9b2..c5ad0e1 100644 + R500_ALU_RGBA_B_SWIZ_R | + R500_ALU_RGBA_A_SWIZ_G)); + -+ /* TEX temp4, temp0.zwzw, tex0, 1D */ ++ /* TEX temp4, temp0.zwzw, tex0, 2D */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | @@ -15778,7 +20859,7 @@ index 277d9b2..c5ad0e1 100644 + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + -+ /* TEX temp0, temp0.xyzw, tex0, 1D */ ++ /* TEX temp0, temp0.xyzw, tex0, 2D */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | + R500_INST_RGB_WMASK_R | @@ -15927,7 +21008,7 @@ index 277d9b2..c5ad0e1 100644 + /* Shader constants. */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0)); + -+ /* const0 = {1 / texture[0].width, 0, 0, 0} */ ++ /* const0 = {1 / texture[0].width, 1 / texture[0].height, 0, 0} */ + OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w)); + OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h)); + OUT_ACCEL_REG_F(R500_GA_US_VECTOR_DATA, 0x0); @@ -16058,7 +21139,7 @@ index 277d9b2..c5ad0e1 100644 } else { -@@ -453,20 +1023,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -453,20 +1375,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= RADEON_COLOR_TILE_ENABLE; @@ -16089,7 +21170,7 @@ index 277d9b2..c5ad0e1 100644 if ((info->ChipFamily == CHIP_FAMILY_RV250) || -@@ -474,77 +1044,82 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -474,84 +1396,106 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv (info->ChipFamily == CHIP_FAMILY_RS300) || (info->ChipFamily == CHIP_FAMILY_R200)) { @@ -16241,7 +21322,49 @@ index 277d9b2..c5ad0e1 100644 } } -@@ -582,77 +1157,96 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv ++ FUNC_NAME(RADEONWaitForVLine)(pScrn, pPixmap, ++ radeon_covering_crtc_num(pScrn, ++ pPriv->drw_x, ++ pPriv->drw_x + pPriv->dst_w, ++ pPriv->drw_y, ++ pPriv->drw_y + pPriv->dst_h, ++ pPriv->desired_crtc), ++ pPriv->drw_y, ++ pPriv->drw_y + pPriv->dst_h, ++ pPriv->vsync); ++ ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | ++ (0 << R300_SCISSOR_Y_SHIFT))); ++ OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | ++ (8191 << R300_SCISSOR_Y_SHIFT))); ++ FINISH_ACCEL(); ++ + while (nBox--) { + int srcX, srcY, srcw, srch; + int dstX, dstY, dstw, dsth; +- xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; + dstX = pBox->x1 + dstxoff; + dstY = pBox->y1 + dstyoff; + dstw = pBox->x2 - pBox->x1; +@@ -565,16 +1509,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + srcw = (pPriv->src_w * dstw) / pPriv->dst_w; + srch = (pPriv->src_h * dsth) / pPriv->dst_h; + +- srcTopLeft.x = IntToxFixed(srcX); +- srcTopLeft.y = IntToxFixed(srcY); +- srcTopRight.x = IntToxFixed(srcX + srcw); +- srcTopRight.y = IntToxFixed(srcY); +- srcBottomLeft.x = IntToxFixed(srcX); +- srcBottomLeft.y = IntToxFixed(srcY + srch); +- srcBottomRight.x = IntToxFixed(srcX + srcw); +- srcBottomRight.y = IntToxFixed(srcY + srch); +- +- + #if 0 + ErrorF("dst: %d, %d, %d, %d\n", dstX, dstY, dstw, dsth); + ErrorF("src: %d, %d, %d, %d\n", srcX, srcY, srcw, srch); +@@ -582,77 +1516,117 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv #ifdef ACCEL_CP if (info->ChipFamily < CHIP_FAMILY_R200) { @@ -16257,32 +21380,36 @@ index 277d9b2..c5ad0e1 100644 RADEON_CP_VC_CNTL_PRIM_WALK_RING | RADEON_CP_VC_CNTL_MAOS_ENABLE | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | -- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ++ } else if (IS_R300_3D || IS_R500_3D) { ++ BEGIN_RING(4 * vtx_count + 4); ++ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, ++ 4 * vtx_count)); ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | ++ RADEON_CP_VC_CNTL_PRIM_WALK_RING | + (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else { - if (IS_R300_3D || IS_R500_3D) +- if (IS_R300_3D || IS_R500_3D) - BEGIN_RING(4 * VTX_DWORD_COUNT + 4); -+ BEGIN_RING(4 * vtx_count + 4); - else +- else - BEGIN_RING(4 * VTX_DWORD_COUNT + 2); -+ BEGIN_RING(4 * vtx_count + 2); ++ BEGIN_RING(3 * vtx_count + 2); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, - 4 * VTX_DWORD_COUNT)); - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ 4 * vtx_count)); -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | ++ 3 * vtx_count)); ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); +- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ++ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } #else /* ACCEL_CP */ if (IS_R300_3D || IS_R500_3D) - BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4); + BEGIN_ACCEL(2 + vtx_count * 4); -+ else if (info->ChipFamily < CHIP_FAMILY_R200) -+ BEGIN_ACCEL(1 + vtx_count * 3); else - BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); -+ BEGIN_ACCEL(1 + vtx_count * 4); ++ BEGIN_ACCEL(1 + vtx_count * 3); - if (info->ChipFamily < CHIP_FAMILY_R200) { - OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | @@ -16294,13 +21421,17 @@ index 277d9b2..c5ad0e1 100644 - } else { - OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | + (3 << RADEON_VF_NUM_VERTICES_SHIFT))); -+ else ++ else if (IS_R300_3D || IS_R500_3D) + OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | RADEON_VF_PRIM_WALK_DATA | - 4 << RADEON_VF_NUM_VERTICES_SHIFT)); - } -#endif + (4 << RADEON_VF_NUM_VERTICES_SHIFT))); ++ else ++ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | ++ RADEON_VF_PRIM_WALK_DATA | ++ (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - VTX_OUT((float)dstX, (float)dstY, - xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); @@ -16312,29 +21443,43 @@ index 277d9b2..c5ad0e1 100644 - xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]); +#endif + if (pPriv->bicubic_enabled) { -+ VTX_OUT_FILTER((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0], -+ xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5); -+ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth), -+ xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0], -+ xFixedToFloat(srcBottomLeft.x) + 0.5, xFixedToFloat(srcBottomLeft.y) + 0.5); -+ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth), -+ xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0], -+ xFixedToFloat(srcBottomRight.x) + 0.5, xFixedToFloat(srcBottomRight.y) + 0.5); -+ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0], -+ xFixedToFloat(srcTopRight.x) + 0.5, xFixedToFloat(srcTopRight.y) + 0.5); ++ /* ++ * This code is only executed on >= R300, so we don't ++ * have to deal with the legacy handling. ++ */ ++ VTX_OUT_FILTER((float)dstX, (float)dstY, ++ (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], ++ (float)srcX + 0.5, (float)srcY + 0.5); ++ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth), ++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0], ++ (float)srcX + 0.5, (float)(srcY + srch) + 0.5); ++ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth), ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0], ++ (float)(srcX + srcw) + 0.5, (float)(srcY + srch) + 0.5); ++ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY, ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], ++ (float)(srcX + srcw) + 0.5, (float)srcY + 0.5); + } else { -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { -+ VTX_OUT((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]); ++ if (IS_R300_3D || IS_R500_3D) { ++ VTX_OUT((float)dstX, (float)dstY, ++ (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); ++ VTX_OUT((float)dstX, (float)(dstY + dsth), ++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); ++ VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); ++ VTX_OUT((float)(dstX + dstw), (float)dstY, ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); ++ } else { ++ /* ++ * Just render a rect (using three coords). ++ */ ++ VTX_OUT((float)dstX, (float)(dstY + dsth), ++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); ++ VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); ++ VTX_OUT((float)(dstX + dstw), (float)dstY, ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + } -+ VTX_OUT((float)dstX, (float)(dstY + dsth), -+ xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]); -+ VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), -+ xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]); -+ VTX_OUT((float)(dstX + dstw), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]); + } if (IS_R300_3D || IS_R500_3D) @@ -16355,7 +21500,8 @@ index 277d9b2..c5ad0e1 100644 if (IS_R300_3D || IS_R500_3D) { - BEGIN_VIDEO(2); - OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); -+ BEGIN_ACCEL(2); ++ BEGIN_ACCEL(3); ++ OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); + OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); } else - BEGIN_VIDEO(1); @@ -16719,7 +21865,7 @@ index ccc1367..5717ead 100644 #ifndef RADEON_VERSION_EXTRA #define RADEON_VERSION_EXTRA "" diff --git a/src/radeon_video.c b/src/radeon_video.c -index ac60166..6249cea 100644 +index ac60166..423ea28 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -89,10 +89,6 @@ static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv); @@ -16733,7 +21879,7 @@ index ac60166..6249cea 100644 static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer; static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity; static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults; -@@ -106,7 +102,6 @@ static Atom xvEncoding, xvFrequency, xvVolume, xvMute, +@@ -106,11 +102,9 @@ static Atom xvEncoding, xvFrequency, xvVolume, xvMute, static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode; @@ -16741,7 +21887,49 @@ index ac60166..6249cea 100644 #define GET_PORT_PRIVATE(pScrn) \ (RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr) -@@ -245,19 +240,6 @@ radeon_crtc_clip_video(ScrnInfoPtr pScrn, +-#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER + static void + radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b) + { +@@ -141,6 +135,37 @@ radeon_box_area(BoxPtr box) + return (int) (box->x2 - box->x1) * (int) (box->y2 - box->y1); + } + ++int ++radeon_covering_crtc_num(ScrnInfoPtr pScrn, ++ int x1, int x2, int y1, int y2, ++ xf86CrtcPtr desired) ++{ ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++ int coverage, best_coverage; ++ int c, best_crtc = 0; ++ BoxRec box, crtc_box, cover_box; ++ ++ box.x1 = x1; ++ box.x2 = x2; ++ box.y1 = y1; ++ box.y2 = y2; ++ best_coverage = 0; ++ for (c = 0; c < xf86_config->num_crtc; c++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[c]; ++ radeon_crtc_box(crtc, &crtc_box); ++ radeon_box_intersect(&cover_box, &crtc_box, &box); ++ coverage = radeon_box_area(&cover_box); ++ if (coverage && crtc == desired) { ++ return c; ++ } else if (coverage > best_coverage) { ++ best_crtc = c; ++ best_coverage = coverage; ++ } ++ } ++ return best_crtc; ++} ++ ++#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER + static xf86CrtcPtr + radeon_covering_crtc(ScrnInfoPtr pScrn, + BoxPtr box, +@@ -245,19 +270,6 @@ radeon_crtc_clip_video(ScrnInfoPtr pScrn, #endif } @@ -16761,7 +21949,7 @@ index ac60166..6249cea 100644 void RADEONInitVideo(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -@@ -1632,13 +1614,12 @@ RADEONSetupImageVideo(ScreenPtr pScreen) +@@ -1632,13 +1644,12 @@ RADEONSetupImageVideo(ScreenPtr pScreen) pPriv->textured = FALSE; @@ -16777,7 +21965,7 @@ index ac60166..6249cea 100644 adapt->PutVideo = RADEONPutVideo; } -@@ -1654,8 +1635,19 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) +@@ -1654,8 +1665,19 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) unsigned char *RADEONMMIO = info->MMIO; RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; @@ -16799,7 +21987,7 @@ index ac60166..6249cea 100644 REGION_EMPTY(pScrn->pScreen, &pPriv->clip); -@@ -1675,7 +1667,7 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) +@@ -1675,7 +1697,7 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv); } if (pPriv->video_memory != NULL) { @@ -16808,7 +21996,7 @@ index ac60166..6249cea 100644 pPriv->video_memory = NULL; } pPriv->videoStatus = 0; -@@ -1699,9 +1691,6 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, +@@ -1699,9 +1721,6 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, Bool setAlpha = FALSE; unsigned char *RADEONMMIO = info->MMIO; @@ -16818,7 +22006,7 @@ index ac60166..6249cea 100644 RADEON_SYNC(info, pScrn); #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) -@@ -1928,7 +1917,7 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, +@@ -1928,7 +1947,7 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, if(pPriv->fi1236!=NULL){ xf86_fi1236_dump_status(pPriv->fi1236); } @@ -16827,7 +22015,7 @@ index ac60166..6249cea 100644 else if(attribute == xvAdjustment) { pPriv->adjustment=value; -@@ -1973,9 +1962,6 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn, +@@ -1973,9 +1992,6 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn, RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; @@ -16837,7 +22025,7 @@ index ac60166..6249cea 100644 if (info->accelOn) RADEON_SYNC(info, pScrn); if(attribute == xvAutopaintColorkey) -@@ -2433,120 +2419,13 @@ RADEONCopyMungedData( +@@ -2433,120 +2449,13 @@ RADEONCopyMungedData( } } @@ -16959,7 +22147,7 @@ index ac60166..6249cea 100644 int offset1, int offset2, int offset3, int offset4, int offset5, int offset6, -@@ -2715,6 +2594,20 @@ RADEONDisplayVideo( +@@ -2715,6 +2624,20 @@ RADEONDisplayVideo( } #endif @@ -16980,7 +22168,7 @@ index ac60166..6249cea 100644 /* keep everything in 16.16 */ if (is_planar) { -@@ -2846,6 +2739,12 @@ RADEONDisplayVideo( +@@ -2846,6 +2769,12 @@ RADEONDisplayVideo( src_w >>= 1; OUTREG(RADEON_OV0_P2_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); @@ -16993,7 +22181,7 @@ index ac60166..6249cea 100644 OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1); OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2); OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3); -@@ -3038,9 +2937,9 @@ RADEONPutImage( +@@ -3038,9 +2967,9 @@ RADEONPutImage( if (idconv == FOURCC_YV12 || id == FOURCC_I420) { new_size += (dstPitch >> 1) * ((height + 1) & ~1); } @@ -17006,7 +22194,7 @@ index ac60166..6249cea 100644 if (pPriv->video_offset == 0) return BadAlloc; -@@ -3150,9 +3049,10 @@ RADEONPutImage( +@@ -3150,9 +3079,10 @@ RADEONPutImage( /* FIXME: someone should look at these offsets, I don't think it makes sense how they are handled throughout the source. */ @@ -17020,7 +22208,7 @@ index ac60166..6249cea 100644 pPriv->videoStatus = CLIENT_VIDEO_ON; -@@ -3233,7 +3133,7 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now) +@@ -3233,7 +3163,7 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now) } else { /* FREE_TIMER */ if(pPriv->freeTime < now) { if (pPriv->video_memory != NULL) { @@ -17029,7 +22217,7 @@ index ac60166..6249cea 100644 pPriv->video_memory = NULL; } pPriv->videoStatus = 0; -@@ -3268,7 +3168,7 @@ RADEONAllocateSurface( +@@ -3268,7 +3198,7 @@ RADEONAllocateSurface( pitch = ((w << 1) + 15) & ~15; size = pitch * h; @@ -17038,7 +22226,7 @@ index ac60166..6249cea 100644 if (offset == 0) return BadAlloc; -@@ -3276,18 +3176,18 @@ RADEONAllocateSurface( +@@ -3276,18 +3206,18 @@ RADEONAllocateSurface( surface->height = h; if(!(surface->pitches = xalloc(sizeof(int)))) { @@ -17060,7 +22248,7 @@ index ac60166..6249cea 100644 return BadAlloc; } -@@ -3328,7 +3228,8 @@ RADEONFreeSurface( +@@ -3328,7 +3258,8 @@ RADEONFreeSurface( if(pPriv->isOn) RADEONStopSurface(surface); @@ -17070,7 +22258,7 @@ index ac60166..6249cea 100644 xfree(surface->pitches); xfree(surface->offsets); xfree(surface->devPrivate.ptr); -@@ -3417,8 +3318,9 @@ RADEONDisplaySurface( +@@ -3417,8 +3348,9 @@ RADEONDisplaySurface( surface->offsets[0], surface->offsets[0], surface->offsets[0], surface->offsets[0], surface->offsets[0], surface->offsets[0], @@ -17082,7 +22270,7 @@ index ac60166..6249cea 100644 if (portPriv->autopaint_colorkey) xf86XVFillKeyHelper(pScrn->pScreen, portPriv->colorKey, clipBoxes); -@@ -3602,9 +3504,9 @@ RADEONPutVideo( +@@ -3602,9 +3534,9 @@ RADEONPutVideo( if (pPriv->capture_vbi_data) alloc_size += 2 * 2 * vbi_line_width * 21; @@ -17095,7 +22283,7 @@ index ac60166..6249cea 100644 if (pPriv->video_offset == 0) return BadAlloc; -@@ -3705,10 +3607,12 @@ RADEONPutVideo( +@@ -3705,10 +3637,12 @@ RADEONPutVideo( RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes); } @@ -17113,7 +22301,7 @@ index ac60166..6249cea 100644 RADEONWaitForFifo(pScrn, 1); OUTREG(RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK); diff --git a/src/radeon_video.h b/src/radeon_video.h -index 096de37..11b8029 100644 +index 096de37..7f1891e 100644 --- a/src/radeon_video.h +++ b/src/radeon_video.h @@ -13,6 +13,10 @@ @@ -17154,7 +22342,7 @@ index 096de37..11b8029 100644 #define METHOD_BOB 0 #define METHOD_SINGLE 1 #define METHOD_WEAVE 2 -@@ -82,13 +86,16 @@ typedef struct { +@@ -82,13 +86,20 @@ typedef struct { xf86CrtcPtr desired_crtc; int size; @@ -17170,18 +22358,29 @@ index 096de37..11b8029 100644 + int bicubic_offset; + Bool bicubic_enabled; + uint32_t bicubic_src_offset; ++ int bicubic_state; ++#define BICUBIC_OFF 0 ++#define BICUBIC_ON 1 ++#define BICUBIC_AUTO 2 + Atom device_id, location_id, instance_id; /* textured video */ -@@ -106,18 +113,12 @@ typedef struct { +@@ -104,8 +115,13 @@ typedef struct { + int src_w, src_h, dst_w, dst_h; + int w, h; int drw_x, drw_y; ++ int vsync; } RADEONPortPrivRec, *RADEONPortPrivPtr; -- ++int ++radeon_covering_crtc_num(ScrnInfoPtr pScrn, ++ int x1, int x2, int y1, int y2, ++ xf86CrtcPtr desired); + void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - +@@ -113,11 +129,6 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); diff --git a/radeon-modeset.patch b/radeon-modeset.patch index ad40c1a..d12226f 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -1,58 +1,306 @@ -commit e3b394a58329df2efe1b57f369cefe6803b5f853 +commit 5b9a9a964c92859cce4f31e3121cb26b11b4bc63 +Author: Dave Airlie +Date: Sat Dec 20 09:14:05 2008 +1000 + + radeon: drop old CS2 setup + +commit 80a220979642ff99a23cd0af59b0fcafc74da2e2 +Author: Dave Airlie +Date: Fri Dec 19 12:37:01 2008 +1100 + + radeon: only do mappings if direct rendering is enabled + +commit 399da3eeea3d273db920e67bffc47c11b688ca7d +Author: Dave Airlie +Date: Tue Dec 9 13:29:18 2008 +1000 + + radeon: upstream fix for Init3D vs switch to/from 2d/3d + +commit 6105102abaa70b1e9c1c24a6f48ba9b4f6a63496 +Author: Dave Airlie +Date: Mon Dec 8 14:19:47 2008 +1000 + + radeon: only update dri buffers if DRI enabled + +commit aef93b70e7b1d0b1d393582273d549551be198f6 +Author: Dave Airlie +Date: Mon Dec 1 15:31:08 2008 +1100 + + radeon: don't have 2D and 3D in one CS buffer + +commit 4fb18164866698d9d42f8cf41fdad3cf10ff34f4 +Author: Dave Airlie +Date: Wed Nov 26 16:09:29 2008 +1100 + + radeon: set touched flag on pinned buffers + +commit 26ea3f4afcf90fbb25abbbd4b5ac2433a63425c0 +Author: Dave Airlie +Date: Wed Nov 26 16:04:35 2008 +1100 + + radeon: fix up some of the touched by gpu handling and force gtt handling + + this fixes DFS on the rs690 + +commit 86447551a72e216df71fca64f5e16ded22c5a1ad +Author: Dave Airlie +Date: Wed Nov 26 12:52:24 2008 +1100 + + radeon: brutal attempt to fix RS4xx and RS6xx by flushing more often + + this might take more CPU but hopefully leads to stabler GPU + +commit 049244cc1a430e46497ad730c54a5e1e66bb7a4c +Author: Dave Airlie +Date: Tue Nov 25 17:20:44 2008 +1100 + + radeon: rs690 stabilisation fixes. + + Flush the VAP due a IB hang on the VAP setup regs. + Flush the TX earlier. + Emit a right to SC_CLIP_RULE to flush as per r500 docs. + +commit ba06b37bde0ad00f8a6b12003d56aeb603227143 +Author: Dave Airlie +Date: Sun Nov 23 17:56:02 2008 +1000 + + radeon: wait for rendering before doing UTS + +commit f36db245fac91aad08b4cd2c131e0c47c21bb950 +Author: Dave Airlie +Date: Sun Nov 23 17:54:27 2008 +1000 + + radeon: stop this_op_read from going negative + +commit b1121141af82075ec16edfdd6095320000f4504b +Author: Dave Airlie +Date: Sun Nov 23 17:52:42 2008 +1000 + + radeon: return flush for conflicting domains + +commit d7f1cebb0cf2d5a8110606e7ef22284cc256df72 +Author: Dave Airlie +Date: Sun Nov 23 17:50:47 2008 +1000 + + radeon: only reset state2d before emitting cache flush + +commit 0f58052bcdce741aa0f6bb63566c390d7c246632 +Author: Dave Airlie +Date: Thu Nov 20 16:48:33 2008 +1000 + + flush on UTS if any references + +commit a29231ab45efc153b6ab1ad19e960d2294aa85ab +Author: Dave Airlie +Date: Thu Nov 20 16:44:40 2008 +1000 + + radeon: add gart vs vram writes + +commit 298e92586d11439bc22aab2cb2f7f61f1e80d70f +Author: Dave Airlie +Date: Thu Nov 20 16:37:07 2008 +1000 + + radeon: improve DFS performance for non-vram objects + +commit 2737e395af3fac9707ea7e05e1dd6aaf2dcc303e +Author: Dave Airlie +Date: Wed Nov 19 14:49:44 2008 +1000 + + radeon: scrap state on LeaveVT not EnterVT + +commit 99e240bbfe3990be735cfa90c7c9e2d560c7ea6e +Author: Dave Airlie +Date: Wed Nov 19 11:08:34 2008 +1000 + + radeon: even more typos + +commit 523e6ae553b4ddffdf82d3759d6b6b63a0230144 +Author: Dave Airlie +Date: Wed Nov 19 07:51:03 2008 +1000 + + radeon: oops bad typo + +commit 05a8c61ef69d4270606129426e45d17bf77d0bbc +Author: Dave Airlie +Date: Tue Nov 18 16:09:10 2008 +1000 + + radeon: even if kernels fails, struggle onwards + + try and keep the session going even if visual glitches happen + +commit 52459be7e841e38e609dd4abad9a67848399219e +Author: Dave Airlie +Date: Tue Nov 18 15:46:46 2008 +1000 + + radeon_bufmgr: much more complete size check functionality + +commit 9910bcbe2b85e3242e2373111605d117e6f3a29d +Author: Dave Airlie +Date: Tue Nov 18 14:33:44 2008 +1000 + + radeon: I fail at uint32_t division + +commit f3f4b0574cf9eb01b69c8ebe7a7da0e05b32f1e4 +Author: Dave Airlie +Date: Tue Nov 18 12:06:02 2008 +1000 + + radeon: workaround O(wtf) logic in post_submit bufmgr + +commit d75dafc38eda798bf4f91b5f8e040d8894631d7c +Author: Dave Airlie +Date: Mon Nov 17 19:19:43 2008 +1000 + + radeon: set emit limit to 90% VRAM + +commit 53eb14298f7b493968462606318301bfa3d62a81 +Author: Dave Airlie +Date: Mon Nov 17 16:16:51 2008 +1000 + + radeon: use get/set master ioctls + +commit 4c154285ebbda9ff5848f02397ff698dc9e57bf3 +Author: Dave Airlie +Date: Fri Nov 14 15:56:16 2008 +1000 + + radeon: make space accounting a lot smarter + +commit 5c7b6f8b8e5a50f49f42658553a66d5fbcd7ae8d +Author: Dave Airlie +Date: Fri Nov 14 15:55:12 2008 +1000 + + radeon: retry on CS2 EAGAIN + +commit 99e9d3981c323ada2aa0c1bbe976a0e4a9c450e5 +Author: Dave Airlie +Date: Fri Nov 14 15:20:59 2008 +1000 + + radeon: add src/mask/dest to fallbacks + +commit 455e9f5f6e5a3e648ffd6135570fbc53abd25609 +Author: Dave Airlie +Date: Fri Nov 14 15:20:37 2008 +1000 + + radeon_memory: align all allocations + +commit 16a417dfeda8d991fb32770280bfe614f5c79f96 +Author: Dave Airlie +Date: Fri Nov 14 11:03:34 2008 +1000 + + radeon: force gtt for mmap after fallbacks + +commit f3f900ff53b8d46614e5757f958cac8b88ef53bb +Author: Dave Airlie +Date: Mon Nov 10 14:18:17 2008 +1000 + + radeon: add more buffer info + fix read objects too big fallback + +commit 04a61bf3b5be1a47436ac7a39b40d2dd687962e1 +Author: Dave Airlie +Date: Mon Nov 10 11:47:02 2008 +1000 + + radeon: remove old exa bufmgr not used anymore code + +commit 4fe1f1458745895c37289c43d342f17dae24a1da +Author: Dave Airlie +Date: Mon Nov 10 11:18:27 2008 +1000 + + radeon: fix crtc dpms + + need to find a better way to switch displays off + +commit c0a8c20b8ad284513d933ef67dc469df222b9e04 +Author: Dave Airlie +Date: Mon Nov 10 11:18:02 2008 +1000 + + radeon: fix textured video corruption + + at least workaround it + +commit 4363273e081fdfc67eee2120693a0a2350b83d9f +Author: Dave Airlie +Date: Sat Nov 8 14:48:29 2008 +1000 + + radeon: add DPMS support for connectors + +commit 332493f1446d929c565e54db15936db5e6fbcb67 +Author: Dave Airlie +Date: Fri Nov 7 16:20:09 2008 +1000 + + radeon: fix rotation of right-of heads + +commit 1962610bfcf611d9b5221852a851adf012880b63 +Author: Dave Airlie +Date: Mon Nov 3 14:51:43 2008 +1000 + + radeon: respect fb tex percent + trust kernel values + +commit 9ec4f7ea480d8cf5431f2e5f0c26ac5293a26015 +Author: Dave Airlie +Date: Fri Oct 31 15:05:14 2008 +1000 + + radeon: remove workaround hack since kernel is hopefully fixed + +commit e0d4781952058834b31cd8decbd8054dcd544974 +Author: Dave Airlie +Date: Fri Oct 31 15:04:31 2008 +1000 + + radeon: workaround use after free + +commit 40113ead912a015f619cce99635d5e1e823ffb7b Author: Dave Airlie Date: Thu Oct 30 13:53:02 2008 +1000 radeon: setup accel dfs for PCIE cards only if drm_mm -commit 2a85b00b38da8f5419837a9b4504aa1ba69b2a32 +commit 354b8569178b15ad9166e6cd85ba31608dd3b53e Author: Dave Airlie Date: Thu Oct 30 10:00:10 2008 +1000 radeon: fixup name handling for bufmgr -commit b57a389fa222ecb832bb72b30f2602bf086db892 +commit da0ead1641f0b0912a269db8af1d6ad0fe24bcc3 Author: Dave Airlie Date: Thu Oct 30 09:59:11 2008 +1000 radeon: fix memory leak in CS2 code -commit ffde9b0fa3157e956e6bc0580f10d21f191be327 +commit 882a213a037b3a220f40b7de815c687a1bb6005f Author: Dave Airlie Date: Tue Oct 28 20:35:19 2008 +1000 return on empty IBs, flush happen in the kernel -commit 1714b8e5443da01d838e9804166b67fcb3a6ec45 +commit 098da7dd3760ec3716eba7da8212119911ccda68 Author: Dave Airlie Date: Tue Oct 28 10:16:09 2008 +1000 radeon: remove some debugging -commit 17b7b76a702640462a3878ae745fd1f5ddd32f19 +commit 086cafeef09042819d3cd0a849c9bd88b74e5791 Author: Dave Airlie Date: Tue Oct 28 06:40:31 2008 +1000 radeon: enable gem wait rendering. -commit 2171a9d834be69e002a93fe440450ff532758e93 +commit de29375198ff5d26b54fbe69d312e38782c4fa57 Author: Dave Airlie Date: Mon Oct 27 16:51:00 2008 +1000 radeon: add new CS submission scheme -commit 3a29ac76d724c9a0ed6f4c2b832178594db94a0a +commit 9bdbba5e7c178433f66121e300c9a833c403914b Author: Dave Airlie Date: Thu Oct 23 17:05:12 2008 +1000 radeon: really rough effort at vram limit setting -commit dddb524ded5b4b3b663cf332a97899b24134974e +commit dec38d7aff0f6de7116ac1028f186eb1bb4501bd Author: Dave Airlie Date: Thu Oct 23 17:04:51 2008 +1000 radeon: this shouldn't fail but it did once while debugging so patch up -commit fe706004af67894eb7cf661ebd42305a754f3381 +commit b1949a68b655006cad76f2e13f4e6a009469a993 Author: Dave Airlie Date: Thu Oct 23 10:43:09 2008 +1000 @@ -60,19 +308,13 @@ Date: Thu Oct 23 10:43:09 2008 +1000 hopefully since the alignment got fixed this doesn't break anything -commit 4e24123007f8dd8bb2aee5398778bf36d920521e -Author: Dave Airlie -Date: Tue Oct 21 15:50:31 2008 +1000 - - radeon: avoid unnecessary emits - -commit e207eb6181692d8afe893fcd3b39f38bd3cf202b +commit 5726b7b4e0a50bc8696ac9a190722d2ccca73304 Author: Dave Airlie Date: Tue Oct 21 15:50:17 2008 +1000 radeon: cleanup reserved space calcs -commit 21d9f5b0d9507404e6a2c55955420747bee2cbfb +commit e5bb8a41208cc9f2199d49d42986264942a5dfbc Author: Dave Airlie Date: Tue Oct 21 15:49:48 2008 +1000 @@ -82,109 +324,109 @@ Date: Tue Oct 21 15:49:48 2008 +1000 seems to cause this failure. but I probably don't have time to track it down before release. -commit dab489dc784bb14ef4a64b3ecec1c46568210c22 +commit f4c4d8377b0ea9688172f6c20842f19659ad8f43 Author: Dave Airlie Date: Sun Oct 19 18:27:53 2008 +1000 radeon: fixup tex offset for no modeset -commit 6b66d506a63c49abf781c390261c460f2183cd84 +commit e0e0d5bee96ed4c80b50a84858792c8f2c0f5ae8 Author: Dave Airlie Date: Wed Oct 15 17:01:34 2008 +1000 radeon: add DFS support for CS -commit f4f95f0a15308d4a8cb38c1ed73a0edb2e8b906a +commit 5cd19b7fa508343537ffb60b04ec0897a8350615 Author: airlied Date: Wed Oct 15 23:55:13 2008 +1000 radeon: add r100/r200 support for EXA render -commit d8cbb2f90b4d399c1ce3ac4cfdf79894bae8d06a +commit 6d9a071719237af4da38ded3f72abee540a9c0d5 Author: Dave Airlie Date: Mon Oct 13 16:59:02 2008 +1000 radeon: fix switch mode path so nexuiz starts -commit 65488679e8443cbebbd4ff9585ac34b1ae42da55 +commit de0ac9eeff9d68e6d429b7b0f5bc6cb02a7e248b Author: Dave Airlie Date: Fri Oct 10 15:29:24 2008 +1000 remove gem buf caching useless on radeon -commit db1d00f76acdc9868546694d4f3ab3a869ad2396 +commit 46da4cac3a825be818eced41dd4d04e6e8cc4b46 Author: Dave Airlie Date: Fri Oct 10 15:18:41 2008 +1000 radeon: drmmode make names same as for non-kms drivers -commit b1a87b4b67cae5a31c87f884f40f7116ac8ecdf2 +commit 8938b8d46cd24fa38b0bfe58b8e19788e25b2fe6 Author: Dave Airlie Date: Fri Oct 10 15:10:28 2008 +1000 radeon: fix rotation under kms -commit 1eb523e28c7a1f69a9fe7b247b7828399d7e6a75 +commit 7d6238f23cad0ed2037e66c2678931e8c583a0e3 Author: Dave Airlie Date: Fri Oct 10 14:44:39 2008 +1000 radeon: remove testing fallback -commit ab876f2a090a5aabb0712aa5388f224e651c83e7 +commit 9969552076c7884d90976be20325f172dbeeeb87 Author: Kristian Høgsberg Date: Fri Oct 10 10:57:47 2008 +1100 radeon: add copy fb contents patch -commit 3bd7fcef66e093ecf2d5c2badf60b8f5bb3bdd4b +commit 1b027f29f7748301385a35a8f59408ac4ee2283e Author: Dave Airlie Date: Fri Oct 10 10:57:20 2008 +1100 bufmgr: turn off debug -commit 44fb767aa95e5f0725386106b89d0782fd53b768 +commit 05394792a97282ab31e9a472541bc5698b392a55 Author: Dave Airlie Date: Fri Oct 10 10:38:38 2008 +1100 radeon: fixup modesetting code after rebasing to master -commit fc5d27b1b7da64fbb4ba0b4156454291a3a243c5 +commit da9ae4160a9b89c7c005c5743e1e9255493d786a Author: Dave Airlie Date: Thu Oct 9 16:34:52 2008 +1100 radeon: misc cleanups in exa -commit c7c2e6f7b2b12c55d0153d9c64fcf39eda5e843e +commit 180df18055f89cd109099e1f43ba71ee439ead24 Author: Dave Airlie Date: Thu Oct 9 16:34:23 2008 +1100 radeon: fix UTS for non-modesetting -commit 62fd7f4335474e7a3f47c6d9aaf6c162ebddc8a5 +commit d18aeb288e13cda262dc676ed11d90fe2ce2d348 Author: Dave Airlie Date: Thu Oct 9 16:33:59 2008 +1100 radeon: fix exa limits problem - shouldn't have been resetting scissor -commit 10602f918013e3799ef41284e71307863aae1aa6 +commit 91821d35bf233e97b1dd1ff12999e10445d8c3fa Author: Dave Airlie Date: Wed Oct 1 11:21:53 2008 +1000 radeon: fixup for latest libdrm changes -commit 088cad33ef83802f42dce1a5684eb813b9bfe251 +commit 4baa05e54f603c72e8d8abf266fa3d815de187ac Author: Owen Taylor Date: Fri Sep 26 16:17:49 2008 -0400 Don't flush when mapping a newly created pixmap into system ram If we have a pixmap that has never been mapped into vram (and thus never written to by the GPU), there is no need to flush the graphics pipeline and wait for idle before starting to write to it. -commit ec7a5b4b701da283e84a899bcfaf35b202043f7b +commit 8b66f282da5f97ab4f4045f90337c6a325a1003c Author: Dave Airlie Date: Mon Sep 29 16:32:51 2008 +1000 radeon: hopefully fix textured xv -commit eac0d78d462e49ce0ee178a87c06d0eb697ed8b8 +commit 62517a660bb21daf3910ec719af59fe07e463b9e Author: Dave Airlie Date: Fri Sep 26 11:38:36 2008 +1000 @@ -192,55 +434,55 @@ Date: Fri Sep 26 11:38:36 2008 +1000 since we are relocating in the kernel we don't need these -commit 8ad885b0f044bda60d38664a62c65f9d7a4f5c47 +commit 5ad65dcc52633d6925a0d458dbf1ed8c7ed62e7a Author: Dave Airlie Date: Fri Sep 26 10:46:20 2008 +1000 radeon: fixup after mertge -commit f3efa0c398d131458945b0b1a89c3fc7887e51f6 +commit 99db5b3a2c60433ddb23ae8a45e2ea4f4dd3f48b Author: Dave Airlie Date: Fri Sep 26 10:34:41 2008 +1000 radeon: fix issues with emitting DST PIPE on cards that don't use it -commit ae03476547568e426c9448b0c13fa25ef3a6a2dd +commit c157c9541cb71d4b8d27bb0d6847e570a6712105 Author: Dave Airlie Date: Wed Sep 24 17:12:19 2008 +1000 modesetting: fixup bits of drmmode_display.c -commit 5140bc984f98661ba6bc8e70025a9f43024a7551 +commit de2ce63ea5c21796490d541e42bf312915992e25 Author: Dave Airlie Date: Wed Sep 24 15:42:01 2008 +1000 r600: fixup for kms -commit bb0cfe3035c03d3703aa0a960790b6e5365759b4 +commit d0090ee991d1b427ea9da03828f0e70c65f9ec92 Author: Dave Airlie Date: Sun Sep 7 08:01:56 2008 +1000 modeset: fix AddFB for current tree -commit b90e88b455e250a2386320005385f3d70b2150f7 +commit 1ecf98ff8c303d80bf39570f31a768d3f5731b2c Author: Dave Airlie Date: Thu Aug 14 10:52:52 2008 +1000 radeon: disable overlay for modesetting for now -commit 5c5736604e6a1bc280821bd92f3714e0c9e7d7d3 +commit 57aafeb0cac1e145c679ace1fc16dc2d74ea392f Author: Dave Airlie Date: Thu Aug 14 10:52:42 2008 +1000 radeon: no need for this anymore -commit aa09c6d7bb28ce5fe3efbe23cf5aa9ce55275fc6 +commit d85b13ca8a17b3ed22460b2ff0f448aff5eed01a Author: Dave Airlie Date: Fri Sep 5 16:32:01 2008 +1000 radeon: fix up for suspend/resume - uses new API -commit 3bf412b019c03e3e8d392a896e79d9fd9cf75a51 +commit 9099983739f8a9fb02cf23578770d079b66b20e6 Author: Dave Airlie Date: Wed Aug 27 13:09:55 2008 +1000 @@ -248,7 +490,7 @@ Date: Wed Aug 27 13:09:55 2008 +1000 this should fix 3d again for now at least -commit 7e30990b969c5789d61bd61ec8d2d9955c5b9f86 +commit 337e87d1f2becc82b8a5c5dd01b20c339fa1f7a5 Author: Dave Airlie Date: Tue Aug 26 18:29:23 2008 +1000 @@ -261,49 +503,49 @@ Date: Tue Aug 26 18:29:23 2008 +1000 Probably need some sort of in-kernel re-use. -commit fbb7f9cf4820bac91ad7a7684fcc8812dd8bc525 +commit 710aabc060388d5c60a29b66f74d0ac16d61dd1d Author: Dave Airlie Date: Mon Aug 25 11:37:48 2008 +1000 radeon: add an initial GEM bufmgr -commit f66550984636e426ff05d3f9109c55c36cf4ab42 +commit 225e8b6013eda2f8c6dc434c02b04566f4a5b835 Author: Dave Airlie Date: Mon Aug 25 11:37:20 2008 +1000 radeon: implement simple UTS -commit 8e22a14716ba852e3945a6588df9b6b77ba10a4c +commit c296ff562755b9f98ba26aab0cd6349b4cc3ccf0 Author: Dave Airlie Date: Fri Aug 22 15:34:58 2008 +1000 radeon: add read/write domains properly -commit 6a5952e34df4c4d38404e6b88043cc749aeeba6a +commit 0b0c142f21330cc0ae84aadf08d8572c02d2bcaa Author: Dave Airlie Date: Fri Aug 15 11:25:31 2008 +1000 radeon: fix some rotate bugs -commit 22d4ea4b1b831f50fe2d2f9c90bd2a529a1f01cd +commit a17e4658bc1790753d2fe630eefb4f6dfec4a292 Author: Dave Airlie Date: Fri Aug 15 11:16:18 2008 +1000 radeon: when create fake bos, they are already mapped -commit 216cd29e2d7354181b8b32dde374bf0ad11dc90d +commit fe8acaa8e666c60af1c0db8f31f24be190f73718 Author: Dave Airlie Date: Fri Aug 15 11:15:58 2008 +1000 exa: remove wrong assert -commit b3ac04aef5148856ecb7df2f83cb858fd1d8df29 +commit 6b9b175962c7347b3914ea38ca4cb589a9a5fc0a Author: Dave Airlie Date: Tue Aug 12 19:27:44 2008 +1000 radeon: start to work on rotate pixmap support -commit 043dd60d8ddcbc00367839be5d0cecf89533bfdf +commit 736036972ee1785b04645d04e93f5fe38127ca00 Author: Dave Airlie Date: Tue Aug 12 18:28:23 2008 +1000 @@ -311,13 +553,13 @@ Date: Tue Aug 12 18:28:23 2008 +1000 exa pixmaps work now but they are slow -commit 5b713057af6362d78c125a90f0cda727e9f511d1 +commit d2d3cd1d2b422c6b99cb4c1334009b01adb1988b Author: Dave Airlie Date: Thu Aug 7 17:52:04 2008 +1000 further pixmaps on EXA -commit 9e245b41674e25c23dbefda37a3e13611206c05f +commit 553ce05ab5817e2fc1153b57cda5a5d3378415f7 Author: Dave Airlie Date: Thu Aug 7 11:22:46 2008 +1000 @@ -328,7 +570,7 @@ Date: Thu Aug 7 11:22:46 2008 +1000 src/radeon_exa.c src/radeon_memory.c -commit 0569311ee032498ac73f176baebd716146b07342 +commit 7276e7b7c7287859d43ce702644eb4202ae36348 Author: Dave Airlie Date: Tue Aug 12 15:31:03 2008 +1000 @@ -336,103 +578,103 @@ Date: Tue Aug 12 15:31:03 2008 +1000 This doesn't work, we really need EXA pixmaps for this stuff -commit 9054524b3bdc8de3588f838401f56c49d1528757 +commit b5226f66c35ae7a01cdcfa67d52582ec942a2eeb Author: Dave Airlie Date: Tue Aug 12 14:40:18 2008 +1000 radeon: use buffer names -commit eb6b80595c9dd731d001058ff997f5e5c35710e0 +commit 443471b0c2581090615a35f4e93d2730919b877f Author: Dave Airlie Date: Tue Aug 12 14:38:56 2008 +1000 ati: fix do adjust mode -commit e44e62cde9c1e19811bd0f9a77068d8f0927e837 +commit fe8e25bbf8341dc9647332d846a0eee4d04ca9cb Author: Dave Airlie Date: Tue Aug 12 09:38:48 2008 +1000 FEDORA: update offsets in DRI private -commit 0e27902438773facffc304e2f6bf43d6a926ab81 +commit 029e79b781bac59aa78593419f157fb52b21f6ad Author: Dave Airlie Date: Tue Aug 12 09:10:18 2008 +1000 radeon: add vt bind flag -commit 648360f17f285bc5cd0498161dcb0cb61eae39cd +commit 1145f94ac69742d02b0e7140eb8cae350c661959 Author: Dave Airlie Date: Wed Aug 6 13:30:54 2008 +1000 radeon: warning cleanups -commit d425be2a405ffd1af684d50260b16c6877fdda56 +commit ac6f7f02a3c6399f1c549fa91030f790728633e8 Author: Dave Airlie Date: Wed Aug 6 13:18:52 2008 +1000 radeon: remove debugging -commit fe75573b5cc05590430b7ffb8b7e10666547a438 +commit 6c609f5c7375335cda6b76185bada8731d68988f Author: Dave Airlie Date: Wed Aug 6 13:17:31 2008 +1000 radeon: add code to set memory map and not futz with mappings -commit 9e586c9e941d69bd5751647f4c891c43a893ac19 +commit 503b618de3c8ceaf89bd70220b9f7ca64a94e15c Author: Dave Airlie Date: Wed Aug 6 13:16:56 2008 +1000 drm: don't futz with framebuffer when no drm_mm -commit 20e17c8f386fa25418ea5fa5265785d9e52ca97f +commit d55a53a1f9dfb0a6d168d48e342d0049ef947c75 Author: Dave Airlie Date: Tue Aug 5 16:47:21 2008 +1000 radeon: undef OUT_RELOC -commit dc14747b1d7446fafe3bc0a639ee964c3944f310 +commit 61060d28036fcfe07e185069ef398f758b7501c2 Author: Dave Airlie Date: Tue Aug 5 16:37:52 2008 +1000 radeon: add stdint/lib to check for modesetting -commit 5ad05af2c23e5cb267234d077c43bafb87c35a5c +commit a2b4af49d7e49a91d4e1bbef5168cbc7d9fc365b Author: Dave Airlie Date: Tue Aug 5 16:07:31 2008 +1000 fix whitespace -commit 97bb89257ec8a5bac629b8e74435ab40389665df +commit 04824237e3b5945c79b56466654ab2b135382e04 Author: Dave Airlie Date: Tue Aug 5 16:07:07 2008 +1000 radeon: fix build issue -commit ccc8673d3e0c37e3ff8f8627d215086e607d0a60 +commit fee0bc168be7f051dd74794e5e3f3b60ecbbbe3c Author: Dave Airlie Date: Mon Aug 4 16:27:55 2008 +1000 radeon: free all pinned memory on server shutdown -commit 894aaf6ec6a8ba851d836358adc28cd122b5270a +commit 45f14242535069259897deff31755ad0df8b997a Author: Dave Airlie Date: Mon Aug 4 16:11:30 2008 +1000 radeon: get textured video working on the memory manager -commit 2c9a7762718ef0560a383f2729ecf72baecb669b +commit ee28a1ab379d16a93c47e6305c2ecdd22ab0bbc2 Author: Dave Airlie Date: Mon Aug 4 16:11:18 2008 +1000 radeon: convert bus addr to void pointer -commit 32f376d062dea6eabb8eca23a23ec9f2967b2073 +commit db3ed400b8cbf04c0195c00be931c299a55e773c Author: Dave Airlie Date: Mon Aug 4 15:11:13 2008 +1000 radeon: avoid z cache flushes if not needed -commit bbd6b19554096bd4880405aa9dfd378cbef8471e +commit 6673579a462f948aede961a924e17e61306715a0 Author: Dave Airlie Date: Wed Jul 30 17:04:22 2008 +1000 @@ -440,13 +682,13 @@ Date: Wed Jul 30 17:04:22 2008 +1000 We only add fake frontbuffer mapping as DRI clients expect one. -commit b419e9c91730c2c9bc94f9df8fba4310d0c4f554 +commit 30a078524f7c71d59ee834725a3f2c11a082c21f Author: Dave Airlie Date: Tue Jul 29 16:50:03 2008 +1000 radeon: exa through the handle relocation function -commit 0c2b073855ead62eca8757c4a52b3c7838d6ec3d +commit 39e5484735471e589e52ad1c91df9b22c2a44f02 Author: Dave Airlie Date: Tue Jul 29 14:58:22 2008 +1000 @@ -454,85 +696,85 @@ Date: Tue Jul 29 14:58:22 2008 +1000 This lets the kernel use the 2D blit engine in theory -commit bb18f9fb7232ab2182fb40d2aa79fb4afb1fc19b +commit 1e43289fadd17898028443cce2ee33e00eae7b89 Author: Dave Airlie Date: Mon Jul 28 17:48:59 2008 +1000 new command submission attempt -commit aca38e9562a307f7a668b3aeffc849bd3658eaab +commit 842040a30b0ba5d586f42e1c64a5651da2ac6cae Author: Dave Airlie Date: Mon Jul 28 17:48:08 2008 +1000 radeon: fixup over fluishing problem -commit 06494b222640cb4315231c31fa172a0345fb3497 +commit 6aa4d546a70fe88cbb0993ec88d0241c8da73704 Author: Dave Airlie Date: Mon Jul 28 17:44:51 2008 +1000 hack for now: divide texture size by 2 -commit 7e2f6d6a14a7736151db128348b9578faeb3e134 +commit 3aab05da72750341430a87c60ee8253994fff577 Author: Dave Airlie Date: Fri Jul 25 17:07:20 2008 +1000 radeon: fix dri message -commit 28d65fc64b1195aa3f3592979d9ed15d0b26847b +commit dbe42d159f91ed2ccf590be366ec27a41b140083 Author: Dave Airlie Date: Fri Jul 25 15:11:58 2008 +1000 radeon: fix pool which caused memory corruption -commit 2bb5310123a8fc4838ab17d6aa6fc0b30ec91d8a +commit 20d94ec16fe6f7f826960adeb40cfddef641b60a Author: Dave Airlie Date: Fri Jul 25 14:59:07 2008 +1000 radeon: get DRI to attempt to start up -commit aa657a2e9698ae25e9ad985b205e9bf051338e3b +commit cf154e884bf0d72fbc3cb907966e8940b826c6c9 Author: Dave Airlie Date: Fri Jul 25 14:58:23 2008 +1000 radeon: call the right sync function -commit 02ff76a1adcfd1ea11798c545256a1021fbba1ce +commit 8c866bd98f3ba2c40b5c23ce73c047596cb18f21 Author: Dave Airlie Date: Fri Jul 25 14:57:21 2008 +1000 radeon: unmap memory from objects -commit cbb97ec98e1d67cab9fc10e4bb8e12a01972a041 +commit 80bd230f4539d0b0564ec78f0d8b1dc179ba564a Author: Dave Airlie Date: Wed Jul 23 10:59:16 2008 +1000 use CP for 3D engine with modeset -commit a479fcf9c158e232cf2c97de007616a9854e455d +commit 18638ff0d88051c333fe986f24c6a9d4a45e9e94 Author: Dave Airlie Date: Wed Jul 23 10:59:04 2008 +1000 radeon: fix DFS -commit 7b39d83234e7c87f59817e6bdc9f4ae8eae4df15 +commit e6f23a36efa674b12be4bbebd6c48dd6552405d4 Author: Dave Airlie Date: Wed Jul 23 10:48:45 2008 +1000 radeon: get the fb location right -commit 72dc11e13790d24e8da308231dc0643ce072771e +commit 81c3c56848283e1da51a7a4d696705457eefea5f Author: Dave Airlie Date: Tue Jul 22 18:08:25 2008 +1000 radeon: make at least the EXA stipple work.. -commit 95b985e65164788ac76ef5c59e6b9b9cb8f931a1 +commit 011ad06973f0866d700a97694b5225eae14e56ad Author: Dave Airlie Date: Tue Jul 22 18:07:15 2008 +1000 radeon: disable debugging for now -commit 695387eaecb3c626d81ee4f326f49fb5093d65fe +commit 33c1418c438aced27890ddb7ac9b026474c658dd Author: Dave Airlie Date: Mon Jul 21 18:40:14 2008 +1000 @@ -545,19 +787,19 @@ Date: Mon Jul 21 18:40:14 2008 +1000 doesn't work think the offsets are all wrong. -commit cf3caa7ca957fff69a9f11624e61017c30068f95 +commit 78dcbaf46bf7363fdf88802b68d87c5fa1e6ef29 Author: Dave Airlie Date: Fri Jul 18 13:46:41 2008 +1000 modesetting step 1: have X and a cursor -commit 409e8b3d156e16dd2300a11ae99f4d552dd84e20 +commit 90d1561470adf8466acec16c281e60fc8f6ec89b Author: Dave Airlie Date: Thu Jul 17 09:59:19 2008 +1000 radeon: add radeon_memory.c -commit ee9f68d728aae8fff4f4194d8e6d6d70f6168ce2 +commit 6f0abb40c55511dbece6a8b2f4aad40953229de9 Author: Dave Airlie Date: Tue Jul 8 16:55:27 2008 +1000 @@ -565,7 +807,7 @@ Date: Tue Jul 8 16:55:27 2008 +1000 use drm gart code if available -commit 8e4a09253d52e9c097871b06c522f1c7ef2b9b14 +commit b0a91607a6fdfe000a42d2abedae6572d43884be Author: Dave Airlie Date: Mon Jul 7 16:54:35 2008 +1000 @@ -576,16 +818,16 @@ Date: Mon Jul 7 16:54:35 2008 +1000 useful steps towards getting kernel modesetting -commit 12e71eaf7999520d23d50cfbcfc0299b2bdf7a9d +commit bc5ef65797de0b20a4cc1ca5189d5bf06fc4f47f Author: Dave Airlie Date: Fri Jul 4 10:39:34 2008 +1000 port to using drm header files diff --git a/configure.ac b/configure.ac -index b8c18a6..8b126b5 100644 +index 5ffe0d9..d495c44 100644 --- a/configure.ac +++ b/configure.ac -@@ -115,6 +115,15 @@ if test "$DRI" = yes; then +@@ -114,6 +114,15 @@ if test "$DRI" = yes; then if test "$have_damage_h" = yes; then AC_DEFINE(DAMAGE,1,[Use Damage extension]) fi @@ -602,7 +844,7 @@ index b8c18a6..8b126b5 100644 save_CFLAGS="$CFLAGS" diff --git a/src/Makefile.am b/src/Makefile.am -index d65a3e4..ff54329 100644 +index d65a3e4..1be325a 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -90,12 +90,13 @@ radeon_drv_ladir = @moduledir@/drivers @@ -617,7 +859,7 @@ index d65a3e4..ff54329 100644 $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ - $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c + $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c \ -+ drmmode_display.c radeon_bufmgr_exa.c radeon_bufmgr_gem.c radeon_dri_bufmgr.c ++ drmmode_display.c radeon_bufmgr_gem.c radeon_dri_bufmgr.c if XMODES radeon_drv_la_SOURCES += \ @@ -631,10 +873,10 @@ index d65a3e4..ff54329 100644 + radeon_dri_bufmgr.h diff --git a/src/drmmode_display.c b/src/drmmode_display.c new file mode 100644 -index 0000000..7ac30f8 +index 0000000..3cb2fb9 --- /dev/null +++ b/src/drmmode_display.c -@@ -0,0 +1,771 @@ +@@ -0,0 +1,864 @@ +/* + * Copyright © 2007 Red Hat, Inc. + * @@ -672,6 +914,9 @@ index 0000000..7ac30f8 +#include "radeon_drm.h" +#include "sarea.h" + ++/* DPMS */ ++#define DPMS_SERVER ++#include + +static Bool drmmode_resize_fb(ScrnInfoPtr scrn, drmmode_ptr drmmode, int width, int height); + @@ -754,9 +999,17 @@ index 0000000..7ac30f8 +}; + +static void -+drmmode_crtc_dpms(xf86CrtcPtr drmmode_crtc, int mode) ++drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode) +{ ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); ++ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; ++ drmmode_ptr drmmode = drmmode_crtc->drmmode; + ++ /* bonghits in the randr 1.2 - uses dpms to disable crtc - bad buzz */ ++ if (mode == DPMSModeOff) { ++// drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, ++// 0, 0, 0, NULL, 0, NULL); ++ } +} + +static PixmapPtr @@ -846,10 +1099,12 @@ index 0000000..7ac30f8 + saved_y = crtc->y; + saved_rotation = crtc->rotation; + -+ crtc->mode = *mode; -+ crtc->x = x; -+ crtc->y = y; -+ crtc->rotation = rotation; ++ if (mode) { ++ crtc->mode = *mode; ++ crtc->x = x; ++ crtc->y = y; ++ crtc->rotation = rotation; ++ } + + output_ids = xcalloc(sizeof(uint32_t), xf86_config->num_output); + if (!output_ids) { @@ -857,35 +1112,42 @@ index 0000000..7ac30f8 + goto done; + } + -+ for (i = 0; i < xf86_config->num_output; i++) { -+ xf86OutputPtr output = xf86_config->output[i]; -+ drmmode_output_private_ptr drmmode_output; ++ if (mode) { ++ for (i = 0; i < xf86_config->num_output; i++) { ++ xf86OutputPtr output = xf86_config->output[i]; ++ drmmode_output_private_ptr drmmode_output; + -+ if (output->crtc != crtc) -+ continue; ++ if (output->crtc != crtc) ++ continue; + -+ drmmode_output = output->driver_private; -+ output_ids[output_count] = drmmode_output->mode_output->connector_id; -+ output_count++; -+ } ++ drmmode_output = output->driver_private; ++ output_ids[output_count] = drmmode_output->mode_output->connector_id; ++ output_count++; ++ } + -+ if (!xf86CrtcRotate(crtc, mode, rotation)) { -+ goto done; -+ } ++ if (!xf86CrtcRotate(crtc, mode, rotation)) { ++ goto done; ++ } + -+ drmmode_ConvertToKMode(crtc->scrn, &kmode, mode); ++ drmmode_ConvertToKMode(crtc->scrn, &kmode, mode); ++ ++ fb_id = drmmode->fb_id; ++ if (drmmode_crtc->rotate_fb_id) { ++ fb_id = drmmode_crtc->rotate_fb_id; ++ x = y = 0; ++ } ++ else if (fb_id != drmmode_crtc->mode_crtc->buffer_id) ++ copy_fb_contents (drmmode, crtc->scrn, fb_id, x, y, ++ drmmode_crtc->mode_crtc->buffer_id); + ++ drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, ++ fb_id, x, y, output_ids, output_count, &kmode); + -+ fb_id = drmmode->fb_id; -+ if (drmmode_crtc->rotate_fb_id) -+ fb_id = drmmode_crtc->rotate_fb_id; -+ copy_fb_contents (drmmode, crtc->scrn, fb_id, x, y, -+ drmmode_crtc->mode_crtc->buffer_id); -+ drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, -+ fb_id, x, y, output_ids, output_count, &kmode); ++ if (crtc->scrn->pScreen) ++ xf86CrtcSetScreenSubpixelOrder(crtc->scrn->pScreen); ++ } ++ + -+ if (crtc->scrn->pScreen) -+ xf86CrtcSetScreenSubpixelOrder(crtc->scrn->pScreen); + + +done: @@ -1147,6 +1409,12 @@ index 0000000..7ac30f8 +static void +drmmode_output_dpms(xf86OutputPtr output, int mode) +{ ++ drmmode_output_private_ptr drmmode_output = output->driver_private; ++ drmModeConnectorPtr koutput = drmmode_output->mode_output; ++ drmmode_ptr drmmode = drmmode_output->drmmode; ++ ++ drmModeConnectorSetProperty(drmmode->fd, koutput->connector_id, ++ drmmode_output->dpms_enum_id, mode); + return; +} + @@ -1198,7 +1466,9 @@ index 0000000..7ac30f8 + drmModeConnectorPtr koutput; + drmModeEncoderPtr kencoder; + drmmode_output_private_ptr drmmode_output; ++ drmModePropertyPtr props; + char name[32]; ++ int i; + + koutput = drmModeGetConnector(drmmode->fd, drmmode->mode_res->connectors[num]); + if (!koutput) @@ -1257,6 +1527,18 @@ index 0000000..7ac30f8 + output->possible_crtcs = kencoder->possible_crtcs; + output->possible_clones = kencoder->possible_clones; + ++ for (i = 0; i < koutput->count_props; i++) { ++ props = drmModeGetProperty(drmmode->fd, koutput->props[i]); ++ if (props && (props->flags && DRM_MODE_PROP_ENUM)) { ++ if (!strcmp(props->name, "DPMS")) { ++ drmmode_output->dpms_enum_id = koutput->props[i]; ++ drmModeFreeProperty(props); ++ break; ++ } ++ drmModeFreeProperty(props); ++ } ++ } ++ + return; +} + @@ -1405,13 +1687,66 @@ index 0000000..7ac30f8 + } +} + ++Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode) ++{ ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); ++ int c, o; ++ ++ for (c = 0; c < config->num_crtc; c++) { ++ xf86CrtcPtr crtc = config->crtc[c]; ++ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; ++ xf86OutputPtr output = NULL; ++ int o; ++ ++ /* Skip disabled CRTCs */ ++ if (!crtc->enabled) { ++ drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, ++ 0, 0, 0, NULL, 0, NULL); ++ continue; ++ } ++ ++ if (config->output[config->compat_output]->crtc == crtc) ++ output = config->output[config->compat_output]; ++ else ++ { ++ for (o = 0; o < config->num_output; o++) ++ if (config->output[o]->crtc == crtc) ++ { ++ output = config->output[o]; ++ break; ++ } ++ } ++ /* paranoia */ ++ if (!output) ++ continue; ++ ++ /* Mark that we'll need to re-set the mode for sure */ ++ memset(&crtc->mode, 0, sizeof(crtc->mode)); ++ if (!crtc->desiredMode.CrtcHDisplay) ++ { ++ DisplayModePtr mode = xf86OutputFindClosestMode (output, pScrn->currentMode); ++ ++ if (!mode) ++ return FALSE; ++ crtc->desiredMode = *mode; ++ crtc->desiredRotation = RR_Rotate_0; ++ crtc->desiredX = 0; ++ crtc->desiredY = 0; ++ } ++ ++ if (!crtc->funcs->set_mode_major(crtc, &crtc->desiredMode, crtc->desiredRotation, ++ crtc->desiredX, crtc->desiredY)) ++ return FALSE; ++ } ++ return TRUE; ++} +#endif diff --git a/src/drmmode_display.h b/src/drmmode_display.h new file mode 100644 -index 0000000..691d62e +index 0000000..dbb6412 --- /dev/null +++ b/src/drmmode_display.h -@@ -0,0 +1,74 @@ +@@ -0,0 +1,76 @@ +/* + * Copyright © 2007 Red Hat, Inc. + * @@ -1475,6 +1810,7 @@ index 0000000..691d62e + drmModeConnectorPtr mode_output; + drmModeEncoderPtr mode_encoder; + drmModePropertyBlobPtr edid_blob; ++ int dpms_enum_id; +} drmmode_output_private_rec, *drmmode_output_private_ptr; + + @@ -1484,10 +1820,11 @@ index 0000000..691d62e +extern Bool drmmode_is_rotate_pixmap(ScrnInfoPtr pScrn, pointer pPixData, dri_bo **bo); +extern void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id, void *ptr, uint32_t handle); +void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y, int flags); ++extern Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode); +#endif +#endif diff --git a/src/radeon.h b/src/radeon.h -index f7ae1a8..a437b55 100644 +index a67962c..370dbf1 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -46,6 +46,8 @@ @@ -1507,7 +1844,7 @@ index f7ae1a8..a437b55 100644 /* Render support */ #ifdef RENDER #include "picturestr.h" -@@ -404,6 +407,14 @@ typedef enum { +@@ -409,6 +412,14 @@ typedef enum { typedef struct _atomBiosHandle *atomBiosHandlePtr; @@ -1522,7 +1859,7 @@ index f7ae1a8..a437b55 100644 typedef struct { uint32_t pci_device_id; RADEONChipFamily chip_family; -@@ -414,7 +425,27 @@ typedef struct { +@@ -419,7 +430,27 @@ typedef struct { int singledac; } RADEONCardInfo; @@ -1550,7 +1887,7 @@ index f7ae1a8..a437b55 100644 struct radeon_cp { Bool CPRuns; /* CP is running */ Bool CPInUse; /* CP has been used by X server */ -@@ -428,6 +459,10 @@ struct radeon_cp { +@@ -433,6 +464,10 @@ struct radeon_cp { drmBufPtr indirectBuffer; int indirectStart; @@ -1561,7 +1898,7 @@ index f7ae1a8..a437b55 100644 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ int dma_begin_count; char *dma_debug_func; -@@ -494,13 +529,13 @@ struct radeon_dri { +@@ -499,13 +534,13 @@ struct radeon_dri { drm_handle_t ringHandle; /* Handle from drmAddMap */ drmSize ringMapSize; /* Size of map */ int ringSize; /* Size of ring (in MB) */ @@ -1577,7 +1914,7 @@ index f7ae1a8..a437b55 100644 /* CP vertex/indirect buffer data */ unsigned long bufStart; /* Offset into GART space */ -@@ -519,7 +554,6 @@ struct radeon_dri { +@@ -524,7 +559,6 @@ struct radeon_dri { drmAddress gartTex; /* Map */ int log2GARTTexGran; @@ -1585,9 +1922,9 @@ index f7ae1a8..a437b55 100644 int fbX; int fbY; int backX; -@@ -836,6 +870,44 @@ typedef struct { - Bool r600_shadow_fb; - void *fb_shadow; +@@ -846,6 +880,44 @@ typedef struct { + /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ + Bool get_hardcoded_edid_from_bios; + Bool new_cs; // new command submission routine + struct radeon_2d_state state_2d; @@ -1630,7 +1967,7 @@ index f7ae1a8..a437b55 100644 } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -1078,6 +1150,23 @@ extern void +@@ -1092,6 +1164,23 @@ extern void radeon_legacy_free_memory(ScrnInfoPtr pScrn, void *mem_struct); @@ -1654,7 +1991,7 @@ index f7ae1a8..a437b55 100644 #ifdef XF86DRI # ifdef USE_XAA /* radeon_accelfuncs.c */ -@@ -1096,7 +1185,9 @@ do { \ +@@ -1110,7 +1199,9 @@ do { \ #define RADEONCP_RELEASE(pScrn, info) \ do { \ @@ -1665,7 +2002,7 @@ index f7ae1a8..a437b55 100644 RADEON_PURGE_CACHE(); \ RADEON_WAIT_UNTIL_IDLE(); \ RADEONCPReleaseIndirect(pScrn); \ -@@ -1130,7 +1221,7 @@ do { \ +@@ -1144,7 +1235,7 @@ do { \ #define RADEONCP_REFRESH(pScrn, info) \ do { \ @@ -1674,7 +2011,7 @@ index f7ae1a8..a437b55 100644 if (info->cp->needCacheFlush) { \ RADEON_PURGE_CACHE(); \ RADEON_PURGE_ZCACHE(); \ -@@ -1157,6 +1248,13 @@ do { \ +@@ -1171,6 +1262,13 @@ do { \ #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 #define BEGIN_RING(n) do { \ @@ -1688,7 +2025,7 @@ index f7ae1a8..a437b55 100644 if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ -@@ -1169,13 +1267,6 @@ do { \ +@@ -1183,13 +1281,6 @@ do { \ } \ info->cp->dma_debug_func = __FILE__; \ info->cp->dma_debug_lineno = __LINE__; \ @@ -1702,7 +2039,7 @@ index f7ae1a8..a437b55 100644 __expected = n; \ __head = (pointer)((char *)info->cp->indirectBuffer->address + \ info->cp->indirectBuffer->used); \ -@@ -1218,6 +1309,14 @@ do { \ +@@ -1232,6 +1323,14 @@ do { \ OUT_RING(val); \ } while (0) @@ -1718,10 +2055,18 @@ index f7ae1a8..a437b55 100644 do { \ if (RADEON_VERBOSE) \ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index a6e332d..d7c70c5 100644 +index 2f62fa5..fd1e073 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c -@@ -311,6 +311,9 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) +@@ -91,6 +91,7 @@ + + /* X and server generic header files */ + #include "xf86.h" ++#include "radeon_bufmgr_gem.h" + + + #ifdef USE_XAA +@@ -316,6 +317,9 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -1731,7 +2076,7 @@ index a6e332d..d7c70c5 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "EngineRestore (%d/%d)\n", info->CurrentLayout.pixel_code, -@@ -370,8 +373,8 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -375,8 +379,8 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->CurrentLayout.bitsPerPixel); #ifdef XF86DRI @@ -1742,7 +2087,7 @@ index a6e332d..d7c70c5 100644 int num_pipes; memset(&np, 0, sizeof(np)); -@@ -390,59 +393,62 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -395,59 +399,62 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) } #endif @@ -1854,7 +2199,7 @@ index a6e332d..d7c70c5 100644 switch (info->CurrentLayout.pixel_code) { case 8: datatype = 2; break; -@@ -550,6 +556,148 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) +@@ -555,6 +562,115 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) } } @@ -1865,12 +2210,21 @@ index a6e332d..d7c70c5 100644 + + info->cp->relocs.size = getpagesize(); + info->cp->relocs.num_reloc = 0; ++ info->cp->relocs.max_bo = info->cp->relocs.size / RADEON_RELOC_SIZE; + info->cp->relocs.buf = xcalloc(1, info->cp->relocs.size); + if (!info->cp->relocs.buf) + return NULL; ++ ++ info->cp->relocs.bo_list = xcalloc(info->cp->relocs.max_bo, sizeof(dri_bo *)); ++ if (!info->cp->relocs.bo_list) { ++ xfree(info->cp->relocs.buf); ++ return NULL; ++ } ++ + info->cp->ib_gem_fake.address = xcalloc(1, RADEON_BUFFER_SIZE); + if (!info->cp->ib_gem_fake.address) { + xfree(info->cp->relocs.buf); ++ xfree(info->cp->relocs.bo_list); + return NULL; + } + @@ -1880,13 +2234,13 @@ index a6e332d..d7c70c5 100644 + return &info->cp->ib_gem_fake; +} + -+#ifdef DRM_RADEON_CS2 +void RADEONCSFlushIndirect(ScrnInfoPtr pScrn, int discard) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct drm_radeon_cs2 args; ++ struct drm_radeon_cs args; + struct drm_radeon_cs_chunk chunk[2]; + uint64_t chunk_array[2]; ++ int retry = 0; + int ret; + RING_LOCALS; + @@ -1916,12 +2270,14 @@ index a6e332d..d7c70c5 100644 + args.num_chunks = 2; + args.chunks = (uint64_t)(unsigned long)chunk_array; + -+ ret = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_CS2, -+ &args, sizeof(args)); -+ ++ do { ++ ret = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_CS, ++ &args, sizeof(args)); ++ retry++; ++ } while (ret == -EAGAIN && retry < 1000); + if (ret) { -+ FatalError("DRM Command submission failure %d\n", ret); -+ return; ++ /* submit failed */ ++ ErrorF("RADEON DRM CS failure - corruptions/glitches may occur %d\n", ret); + } + + @@ -1930,7 +2286,7 @@ index a6e332d..d7c70c5 100644 + info->cp->indirectBuffer->total -= RADEON_IB_RESERVE; + + if (info->bufmgr) -+ radeon_gem_bufmgr_post_submit(info->bufmgr, &info->cp->relocs); ++ radeon_gem_bufmgr_post_submit(info->bufmgr, &info->cp->relocs, ret); + + info->cp->relocs.num_reloc = 0; + /* copy some state into the buffer now - we need to add 2D state to each @@ -1938,51 +2294,6 @@ index a6e332d..d7c70c5 100644 + if (info->reemit_current2d) + info->reemit_current2d(pScrn, 0); +} -+#else -+void RADEONCSFlushIndirect(ScrnInfoPtr pScrn, int discard) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct drm_radeon_cs args; -+ int ret; -+ RING_LOCALS; -+ -+ /* always add the cache flushes to the end of the IB */ -+ info->cp->indirectBuffer->total += RADEON_IB_RESERVE; -+ -+ /* end of IB purge caches */ -+ if (info->cs_used_depth) { -+ RADEON_PURGE_ZCACHE(); -+ info->cs_used_depth = 0; -+ } -+ -+ RADEON_PURGE_CACHE(); -+ RADEON_WAIT_UNTIL_IDLE(); -+ -+ args.packets = (unsigned long)info->cp->ib_gem_fake.address; -+ args.dwords = info->cp->indirectBuffer->used / sizeof(uint32_t); -+ -+ ret = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_CS, -+ &args, sizeof(args)); -+ -+ if (ret) { -+ FatalError("DRM Command submission failure %d\n", ret); -+ return; -+ } -+ -+ -+ info->cp->indirectStart = 0; -+ info->cp->indirectBuffer->used = 0; -+ info->cp->indirectBuffer->total -= RADEON_IB_RESERVE; -+ -+ if (info->bufmgr) -+ radeon_gem_bufmgr_post_submit(info->bufmgr); -+ -+ /* copy some state into the buffer now - we need to add 2D state to each -+ buffer as the kernel needs to use the blit engine to move stuff around */ -+ if (info->reemit_current2d) -+ info->reemit_current2d(pScrn, 0); -+} -+#endif + +void RADEONCSReleaseIndirect(ScrnInfoPtr pScrn) +{ @@ -1991,6 +2302,7 @@ index a6e332d..d7c70c5 100644 + if (!info->cp->indirectBuffer) return; + RADEONCSFlushIndirect(pScrn, 0); + xfree(info->cp->relocs.buf); ++ xfree(info->cp->relocs.bo_list); + info->cp->relocs.buf = 0; + info->cp->relocs.size = 0; + info->cp->relocs.num_reloc = 0; @@ -2003,7 +2315,7 @@ index a6e332d..d7c70c5 100644 /* Get an indirect buffer for the CP 2D acceleration commands */ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) { -@@ -560,6 +708,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -565,6 +681,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) int size = 0; int i = 0; int ret; @@ -2013,7 +2325,7 @@ index a6e332d..d7c70c5 100644 #if 0 /* FIXME: pScrn->pScreen has not been initialized when this is first -@@ -625,6 +776,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -630,6 +749,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) if (!buffer) return; if (start == buffer->used && !discard) return; @@ -2025,7 +2337,7 @@ index a6e332d..d7c70c5 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", buffer->idx); -@@ -659,10 +815,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -664,10 +788,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) int start = info->cp->indirectStart; drm_radeon_indirect_t indirect; @@ -2042,7 +2354,7 @@ index a6e332d..d7c70c5 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n", -@@ -789,6 +951,7 @@ RADEONHostDataBlit( +@@ -794,6 +924,7 @@ RADEONHostDataBlit( ret = ( uint8_t* )&__head[__count]; __count += dwords; @@ -2050,7 +2362,7 @@ index a6e332d..d7c70c5 100644 ADVANCE_RING(); *y += *hpass; -@@ -926,7 +1089,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -931,7 +1062,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) #ifdef USE_EXA if (info->useEXA) { # ifdef XF86DRI @@ -2059,7 +2371,7 @@ index a6e332d..d7c70c5 100644 if (!RADEONDrawInitCP(pScreen)) return FALSE; } else -@@ -947,7 +1110,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -952,7 +1083,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) } #ifdef XF86DRI @@ -2068,7 +2380,7 @@ index a6e332d..d7c70c5 100644 RADEONAccelInitCP(pScreen, a); else #endif /* XF86DRI */ -@@ -969,11 +1132,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -974,11 +1105,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR (pScrn); #ifdef XF86DRI @@ -2086,7 +2398,7 @@ index a6e332d..d7c70c5 100644 RADEONInit3DEngineCP(pScrn); } else #endif -@@ -981,7 +1146,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -986,7 +1119,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) info->accel_state->XInited3D = TRUE; } @@ -2097,10 +2409,10 @@ index a6e332d..d7c70c5 100644 Bool diff --git a/src/radeon_bufmgr.h b/src/radeon_bufmgr.h new file mode 100644 -index 0000000..5d45aa5 +index 0000000..481c5cf --- /dev/null +++ b/src/radeon_bufmgr.h -@@ -0,0 +1,28 @@ +@@ -0,0 +1,25 @@ +/** + * @file intel_bufmgr.h + * @@ -2124,17 +2436,14 @@ index 0000000..5d45aa5 + +void radeon_bufmgr_emit_reloc(dri_bo *buf, struct radeon_relocs_info *relocs, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); + -+dri_bufmgr *radeon_bufmgr_exa_init(ScrnInfoPtr pScrn); -+extern void radeon_bufmgr_exa_wait_rendering(dri_bo *bo); -+extern dri_bo *radeon_bufmgr_exa_create_bo(dri_bufmgr *bufmgr, struct radeon_memory *mem); +void radeon_bufmgr_post_submit(dri_bufmgr *bufmgr); +#endif -diff --git a/src/radeon_bufmgr_exa.c b/src/radeon_bufmgr_exa.c +diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c new file mode 100644 -index 0000000..0f493a5 +index 0000000..7508dd7 --- /dev/null -+++ b/src/radeon_bufmgr_exa.c -@@ -0,0 +1,328 @@ ++++ b/src/radeon_bufmgr_gem.c +@@ -0,0 +1,656 @@ +/************************************************************************** + * + * Copyright © 2007-2008 Red Hat Inc. @@ -2181,6 +2490,8 @@ index 0000000..0f493a5 +#include +#include +#include ++#include ++#include + +#include "xf86.h" +#include "errno.h" @@ -2192,407 +2503,51 @@ index 0000000..0f493a5 +#include "radeon_bufmgr.h" +#include "radeon_drm.h" + ++#define DBG(...) do { \ ++ if (bufmgr_gem->bufmgr.debug) \ ++ fprintf(stderr, __VA_ARGS__); \ ++} while (0) + -+typedef struct _dri_bo_exa { ++typedef struct _dri_bo_gem { + dri_bo bo; -+ struct radeon_memory *mem; + int refcount; + int reloc_count; + int map_count; + /* reloc list - add to list for relocs */ -+ struct _dri_bo_exa *next; -+} dri_bo_exa; ++ uint32_t gem_handle; ++ const char *name; ++ struct _dri_bo_gem *next; ++ int in_vram; /* have we migrated this bo to VRAM ever */ ++ int force_gtt; ++ int pinned; ++ int touched; ++ uint32_t space_accounted; ++} dri_bo_gem; + -+typedef struct _dri_bufmgr_exa { ++typedef struct _dri_bufmgr_gem { + dri_bufmgr bufmgr; + struct radeon_bufmgr radeon_bufmgr; -+ ScrnInfoPtr pScrn; -+ struct _dri_bo_exa *reloc_head; -+} dri_bufmgr_exa; ++ int fd; ++ uint32_t vram_limit, gart_limit; ++ uint32_t vram_write_used, gart_write_used; ++ uint32_t read_used; ++ ++ struct _dri_bo_gem *bo_list; ++} dri_bufmgr_gem; + +static dri_bo * -+dri_exa_alloc(dri_bufmgr *bufmgr, const char *name, -+ unsigned long size, unsigned int alignment, uint64_t location_mask) ++dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name, ++ unsigned long size, unsigned int alignment, uint64_t location_mask) + +{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)bufmgr; -+ RADEONInfoPtr info = RADEONPTR(bufmgr_exa->pScrn); -+ dri_bo_exa *exa_buf; ++ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr; ++ struct drm_radeon_gem_create args; ++ int ret; ++ unsigned int page_size = getpagesize(); ++ dri_bo_gem *gem_bo; + -+ exa_buf = malloc(sizeof(*exa_buf)); -+ if (!exa_buf) -+ return NULL; -+ -+ exa_buf->refcount = 1; -+ exa_buf->mem = radeon_allocate_memory(bufmgr_exa->pScrn, RADEON_POOL_GART, -+ size, alignment, 0, name, 0); -+ -+ exa_buf->bo.size = exa_buf->mem->size; -+ exa_buf->bo.offset = exa_buf->mem->offset; -+ exa_buf->bo.bufmgr = bufmgr; -+ exa_buf->next = NULL; -+ exa_buf->reloc_count = 0; -+ exa_buf->map_count = 0; -+ -+ return &exa_buf->bo; -+} -+ -+static void -+dri_exa_bo_reference(dri_bo *buf) -+{ -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ exa_buf->refcount++; -+} -+ -+static void -+dri_exa_bo_unreference(dri_bo *buf) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ -+ if (!buf) -+ return; -+ -+ if (--exa_buf->refcount == 0) -+ radeon_free_memory(bufmgr_exa->pScrn, exa_buf->mem); -+} -+ -+static int -+dri_exa_bo_map(dri_bo *buf, int write_enable) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ -+ if (exa_buf->map_count++ != 0) -+ return 0; -+ -+ radeon_map_memory(bufmgr_exa->pScrn, exa_buf->mem); -+ exa_buf->bo.virtual = exa_buf->mem->map; -+ return 0; -+} -+ -+static int -+dri_exa_bo_unmap(dri_bo *buf) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ -+ if (--exa_buf->map_count > 0) -+ return 0; -+ -+ radeon_unmap_memory(bufmgr_exa->pScrn, exa_buf->mem); -+ exa_buf->bo.virtual = 0; -+ return 0; -+} -+ -+static void -+dri_bufmgr_exa_destroy(dri_bufmgr *bufmgr) -+{ -+ free(bufmgr); -+} -+ -+void radeon_bufmgr_exa_wait_rendering(dri_bo *buf) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ RADEONInfoPtr info = RADEONPTR(bufmgr_exa->pScrn); -+ struct drm_radeon_gem_set_domain dom_args; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ int ret; -+ -+ dom_args.handle = exa_buf->mem->kernel_bo_handle; -+ dom_args.read_domains = RADEON_GEM_DOMAIN_GTT; -+ dom_args.write_domain = 0; -+ ret = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_SET_DOMAIN, -+ &dom_args, sizeof(dom_args)); -+ -+ return; -+} -+ -+int radeon_bufmgr_subdata(dri_bo *buf, unsigned long offset, -+ unsigned long size, const void *data) -+{ -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ RADEONInfoPtr info = RADEONPTR(bufmgr_exa->pScrn); -+ int ret; -+ /* go to pwrite */ -+ struct drm_radeon_gem_pwrite pwrite; -+ -+ pwrite.handle = exa_buf->mem->kernel_bo_handle; -+ pwrite.offset = offset; -+ pwrite.size = size; -+ pwrite.data_ptr = (uint64_t)(uintptr_t)data; -+ -+ do { -+ ret = drmCommandWriteRead(info->dri->drmFD, DRM_IOCTL_RADEON_GEM_PWRITE, -+ &pwrite, sizeof(pwrite)); -+ } while (ret == -1 && errno == EINTR); -+ -+ if (ret != 0) { -+ fprintf(stderr,"Pwrite %lx at %lx failed\n", size, offset); -+ return -1; -+ } -+ return 0; -+} -+ -+ -+dri_bo * -+radeon_bufmgr_exa_create_bo(dri_bufmgr *bufmgr, struct radeon_memory *mem) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)bufmgr; -+ dri_bo_exa *exa_buf; -+ -+ exa_buf = malloc(sizeof(*exa_buf)); -+ if (!exa_buf) -+ return NULL; -+ exa_buf->refcount = 1; -+ exa_buf->mem = mem; -+ exa_buf->bo.size = exa_buf->mem->size; -+ exa_buf->bo.offset = exa_buf->mem->offset; -+ exa_buf->bo.bufmgr = bufmgr; -+ exa_buf->bo.virtual = exa_buf->mem->map; -+ exa_buf->next = NULL; -+ exa_buf->reloc_count = 0; -+ /* get map count right */ -+ exa_buf->map_count = 1; -+ -+ return &exa_buf->bo; -+} -+ -+static void radeon_bufmgr_exa_emit_reloc(dri_bo *buf, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ ScrnInfoPtr pScrn = bufmgr_exa->pScrn; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ uint32_t *__head = head; -+ uint32_t __count = *count_p; -+ dri_bo_exa *trav; -+ -+ if (exa_buf->reloc_count == 0) { -+ dri_bo_reference(buf); -+ -+ if (bufmgr_exa->reloc_head == NULL) -+ bufmgr_exa->reloc_head = exa_buf; -+ else { -+ trav = bufmgr_exa->reloc_head; -+ while (trav->next != NULL) -+ trav = trav->next; -+ trav->next = exa_buf; -+ } -+ } -+ exa_buf->reloc_count++; -+ OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 2)); -+ OUT_RING(exa_buf->mem->kernel_bo_handle); -+ OUT_RING(read_domains); -+ OUT_RING(write_domain); -+ *count_p = __count; -+} -+ -+static int radeon_bufmgr_exa_pin(dri_bo *buf) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ -+ return !radeon_bind_memory(bufmgr_exa->pScrn, exa_buf->mem); -+} -+ -+static void radeon_bufmgr_exa_unpin(dri_bo *buf) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)buf->bufmgr; -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ -+ radeon_unbind_memory(bufmgr_exa->pScrn, exa_buf->mem); -+} -+ -+static uint32_t radeon_bufmgr_get_handle(dri_bo *buf) -+{ -+ dri_bo_exa *exa_buf = (dri_bo_exa *)buf; -+ -+ return exa_buf->mem->kernel_bo_handle; -+} -+ -+ -+/** -+ * Initializes the EXA buffer manager, which is just a thin wrapper -+ * around the EXA allocator. -+ * -+ * \param fd File descriptor of the opened DRM device. -+ * \param fence_type Driver-specific fence type used for fences with no flush. -+ * \param fence_type_flush Driver-specific fence type used for fences with a -+ * flush. -+ */ -+dri_bufmgr * -+radeon_bufmgr_exa_init(ScrnInfoPtr pScrn) -+{ -+ dri_bufmgr_exa *bufmgr_exa; -+ -+ bufmgr_exa = calloc(1, sizeof(*bufmgr_exa)); -+ bufmgr_exa->pScrn = pScrn; -+ -+ bufmgr_exa->bufmgr.bo_alloc = dri_exa_alloc; -+ bufmgr_exa->bufmgr.bo_reference = dri_exa_bo_reference; -+ bufmgr_exa->bufmgr.bo_unreference = dri_exa_bo_unreference; -+ bufmgr_exa->bufmgr.bo_map = dri_exa_bo_map; -+ bufmgr_exa->bufmgr.bo_unmap = dri_exa_bo_unmap; -+ bufmgr_exa->bufmgr.destroy = dri_bufmgr_exa_destroy; -+ //bufmgr_exa->bufmgr.bo_wait_rendering = radeon_bufmgr_exa_wait_rendering; -+ bufmgr_exa->radeon_bufmgr.emit_reloc = radeon_bufmgr_exa_emit_reloc; -+ bufmgr_exa->bufmgr.pin = radeon_bufmgr_exa_pin; -+ bufmgr_exa->bufmgr.unpin = radeon_bufmgr_exa_unpin; -+ bufmgr_exa->bufmgr.get_handle = radeon_bufmgr_get_handle; -+ return &bufmgr_exa->bufmgr; -+} -+ -+void radeon_bufmgr_post_submit(dri_bufmgr *bufmgr) -+{ -+ dri_bufmgr_exa *bufmgr_exa = (dri_bufmgr_exa *)bufmgr; -+ struct _dri_bo_exa *trav, *prev; -+ -+ if (!bufmgr_exa->reloc_head) -+ return; -+ -+ trav = bufmgr_exa->reloc_head; -+ while (trav) { -+ prev = trav; -+ trav = trav->next; -+ -+ prev->reloc_count = 0; -+ prev->next = NULL; -+ dri_bo_unreference(&prev->bo); -+ } -+ bufmgr_exa->reloc_head = NULL; -+ -+} -diff --git a/src/radeon_bufmgr_exa.h b/src/radeon_bufmgr_exa.h -new file mode 100644 -index 0000000..0d79b58 ---- /dev/null -+++ b/src/radeon_bufmgr_exa.h -@@ -0,0 +1,14 @@ -+#ifndef RADEON_BUFMGR_EXA_H -+#define RADEON_BUFMGR_EXA_H -+ -+#include "radeon_dri_bufmgr.h" -+ -+dri_bufmgr *radeon_bufmgr_exa_init(ScrnInfoPtr pScrn); -+extern void radeon_bufmgr_exa_wait_rendering(dri_bo *bo); -+extern dri_bo *radeon_bufmgr_exa_create_bo(dri_bufmgr *bufmgr, struct radeon_memory *mem); -+void radeon_bufmgr_exa_emit_reloc(dri_bo *bo, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); -+void radeon_bufmgr_post_submit(dri_bufmgr *bufmgr); -+void radeon_bufmgr_pin(dri_bo *buf); -+void radeon_bufmgr_unpin(dri_bo *buf); -+uint32_t radeon_bufmgr_get_handle(dri_bo *buf); -+#endif -diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c -new file mode 100644 -index 0000000..7a41852 ---- /dev/null -+++ b/src/radeon_bufmgr_gem.c -@@ -0,0 +1,538 @@ -+/************************************************************************** -+ * -+ * Copyright © 2007-2008 Red Hat Inc. -+ * Copyright © 2007 Intel Corporation -+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA -+ * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the -+ * "Software"), to deal in the Software without restriction, including -+ * without limitation the rights to use, copy, modify, merge, publish, -+ * distribute, sub license, and/or sell copies of the Software, and to -+ * permit persons to whom the Software is furnished to do so, subject to -+ * the following conditions: -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, -+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -+ * USE OR OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * The above copyright notice and this permission notice (including the -+ * next paragraph) shall be included in all copies or substantial portions -+ * of the Software. -+ * -+ * -+ **************************************************************************/ -+/* -+ * Authors: Thomas Hellström -+ * Keith Whitwell -+ * Eric Anholt -+ * Dave Airlie -+ * Kristian Høgsberg -+ */ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "xf86.h" -+#include "errno.h" -+#include "string.h" -+ -+#include "radeon_reg.h" -+#include "radeon_probe.h" -+#include "radeon.h" -+#include "radeon_bufmgr.h" -+#include "radeon_drm.h" -+ -+#define DBG(...) do { \ -+ if (bufmgr_gem->bufmgr.debug) \ -+ fprintf(stderr, __VA_ARGS__); \ -+} while (0) -+ -+typedef struct _dri_bo_gem { -+ dri_bo bo; -+ int refcount; -+ int reloc_count; -+ int map_count; -+ /* reloc list - add to list for relocs */ -+ uint32_t gem_handle; -+ const char *name; -+ struct _dri_bo_gem *next; -+ int in_vram; /* have we migrated this bo to VRAM ever */ -+ int pinned; -+ int touched; -+ int space_accounted; -+ -+} dri_bo_gem; -+ -+typedef struct _dri_bufmgr_gem { -+ dri_bufmgr bufmgr; -+ struct radeon_bufmgr radeon_bufmgr; -+ int fd; -+ uint32_t vram_limit; -+ uint32_t vram_write_used, gart_write_used; -+ uint32_t read_used; -+ -+ struct _dri_bo_gem *bo_list; -+} dri_bufmgr_gem; -+ -+static dri_bo * -+dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name, -+ unsigned long size, unsigned int alignment, uint64_t location_mask) -+ -+{ -+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr; -+ struct drm_radeon_gem_create args; -+ int ret; -+ unsigned int page_size = getpagesize(); -+ dri_bo_gem *gem_bo; -+ -+ gem_bo = calloc(1, sizeof(*gem_bo)); -+ if (!gem_bo) ++ gem_bo = calloc(1, sizeof(*gem_bo)); ++ if (!gem_bo) + return NULL; + + gem_bo->bo.size = size; @@ -2691,7 +2646,6 @@ index 0000000..7a41852 + if (gem_bo->map_count++ != 0) + return 0; + -+ /*gem_bo->touched = 1; workaround */ + args.handle = gem_bo->gem_handle; + args.offset = 0; + args.size = gem_bo->bo.size; @@ -2730,15 +2684,30 @@ index 0000000..7a41852 +{ + dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)buf->bufmgr; + struct drm_radeon_gem_wait_rendering args; ++ struct drm_radeon_gem_set_domain sd_args; + dri_bo_gem *gem_bo = (dri_bo_gem *)buf; + int ret; + -+ args.handle = gem_bo->gem_handle; ++ if (!gem_bo->touched) ++ return; + -+ do { -+ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_WAIT_RENDERING, -+ &args, sizeof(args)); -+ } while (ret == -EAGAIN); ++ /* do a set domain */ ++ if (gem_bo->force_gtt) { ++ sd_args.handle = gem_bo->gem_handle; ++ sd_args.read_domains = RADEON_GEM_DOMAIN_GTT; ++ sd_args.write_domain = 0; ++ ++ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_SET_DOMAIN, ++ &sd_args, sizeof(sd_args)); ++ ++ } else { ++ args.handle = gem_bo->gem_handle; ++ ++ do { ++ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_WAIT_RENDERING, ++ &args, sizeof(args)); ++ } while (ret == -EAGAIN); ++ } + return; +} + @@ -2763,6 +2732,9 @@ index 0000000..7a41852 + bo_gem->refcount = 1; + bo_gem->pinned = 1; + bo_gem->gem_handle = handle; ++ bo_gem->in_vram = 1; ++ /* if we get from kernel assume touched */ ++ bo_gem->touched = 1; + + bo_gem->next = bufmgr_gem->bo_list; + bufmgr_gem->bo_list = bo_gem; @@ -2818,6 +2790,9 @@ index 0000000..7a41852 + } + } + ++ if (gem_bo->force_gtt && (read_domains & RADEON_GEM_DOMAIN_VRAM)) ++ read_domains = RADEON_GEM_DOMAIN_GTT; ++ + if (have_reloc != -1) { + uint32_t old_write, old_read; + @@ -2848,12 +2823,15 @@ index 0000000..7a41852 + reloc_info->buf = xrealloc(reloc_info->buf, reloc_info->size); + if (!reloc_info->buf) + FatalError("failed to increase reloc buffer size\n"); ++ reloc_info->max_bo = reloc_info->size / RADEON_RELOC_SIZE; ++ reloc_info->bo_list = xrealloc(reloc_info->bo_list, reloc_info->max_bo * (sizeof(dri_bo *))); + } + + dri_bo_reference(buf); + gem_bo->touched = 1; + + index = reloc_info->num_reloc * 4; ++ reloc_info->bo_list[index/4] = buf; + reloc_info->buf[index] = gem_bo->gem_handle; + reloc_info->buf[index + 1] = read_domains; + reloc_info->buf[index + 2] = write_domain; @@ -2881,6 +2859,9 @@ index 0000000..7a41852 + struct drm_radeon_gem_pin pin; + int ret; + ++ if (domain == RADEON_GEM_DOMAIN_VRAM) ++ gem_bo->in_vram = 1; ++ + pin.pin_domain = domain; + pin.handle = gem_bo->gem_handle; + pin.alignment = 0; @@ -2889,6 +2870,8 @@ index 0000000..7a41852 + if (ret != 0) + return -1; + ++ /* pinned buffers are considered touched */ ++ gem_bo->touched = 1; + gem_bo->pinned = 1; + return 0; +} @@ -2913,31 +2896,103 @@ index 0000000..7a41852 + return gem_bo->gem_handle; +} + -+static int radeon_gem_bufmgr_check_aperture_space(dri_bo *buf, uint32_t read_domains, uint32_t write_domain) ++static int radeon_gem_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo) +{ -+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)buf->bufmgr; -+ dri_bo_gem *gem_bo = (dri_bo_gem *)buf; ++ dri_bufmgr_gem *bufmgr_gem; ++ dri_bo_gem *gem_bo; ++ dri_bo *buf; ++ int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0; ++ uint32_t read_domains, write_domain; ++ int i; ++ /* check the totals for this operation */ + -+ if (gem_bo->pinned) ++ if (num_bo == 0) + return 0; + -+ if (gem_bo->space_accounted == 1) -+ return 0; ++ bufmgr_gem = (dri_bufmgr_gem *)bos[0].buf->bufmgr; + -+ if (write_domain == RADEON_GEM_DOMAIN_VRAM) { -+ bufmgr_gem->vram_write_used += buf->size; -+ } else { -+ bufmgr_gem->read_used += buf->size; ++ /* prepare */ ++ for (i = 0; i < num_bo; i++) { ++ buf = bos[i].buf; ++ gem_bo = (dri_bo_gem *)buf; ++ ++ bos[i].new_accounted = 0; ++ read_domains = bos[i].read_domains; ++ write_domain = bos[i].write_domain; ++ ++ /* pinned bos don't count */ ++ if (gem_bo->pinned) ++ continue; ++ ++ /* already accounted this bo */ ++ if (write_domain && (write_domain == gem_bo->space_accounted)) ++ continue; ++ ++ if (read_domains && ((read_domains << 16) == gem_bo->space_accounted)) ++ continue; ++ ++ if (gem_bo->space_accounted == 0) { ++ if (write_domain == RADEON_GEM_DOMAIN_VRAM) ++ this_op_vram_write += buf->size; ++ else if (write_domain == RADEON_GEM_DOMAIN_GTT) ++ this_op_gart_write += buf->size; ++ else ++ this_op_read += buf->size; ++ bos[i].new_accounted = (read_domains << 16) | write_domain; ++ } else { ++ uint16_t old_read, old_write; ++ ++ old_read = gem_bo->space_accounted >> 16; ++ old_write = gem_bo->space_accounted & 0xffff; ++ ++ if (write_domain && (old_read & write_domain)) { ++ bos[i].new_accounted = write_domain; ++ /* moving from read to a write domain */ ++ if (write_domain == RADEON_GEM_DOMAIN_VRAM) { ++ this_op_read -= buf->size; ++ this_op_vram_write += buf->size; ++ } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) { ++ this_op_read -= buf->size; ++ this_op_gart_write += buf->size; ++ } ++ } else if (read_domains & old_write) { ++ bos[i].new_accounted = gem_bo->space_accounted & 0xffff; ++ } else { ++ /* rewrite the domains */ ++ if (write_domain != old_write) ++ ErrorF("WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", gem_bo->gem_handle, write_domain, old_write); ++ if (read_domains != old_read) ++ ErrorF("READ DOMAIN RELOC FAILURE 0x%x %d %d\n", gem_bo->gem_handle, read_domains, old_read); ++ return BUFMGR_SPACE_FLUSH; ++ } ++ } + } ++ ++ if (this_op_read < 0) ++ this_op_read = 0; + -+ if (bufmgr_gem->vram_write_used > bufmgr_gem->vram_limit) { -+ bufmgr_gem->vram_write_used = 0; -+ return -1; ++ /* check sizes - operation first */ ++ if ((this_op_read + this_op_gart_write > bufmgr_gem->gart_limit) || ++ (this_op_vram_write > bufmgr_gem->vram_limit)) { ++ return BUFMGR_SPACE_OP_TO_BIG; + } + -+ gem_bo->space_accounted = 1; ++ if (((bufmgr_gem->vram_write_used + this_op_vram_write) > bufmgr_gem->vram_limit) || ++ ((bufmgr_gem->read_used + bufmgr_gem->gart_write_used + this_op_gart_write + this_op_read) > bufmgr_gem->gart_limit)) { ++ return BUFMGR_SPACE_FLUSH; ++ } + -+ return 0; ++ bufmgr_gem->gart_write_used += this_op_gart_write; ++ bufmgr_gem->vram_write_used += this_op_vram_write; ++ bufmgr_gem->read_used += this_op_read; ++ /* commit */ ++ for (i = 0; i < num_bo; i++) { ++ buf = bos[i].buf; ++ gem_bo = (dri_bo_gem *)buf; ++ gem_bo->space_accounted = bos[i].new_accounted; ++ } ++ ++ return BUFMGR_SPACE_OK; +} + +/** @@ -2975,31 +3030,31 @@ index 0000000..7a41852 +} + + -+void radeon_gem_bufmgr_post_submit(dri_bufmgr *bufmgr, struct radeon_relocs_info *reloc_info) ++void radeon_gem_bufmgr_post_submit(dri_bufmgr *bufmgr, struct radeon_relocs_info *reloc_info, int error) +{ + dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr; + struct _dri_bo_gem *trav, *prev; + int i; + ++ if (error) { ++ ErrorF("bufmgr: last submission : r:%d vs g:%d w:%d vs v:%d\n", ++ bufmgr_gem->read_used, bufmgr_gem->gart_limit, ++ bufmgr_gem->vram_write_used, bufmgr_gem->vram_limit); ++ } ++ + if (!bufmgr_gem->bo_list) + return; + + for (i = 0; i < reloc_info->num_reloc; i++) { -+ trav = bufmgr_gem->bo_list; -+ while (trav) { -+ prev = trav; -+ trav = trav->next; -+ -+ if (prev->gem_handle == reloc_info->buf[i * 4]) { -+ prev->space_accounted = 0; -+ dri_bo_unreference(&prev->bo); -+ } -+ } ++ trav = (dri_bo_gem *)reloc_info->bo_list[i]; ++ ++ trav->space_accounted = 0; ++ dri_bo_unreference(&trav->bo); + } + -+// bufmgr_gem->reloc_head = NULL; + bufmgr_gem->read_used = 0; + bufmgr_gem->vram_write_used = 0; ++ bufmgr_gem->gart_write_used = 0; + +} + @@ -3021,35 +3076,57 @@ index 0000000..7a41852 + return gem_bo->touched; +} + -+void radeon_bufmgr_gem_set_vram_limit(dri_bufmgr *bufmgr, uint32_t vram_limit) ++void radeon_bufmgr_gem_set_limit(dri_bufmgr *bufmgr, uint32_t domain, uint32_t limit) +{ + dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr; + -+ bufmgr_gem->vram_limit = vram_limit; ++ if (domain == RADEON_GEM_DOMAIN_VRAM) ++ bufmgr_gem->vram_limit = limit; ++ else ++ bufmgr_gem->gart_limit = limit; ++ ++} ++ ++void radeon_bufmgr_gem_force_gtt(dri_bo *buf) ++{ ++ dri_bo_gem *gem_bo = (dri_bo_gem *)buf; ++ ++ if (!gem_bo->pinned && !gem_bo->force_gtt) ++ gem_bo->force_gtt = 1; ++} ++ ++int radeon_bufmgr_gem_in_vram(dri_bo *buf) ++{ ++ dri_bo_gem *gem_bo = (dri_bo_gem *)buf; ++ return gem_bo->in_vram; +} diff --git a/src/radeon_bufmgr_gem.h b/src/radeon_bufmgr_gem.h new file mode 100644 -index 0000000..e4f074c +index 0000000..7c32b61 --- /dev/null +++ b/src/radeon_bufmgr_gem.h -@@ -0,0 +1,15 @@ +@@ -0,0 +1,19 @@ +#ifndef RADEON_BUFMGR_GEM_H +#define RADEON_BUFMGR_GEM_H + +#include "radeon_dri_bufmgr.h" + ++ +extern void radeon_bufmgr_gem_wait_rendering(dri_bo *bo); +extern dri_bo *radeon_bufmgr_gem_create_bo(dri_bufmgr *bufmgr, struct radeon_memory *mem); +void radeon_bufmgr_gem_emit_reloc(dri_bo *bo, struct radeon_relocs_info *reloc_info, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); -+void radeon_gem_bufmgr_post_submit(dri_bufmgr *bufmgr, struct radeon_relocs_info *reloc_info); ++void radeon_gem_bufmgr_post_submit(dri_bufmgr *bufmgr, struct radeon_relocs_info *reloc_info, int error); +void radeon_bufmgr_pin(dri_bo *buf); +void radeon_bufmgr_unpin(dri_bo *buf); +uint32_t radeon_bufmgr_get_handle(dri_bo *buf); +int radeon_bufmgr_gem_has_references(dri_bo *buf); -+void radeon_bufmgr_gem_set_vram_limit(dri_bufmgr *bufmgr, uint32_t vram_limit); ++int radeon_bufmgr_gem_force_gtt(dri_bo *buf); ++void radeon_bufmgr_gem_set_limit(dri_bufmgr *bufmgr, uint32_t domain, uint32_t limit); ++int radeon_bufmgr_gem_in_vram(dri_bo *buf); ++ +#endif diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index dba197e..10d146e 100644 +index 0a9f9db..07f83e0 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -62,12 +62,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) @@ -3088,7 +3165,7 @@ index dba197e..10d146e 100644 OUT_ACCEL_REG(R300_GB_SELECT, 0); OUT_ACCEL_REG(R300_GB_ENABLE, 0); FINISH_ACCEL(); -@@ -687,7 +692,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) +@@ -715,7 +720,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) #ifdef ACCEL_CP /* Make sure the CP is idle first */ @@ -3098,7 +3175,7 @@ index dba197e..10d146e 100644 FLUSH_RING(); diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c -index 08bfddf..53dcb8a 100644 +index 0fcdcf0..49601cf 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -96,12 +96,19 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) @@ -3131,7 +3208,7 @@ index 08bfddf..53dcb8a 100644 if (x < 0) xorigin = -x+1; if (y < 0) yorigin = -y+1; -@@ -235,8 +243,12 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) +@@ -233,8 +241,12 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) | (yorigin ? 0 : y))); RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); @@ -3145,7 +3222,7 @@ index 08bfddf..53dcb8a 100644 } else if (crtc_id == 1) { OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK | (xorigin << 16) -@@ -246,8 +258,12 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) +@@ -244,8 +256,12 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) | (yorigin ? 0 : y))); RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); @@ -3159,7 +3236,7 @@ index 08bfddf..53dcb8a 100644 } } } -@@ -301,10 +317,15 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) +@@ -299,10 +315,15 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(pScrn); CURSOR_SWAPPING_DECL_MMIO @@ -3176,7 +3253,7 @@ index 08bfddf..53dcb8a 100644 info->cursor_argb = TRUE; CURSOR_SWAPPING_START(); -@@ -335,7 +356,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) +@@ -333,7 +354,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; int align = IS_AVIVO_VARIANT ? 4096 : 256; @@ -3186,7 +3263,7 @@ index 08bfddf..53dcb8a 100644 xf86CrtcPtr crtc = xf86_config->crtc[c]; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index 5542d2b..a4e8dea 100644 +index 7c317e6..8217b6e 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -40,6 +40,8 @@ @@ -3422,17 +3499,17 @@ index 5542d2b..a4e8dea 100644 + } - /* Set AGP transfer mode according to requests and constraints */ -@@ -888,6 +1037,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] ring handle = 0x%08x\n", info->dri->ringHandle); + /* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with +@@ -952,6 +1101,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) + "[agp] ring handle = 0x%08x\n", + (unsigned int)info->dri->ringHandle); + +#if 0 if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, &info->dri->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); -@@ -896,9 +1047,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -960,9 +1111,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Ring mapped at 0x%08lx\n", (unsigned long)info->dri->ring); @@ -3444,16 +3521,16 @@ index 5542d2b..a4e8dea 100644 xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not add ring read ptr mapping\n"); return FALSE; -@@ -907,6 +1059,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -971,6 +1123,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) "[agp] ring read ptr handle = 0x%08x\n", - info->dri->ringReadPtrHandle); + (unsigned int)info->dri->ringReadPtrHandle); + +#if 0 if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, &info->dri->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -916,6 +1070,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -980,6 +1134,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Ring read ptr mapped at 0x%08lx\n", (unsigned long)info->dri->ringReadPtr); @@ -3461,15 +3538,15 @@ index 5542d2b..a4e8dea 100644 if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, DRM_AGP, 0, &info->dri->bufHandle) < 0) { -@@ -991,6 +1146,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] ring handle = 0x%08x\n", info->dri->ringHandle); +@@ -1057,6 +1212,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) + "[pci] ring handle = 0x%08x\n", + (unsigned int)info->dri->ringHandle); +#if 0 if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, &info->dri->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); -@@ -1002,6 +1158,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1068,6 +1224,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] Ring contents 0x%08lx\n", *(unsigned long *)(pointer)info->dri->ring); @@ -3477,9 +3554,9 @@ index 5542d2b..a4e8dea 100644 if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) { -@@ -1013,8 +1170,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1079,8 +1236,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) "[pci] ring read ptr handle = 0x%08x\n", - info->dri->ringReadPtrHandle); + (unsigned int)info->dri->ringReadPtrHandle); +#if 0 if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, @@ -3488,7 +3565,7 @@ index 5542d2b..a4e8dea 100644 xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring read ptr\n"); return FALSE; -@@ -1025,6 +1184,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1091,6 +1250,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] Ring read ptr contents 0x%08lx\n", *(unsigned long *)(pointer)info->dri->ringReadPtr); @@ -3496,7 +3573,7 @@ index 5542d2b..a4e8dea 100644 if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) { -@@ -1077,6 +1237,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1143,6 +1303,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) */ static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) { @@ -3506,7 +3583,7 @@ index 5542d2b..a4e8dea 100644 /* Map registers */ info->dri->registerSize = info->MMIOSize; if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize, -@@ -1115,20 +1278,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1182,20 +1345,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) drmInfo.fb_bpp = info->CurrentLayout.pixel_code; drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2; @@ -3544,7 +3621,7 @@ index 5542d2b..a4e8dea 100644 if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drm_radeon_init_t)) < 0) return FALSE; -@@ -1137,7 +1303,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1204,7 +1370,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) * registers back to their default values, so we need to restore * those engine register here. */ @@ -3554,7 +3631,7 @@ index 5542d2b..a4e8dea 100644 return TRUE; } -@@ -1333,12 +1500,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1400,12 +1567,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) /* Get DRM version & close DRM */ info->dri->pKernelDRMVersion = drmGetVersion(fd); @@ -3568,7 +3645,7 @@ index 5542d2b..a4e8dea 100644 } /* Now check if we qualify */ -@@ -1372,10 +1538,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1439,10 +1605,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) req_patch); drmFreeVersion(info->dri->pKernelDRMVersion); info->dri->pKernelDRMVersion = NULL; @@ -3599,7 +3676,7 @@ index 5542d2b..a4e8dea 100644 } Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) -@@ -1384,6 +1569,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1451,6 +1636,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int value = 0; @@ -3609,7 +3686,7 @@ index 5542d2b..a4e8dea 100644 if (!info->want_vblank_interrupts) on = FALSE; -@@ -1403,6 +1591,48 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1470,6 +1658,48 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) return TRUE; } @@ -3658,7 +3735,7 @@ index 5542d2b..a4e8dea 100644 /* Initialize the screen-specific data structures for the DRI and the * Radeon. This is the main entry point to the device-specific -@@ -1466,10 +1696,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1533,10 +1763,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; pDRIInfo->ddxDriverMinorVersion = 3; pDRIInfo->ddxDriverPatchVersion = 0; @@ -3685,7 +3762,7 @@ index 5542d2b..a4e8dea 100644 pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES < RADEON_MAX_DRAWABLES -@@ -1522,9 +1764,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1589,9 +1831,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; @@ -3696,7 +3773,7 @@ index 5542d2b..a4e8dea 100644 pDRIInfo->ClipNotify = RADEONDRIClipNotify; #endif -@@ -1556,57 +1796,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1623,57 +1863,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo = NULL; return FALSE; } @@ -3801,7 +3878,7 @@ index 5542d2b..a4e8dea 100644 static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -@@ -1648,14 +1891,18 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1715,14 +1958,18 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) return FALSE; } @@ -3826,7 +3903,7 @@ index 5542d2b..a4e8dea 100644 /* Initialize kernel GART memory manager */ RADEONDRIGartHeapInit(info, pScreen); -@@ -1667,6 +1914,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1734,6 +1981,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen); memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); @@ -3837,7 +3914,7 @@ index 5542d2b..a4e8dea 100644 pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; pRADEONDRI->deviceID = info->Chipset; -@@ -1823,6 +2074,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1890,6 +2141,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->dri->buf, info->dri->bufMapSize); info->dri->buf = NULL; } @@ -3846,7 +3923,7 @@ index 5542d2b..a4e8dea 100644 if (info->dri->ringReadPtr) { drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize); info->dri->ringReadPtr = NULL; -@@ -1831,6 +2084,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1898,6 +2151,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->dri->ring, info->dri->ringMapSize); info->dri->ring = NULL; } @@ -3854,7 +3931,7 @@ index 5542d2b..a4e8dea 100644 if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) { drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle); drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); -@@ -2237,3 +2491,16 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) +@@ -2304,3 +2558,16 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) &radeonsetparam, sizeof(drm_radeon_setparam_t)); return ret; } @@ -3873,10 +3950,10 @@ index 5542d2b..a4e8dea 100644 +} diff --git a/src/radeon_dri_bufmgr.c b/src/radeon_dri_bufmgr.c new file mode 100644 -index 0000000..12263c3 +index 0000000..f6154dc --- /dev/null +++ b/src/radeon_dri_bufmgr.c -@@ -0,0 +1,174 @@ +@@ -0,0 +1,177 @@ +/* + * Copyright © 2007 Intel Corporation + * @@ -4032,9 +4109,12 @@ index 0000000..12263c3 +} + +int -+dri_bufmgr_check_aperture_space(dri_bo *bo, uint32_t read_domains, uint32_t write_domain) ++dri_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo) +{ -+ return bo->bufmgr->check_aperture_space(bo, read_domains, write_domain); ++ if (num_bo == 0) ++ return BUFMGR_SPACE_OK; ++ ++ return bos[0].buf->bufmgr->check_aperture_space(bos, num_bo); +} + +int dri_bo_pin(dri_bo *bo, int domain) @@ -4053,10 +4133,10 @@ index 0000000..12263c3 +} diff --git a/src/radeon_dri_bufmgr.h b/src/radeon_dri_bufmgr.h new file mode 100644 -index 0000000..041671f +index 0000000..a19d7ec --- /dev/null +++ b/src/radeon_dri_bufmgr.h -@@ -0,0 +1,279 @@ +@@ -0,0 +1,291 @@ +/************************************************************************** + * + * Copyright � 2007 Intel Corporation @@ -4099,12 +4179,24 @@ index 0000000..041671f +typedef struct _dri_bo dri_bo; +typedef struct _dri_fence dri_fence; + ++#define BUFMGR_SPACE_OK 0 ++#define BUFMGR_SPACE_OP_TO_BIG 1 ++#define BUFMGR_SPACE_FLUSH 2 ++struct radeon_space_check { ++ dri_bo *buf; ++ uint32_t read_domains; ++ uint32_t write_domain; ++ uint32_t new_accounted; ++}; ++ +/* reloc format */ +/* gem handle, read_domains, write_domain, reloc_count */ +#define RADEON_RELOC_SIZE 4 +struct radeon_relocs_info { + uint32_t *buf; ++ dri_bo **bo_list; + int size; ++ int max_bo; + int num_reloc; +}; + @@ -4244,7 +4336,7 @@ index 0000000..041671f + + void (*post_submit)(dri_bo *batch_buf, dri_fence **fence); + -+ int (*check_aperture_space)(dri_bo *bo, uint32_t read_domains, uint32_t write_domain); ++ int (*check_aperture_space)(struct radeon_space_check *bos, int num_bo); + + int (*pin)(dri_bo *bo, int domain); + void (*unpin)(dri_bo *bo); @@ -4290,7 +4382,7 @@ index 0000000..041671f +void *dri_process_relocs(dri_bo *batch_buf, uint32_t *count); +void dri_post_process_relocs(dri_bo *batch_buf); +void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence); -+int dri_bufmgr_check_aperture_space(dri_bo *bo, uint32_t read_domains, uint32_t write_domain); ++int dri_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo); + +int dri_bo_pin(dri_bo *bo, int domain); +void dri_bo_unpin(dri_bo *bo); @@ -4337,9 +4429,18 @@ index 0000000..041671f + +#endif diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index c759bd6..0efe9de 100644 +index d414854..6775372 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c +@@ -67,7 +67,7 @@ + + #include + #include +- ++#include + /* Driver data structures */ + #include "radeon.h" + #include "radeon_reg.h" @@ -224,7 +224,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; @@ -4360,13 +4461,16 @@ index c759bd6..0efe9de 100644 info->FbMapSize = pScrn->videoRam * 1024; /* if the card is PCI Express reserve the last 32k for the gart table */ -@@ -1747,56 +1751,62 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1750,58 +1754,64 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + } + from = X_PROBED; - info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; +- info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; ++ info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; pScrn->memPhysBase = info->LinearAddr; - if (dev->MemBase) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "Linear address override, using 0x%016lx instead of 0x%016lx\n", +- "Linear address override, using 0x%016lx instead of 0x%016llx\n", - dev->MemBase, - info->LinearAddr); - info->LinearAddr = dev->MemBase; @@ -4377,7 +4481,7 @@ index c759bd6..0efe9de 100644 - return FALSE; - } - xf86DrvMsg(pScrn->scrnIndex, from, -- "Linear framebuffer at 0x%016lx\n", info->LinearAddr); +- "Linear framebuffer at 0x%016llx\n", info->LinearAddr); -#ifndef XSERVER_LIBPCIACCESS - /* BIOS */ @@ -4386,8 +4490,8 @@ index c759bd6..0efe9de 100644 - if (dev->BiosBase) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "BIOS address override, using 0x%08lx instead of 0x%08lx\n", -- dev->BiosBase, -- info->BIOSAddr); +- (unsigned long)dev->BiosBase, +- (unsigned long)info->BIOSAddr); - info->BIOSAddr = dev->BiosBase; - from = X_CONFIG; - } @@ -4398,7 +4502,7 @@ index c759bd6..0efe9de 100644 + pScrn->memPhysBase = info->LinearAddr; + if (dev->MemBase) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, -+ "Linear address override, using 0x%016lx instead of 0x%016lx\n", ++ "Linear address override, using 0x%016lx instead of 0x%016llx\n", + dev->MemBase, + info->LinearAddr); + info->LinearAddr = dev->MemBase; @@ -4409,9 +4513,9 @@ index c759bd6..0efe9de 100644 + return FALSE; + } xf86DrvMsg(pScrn->scrnIndex, from, -- "BIOS at 0x%08lx\n", info->BIOSAddr); +- "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); - } -+ "Linear framebuffer at 0x%016lx\n", info->LinearAddr); ++ "Linear framebuffer at 0x%016llx\n", info->LinearAddr); + +#ifndef XSERVER_LIBPCIACCESS + /* BIOS */ @@ -4465,7 +4569,7 @@ index c759bd6..0efe9de 100644 #ifdef XF86DRI /* AGP/PCI */ -@@ -1989,6 +1999,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -1994,6 +2004,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; @@ -4475,7 +4579,7 @@ index c759bd6..0efe9de 100644 from = X_DEFAULT; #if defined(USE_EXA) #if defined(USE_XAA) -@@ -1999,6 +2012,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2004,6 +2017,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) info->useEXA = TRUE; } else if (xf86NameCmp(optstr, "XAA") == 0) { from = X_CONFIG; @@ -4483,7 +4587,7 @@ index c759bd6..0efe9de 100644 } } #else /* USE_XAA */ -@@ -2102,15 +2116,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -2107,15 +2121,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) return TRUE; } @@ -4500,7 +4604,7 @@ index c759bd6..0efe9de 100644 if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); -@@ -2121,6 +2129,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2126,6 +2134,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); return FALSE; } @@ -4523,7 +4627,7 @@ index c759bd6..0efe9de 100644 info->cp->CPInUse = FALSE; info->cp->CPStarted = FALSE; info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; -@@ -2685,6 +2709,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { +@@ -2690,6 +2714,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { RADEONCRTCResize }; @@ -4561,7 +4665,7 @@ index c759bd6..0efe9de 100644 Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) { xf86CrtcConfigPtr xf86_config; -@@ -2705,6 +2760,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2710,6 +2765,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info = RADEONPTR(pScrn); info->MMIO = NULL; @@ -4570,18 +4674,21 @@ index c759bd6..0efe9de 100644 info->IsSecondary = FALSE; info->IsPrimary = FALSE; -@@ -2739,59 +2796,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2744,62 +2801,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); - info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), - PCI_DEV_DEV(info->PciInfo), - PCI_DEV_FUNC(info->PciInfo)); -- info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffUL; +- info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; - info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", +- (unsigned long long)PCI_REGION_BASE(info->PciInfo, +- 2, REGION_MEM)); - if (info->pEnt->device->IOBase) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, -- "MMIO address override, using 0x%08lx instead of 0x%08lx\n", +- "MMIO address override, using 0x%08lx instead of 0x%016llx\n", - info->pEnt->device->IOBase, - info->MMIOAddr); - info->MMIOAddr = info->pEnt->device->IOBase; @@ -4590,7 +4697,7 @@ index c759bd6..0efe9de 100644 - goto fail1; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "MMIO registers at 0x%016lx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); +- "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); - if(!RADEONMapMMIO(pScrn)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -4602,11 +4709,11 @@ index c759bd6..0efe9de 100644 + info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), + PCI_DEV_DEV(info->PciInfo), + PCI_DEV_FUNC(info->PciInfo)); -+ info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffUL; ++ info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; + info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); + if (info->pEnt->device->IOBase) { + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, -+ "MMIO address override, using 0x%08lx instead of 0x%08lx\n", ++ "MMIO address override, using 0x%08lx instead of 0x%08llx\n", + info->pEnt->device->IOBase, + info->MMIOAddr); + info->MMIOAddr = info->pEnt->device->IOBase; @@ -4615,7 +4722,7 @@ index c759bd6..0efe9de 100644 + goto fail1; + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, -+ "MMIO registers at 0x%016lx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); ++ "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); + + if(!RADEONMapMMIO(pScrn)) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -4678,7 +4785,7 @@ index c759bd6..0efe9de 100644 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; -@@ -2801,10 +2862,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2809,10 +2867,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; @@ -4695,7 +4802,7 @@ index c759bd6..0efe9de 100644 if (!RADEONPreInitVisual(pScrn)) goto fail; -@@ -2818,136 +2881,197 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2826,136 +2886,197 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); @@ -4907,14 +5014,14 @@ index c759bd6..0efe9de 100644 + xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y); + + RADEONPreInitDDC(pScrn); -+ -+ if (!RADEONPreInitControllers(pScrn)) -+ goto fail; - RADEONPreInitDDC(pScrn); ++ if (!RADEONPreInitControllers(pScrn)) ++ goto fail; - if (!RADEONPreInitControllers(pScrn)) - goto fail; + + ErrorF("before xf86InitialConfiguration\n"); + + if (!xf86InitialConfiguration (pScrn, FALSE)) @@ -4925,13 +5032,18 @@ index c759bd6..0efe9de 100644 + + ErrorF("after xf86InitialConfiguration\n"); +- ErrorF("before xf86InitialConfiguration\n"); + } else { +#ifdef XF86DRM_MODE + char *bus_id; + if (!radeon_alloc_dri(pScrn)) + return FALSE; -- ErrorF("before xf86InitialConfiguration\n"); +- if (!xf86InitialConfiguration (pScrn, FALSE)) +- { +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); +- goto fail; +- } + bus_id = DRICreatePCIBusID(info->PciInfo); + if (drmmode_pre_init(pScrn, &info->drmmode, bus_id, "radeon", pScrn->bitsPerPixel / 8) == FALSE) { + xfree(bus_id); @@ -4939,11 +5051,7 @@ index c759bd6..0efe9de 100644 + goto fail; + } -- if (!xf86InitialConfiguration (pScrn, FALSE)) -- { -- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); -- goto fail; -- } +- ErrorF("after xf86InitialConfiguration\n"); + info->drmmode.create_new_fb = radeon_create_new_fb; + info->dri->drmFD = info->drmmode.fd; + xfree(bus_id); @@ -4963,8 +5071,7 @@ index c759bd6..0efe9de 100644 + { + struct drm_radeon_getparam gp; + int value; - -- ErrorF("after xf86InitialConfiguration\n"); ++ + memset(&gp, 0, sizeof(gp)); + gp.param = RADEON_PARAM_FB_LOCATION; + gp.value = &value; @@ -4998,7 +5105,7 @@ index c759bd6..0efe9de 100644 /* Get ScreenInit function */ if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; -@@ -2962,10 +3086,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2970,10 +3091,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitXv(pScrn)) goto fail; } @@ -5015,7 +5122,7 @@ index c759bd6..0efe9de 100644 } if (pScrn->modes == NULL) { -@@ -3206,7 +3332,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3214,7 +3337,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int subPixelOrder = SubPixelUnknown; char* s; #endif @@ -5024,7 +5131,7 @@ index c759bd6..0efe9de 100644 info->accelOn = FALSE; #ifdef USE_XAA -@@ -3226,52 +3352,55 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3234,52 +3357,55 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "RADEONScreenInit %lx %ld\n", pScrn->memPhysBase, pScrn->fbOffset); #endif @@ -5114,7 +5221,7 @@ index c759bd6..0efe9de 100644 /* Visual setup */ miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, -@@ -3305,19 +3434,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3313,19 +3439,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, hasDRI = info->directRenderingEnabled; #endif /* XF86DRI */ @@ -5149,10 +5256,11 @@ index c759bd6..0efe9de 100644 } } -@@ -3357,11 +3488,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3365,11 +3493,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (hasDRI) { info->accelDFS = info->cardType != CARD_AGP; ++ /* disable DFS by default */ + if (info->cardType != CARD_PCIE && info->drm_mm) + info->accelDFS = FALSE; + @@ -5165,7 +5273,7 @@ index c759bd6..0efe9de 100644 /* Reserve approx. half of offscreen memory for local textures by * default, can be overridden with Option "FBTexPercent". * Round down to a whole number of texture regions. -@@ -3390,7 +3525,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3398,7 +3531,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif #if defined(XF86DRI) && defined(USE_XAA) @@ -5174,7 +5282,7 @@ index c759bd6..0efe9de 100644 info->dri->textureSize = -1; if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, &(info->dri->textureSize))) { -@@ -3408,7 +3543,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3416,7 +3549,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif #ifdef USE_XAA @@ -5183,7 +5291,7 @@ index c759bd6..0efe9de 100644 return FALSE; #endif -@@ -3429,7 +3564,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3437,7 +3570,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->CurrentLayout.pixel_bytes); int maxy = info->FbMapSize / width_bytes; @@ -5192,7 +5300,7 @@ index c759bd6..0efe9de 100644 xf86DrvMsg(scrnIndex, X_ERROR, "Static buffer allocation failed. Disabling DRI.\n"); xf86DrvMsg(scrnIndex, X_ERROR, -@@ -3443,15 +3578,39 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3451,15 +3584,42 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } @@ -5212,6 +5320,8 @@ index c759bd6..0efe9de 100644 + info->bufmgr = radeon_bufmgr_gem_init(info->dri->drmFD); + drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); + //radeon_bufmgr_gem_enable_reuse(info->bufmgr); ++ radeon_bufmgr_gem_set_limit(info->bufmgr, RADEON_GEM_DOMAIN_GTT, info->mm.gart_size - info->dri->gartTexMapSize); ++ + radeon_setup_kernel_mem(pScreen); + front_ptr = info->mm.front_buffer->map; + pScrn->fbOffset = info->mm.front_buffer->offset; @@ -5230,12 +5340,13 @@ index c759bd6..0efe9de 100644 } } + -+ RADEONDRIDoMappings(pScreen); ++ if (info->directRenderingEnabled == TRUE) ++ RADEONDRIDoMappings(pScreen); + #endif xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing fb layer\n"); -@@ -3475,7 +3634,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3483,7 +3643,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->r600_shadow_fb == FALSE) { /* Init fb layer */ @@ -5244,7 +5355,7 @@ index c759bd6..0efe9de 100644 pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) -@@ -3517,8 +3676,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3525,8 +3685,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* restore the memory map here otherwise we may get a hang when * initializing the drm below */ @@ -5257,7 +5368,7 @@ index c759bd6..0efe9de 100644 /* Backing store setup */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -3528,7 +3689,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3536,7 +3698,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* DRI finalisation */ #ifdef XF86DRI @@ -5266,7 +5377,7 @@ index c759bd6..0efe9de 100644 info->dri->pKernelDRMVersion->version_minor >= 19) { if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) -@@ -3547,11 +3708,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3555,11 +3717,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); } if (info->directRenderingEnabled) { @@ -5285,15 +5396,25 @@ index c759bd6..0efe9de 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); -@@ -3649,6 +3816,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3657,10 +3825,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, return FALSE; } } + pScrn->pScreen = pScreen; /* set the modes with desired rotation, etc. */ - if (!xf86SetDesiredModes (pScrn)) -@@ -5133,7 +5301,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +- if (!xf86SetDesiredModes (pScrn)) ++ if (info->drm_mode_setting) { ++ if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) ++ return FALSE; ++ } else { ++ if (!xf86SetDesiredModes (pScrn)) + return FALSE; ++ } + + /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ + /* Wrap CloseScreen */ +@@ -5141,7 +5315,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) #ifdef XF86DRI Bool CPStarted = info->cp->CPStarted; @@ -5302,7 +5423,7 @@ index c759bd6..0efe9de 100644 DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); } -@@ -5156,8 +5324,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5164,8 +5338,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) #endif } @@ -5315,7 +5436,7 @@ index c759bd6..0efe9de 100644 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); -@@ -5169,15 +5339,18 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5177,15 +5353,18 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) /* xf86SetRootClip would do, but can't access that here */ } @@ -5341,7 +5462,7 @@ index c759bd6..0efe9de 100644 } #endif -@@ -5375,6 +5548,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5383,6 +5562,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) xf86OutputPtr output = config->output[config->compat_output]; xf86CrtcPtr crtc = output->crtc; @@ -5353,7 +5474,7 @@ index c759bd6..0efe9de 100644 #ifdef XF86DRI if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); #endif -@@ -5410,67 +5588,79 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5418,67 +5602,92 @@ Bool RADEONEnterVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); @@ -5420,7 +5541,13 @@ index c759bd6..0efe9de 100644 - if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { - atombios_static_pwrmgt_setup(pScrn, 1); - atombios_dyn_clk_setup(pScrn, 1); -- } ++ } else { ++ int ret; ++ if (info->drm_mode_setting) { ++ ret = ioctl(info->dri->drmFD, DRM_IOCTL_SET_MASTER, NULL); ++ if (ret == -EINVAL) ++ ErrorF("Unable to retrieve master\n"); + } } - if (IS_R300_VARIANT || IS_RV100_VARIANT) @@ -5433,16 +5560,23 @@ index c759bd6..0efe9de 100644 - for (i = 0; i < config->num_crtc; i++) - radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); -+ radeon_update_dri_buffers(pScrn->pScreen); ++ if (info->directRenderingEnabled) ++ radeon_update_dri_buffers(pScrn->pScreen); pScrn->vtSema = TRUE; +- if (!xf86SetDesiredModes(pScrn)) + if (!info->drm_mode_setting) + for (i = 0; i < config->num_crtc; i++) + radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); + - if (!xf86SetDesiredModes(pScrn)) ++ if (info->drm_mode_setting) { ++ if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) ++ return FALSE; ++ } else { ++ if (!xf86SetDesiredModes(pScrn)) return FALSE; ++ } - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONRestoreSurfaces(pScrn, info->ModeReg); @@ -5478,7 +5612,7 @@ index c759bd6..0efe9de 100644 } #endif /* this will get XVideo going again, but only if XVideo was initialised -@@ -5482,7 +5672,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5490,7 +5699,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) RADEONEngineRestore(pScrn); #ifdef XF86DRI @@ -5487,7 +5621,7 @@ index c759bd6..0efe9de 100644 RADEONCP_START(pScrn, info); DRIUnlock(pScrn->pScreen); } -@@ -5505,17 +5695,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5513,17 +5722,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) "RADEONLeaveVT\n"); #ifdef XF86DRI if (RADEONPTR(pScrn)->directRenderingInited) { @@ -5517,13 +5651,28 @@ index c759bd6..0efe9de 100644 /* Make sure 3D clients will re-upload textures to video RAM */ if (info->dri->textureSize) { -@@ -5551,10 +5742,15 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5539,6 +5749,11 @@ void RADEONLeaveVT(int scrnIndex, int flags) + i = list[i].next; + } while (i != 0); + } ++ ++ if (info->drm_mode_setting) ++ ioctl(info->dri->drmFD, DRM_IOCTL_DROP_MASTER, NULL); ++ ++ + } + #endif + +@@ -5559,10 +5774,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) xf86_hide_cursors (pScrn); - RADEONRestore(pScrn); -+ if (info->drm_mm) ++ if (info->drm_mm) { ++ info->accel_state->XInited3D = FALSE; ++ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; + radeon_unbind_all_memory(pScrn); ++ } + + if (!info->drm_mode_setting) { + RADEONRestore(pScrn); @@ -5536,7 +5685,7 @@ index c759bd6..0efe9de 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); -@@ -5599,7 +5795,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5607,7 +5830,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #endif /* USE_XAA */ if (pScrn->vtSema) { @@ -5546,7 +5695,7 @@ index c759bd6..0efe9de 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5634,6 +5831,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5642,6 +5866,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) info->DGAModes = NULL; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unmapping memory\n"); @@ -5560,7 +5709,7 @@ index c759bd6..0efe9de 100644 pScrn->vtSema = FALSE; diff --git a/src/radeon_drm.h b/src/radeon_drm.h -index 66cefb7..af7d382 100644 +index 54bc234..9241a88 100644 --- a/src/radeon_drm.h +++ b/src/radeon_drm.h @@ -303,7 +303,6 @@ typedef union { @@ -5587,7 +5736,7 @@ index 66cefb7..af7d382 100644 } drm_radeon_sarea_t; /* WARNING: If you change any of these defines, make sure to change the -@@ -494,6 +502,19 @@ typedef struct { +@@ -494,6 +502,18 @@ typedef struct { #define DRM_RADEON_SURF_ALLOC 0x1a #define DRM_RADEON_SURF_FREE 0x1b @@ -5601,13 +5750,12 @@ index 66cefb7..af7d382 100644 +#define DRM_RADEON_GEM_SET_DOMAIN 0x23 +#define DRM_RADEON_GEM_WAIT_RENDERING 0x24 + -+#define DRM_RADEON_CS 0x25 -+#define DRM_RADEON_CS2 0x26 ++#define DRM_RADEON_CS 0x26 + #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) -@@ -522,16 +543,28 @@ typedef struct { +@@ -522,16 +542,27 @@ typedef struct { #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) @@ -5621,7 +5769,6 @@ index 66cefb7..af7d382 100644 +#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) +#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering) +#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) -+#define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2) + + typedef struct drm_radeon_init { @@ -5639,73 +5786,73 @@ index 66cefb7..af7d382 100644 int cp_mode; int gart_size; int ring_size; -@@ -543,9 +576,8 @@ typedef struct drm_radeon_init { +@@ -543,9 +574,8 @@ typedef struct drm_radeon_init { unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; - /* DEPRECATED commented out below to allow for -Werror build */ -- unsigned long fb_offset /*DEPRECATED*/; /* deprecated, driver asks hardware */ -- unsigned long mmio_offset /*DEPRECATED*/; /* deprecated, driver asks hardware */ +- unsigned long fb_offset; /* deprecated, driver asks hardware */ +- unsigned long mmio_offset; /* deprecated, driver asks hardware */ + unsigned long fb_offset; + unsigned long mmio_offset; unsigned long ring_offset; unsigned long ring_rptr_offset; unsigned long buffers_offset; -@@ -581,7 +613,7 @@ typedef struct drm_radeon_clear { +@@ -581,7 +611,7 @@ typedef struct drm_radeon_clear { unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; /* misnamed field: should be stencil */ -- drm_radeon_clear_rect_t __user *depth_boxes; +- drm_radeon_clear_rect_t *depth_boxes; + drm_radeon_clear_rect_t *depth_boxes; } drm_radeon_clear_t; typedef struct drm_radeon_vertex { -@@ -607,9 +639,9 @@ typedef struct drm_radeon_vertex2 { +@@ -607,9 +637,9 @@ typedef struct drm_radeon_vertex2 { int idx; /* Index of vertex buffer */ int discard; /* Client finished with buffer? */ int nr_states; -- drm_radeon_state_t __user *state; +- drm_radeon_state_t *state; + drm_radeon_state_t *state; int nr_prims; -- drm_radeon_prim_t __user *prim; +- drm_radeon_prim_t *prim; + drm_radeon_prim_t *prim; } drm_radeon_vertex2_t; /* v1.3 - obsoletes drm_radeon_vertex2 -@@ -624,15 +656,15 @@ typedef struct drm_radeon_vertex2 { +@@ -624,15 +654,15 @@ typedef struct drm_radeon_vertex2 { */ typedef struct drm_radeon_cmd_buffer { int bufsz; -- char __user *buf; +- char *buf; + char *buf; int nbox; -- struct drm_clip_rect __user *boxes; +- struct drm_clip_rect *boxes; + struct drm_clip_rect *boxes; } drm_radeon_cmd_buffer_t; typedef struct drm_radeon_tex_image { unsigned int x, y; /* Blit coordinates */ unsigned int width, height; -- const void __user *data; +- const void *data; + const void *data; } drm_radeon_tex_image_t; typedef struct drm_radeon_texture { -@@ -641,11 +673,11 @@ typedef struct drm_radeon_texture { +@@ -641,11 +671,11 @@ typedef struct drm_radeon_texture { int format; int width; /* Texture image coordinates */ int height; -- drm_radeon_tex_image_t __user *image; +- drm_radeon_tex_image_t *image; + drm_radeon_tex_image_t *image; } drm_radeon_texture_t; typedef struct drm_radeon_stipple { -- unsigned int __user *mask; +- unsigned int *mask; + unsigned int *mask; } drm_radeon_stipple_t; typedef struct drm_radeon_indirect { -@@ -655,9 +687,6 @@ typedef struct drm_radeon_indirect { +@@ -655,9 +685,6 @@ typedef struct drm_radeon_indirect { int discard; } drm_radeon_indirect_t; @@ -5715,7 +5862,7 @@ index 66cefb7..af7d382 100644 /* enum for card type parameters */ #define RADEON_CARD_PCI 0 #define RADEON_CARD_AGP 1 -@@ -683,10 +712,11 @@ typedef struct drm_radeon_indirect { +@@ -683,10 +710,11 @@ typedef struct drm_radeon_indirect { #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ @@ -5723,30 +5870,30 @@ index 66cefb7..af7d382 100644 typedef struct drm_radeon_getparam { int param; -- void __user *value; +- void *value; + void *value; } drm_radeon_getparam_t; /* 1.6: Set up a memory manager for regions of shared memory: -@@ -698,7 +728,7 @@ typedef struct drm_radeon_mem_alloc { +@@ -698,7 +726,7 @@ typedef struct drm_radeon_mem_alloc { int region; int alignment; int size; -- int __user *region_offset; /* offset from start of fb or GART */ +- int *region_offset; /* offset from start of fb or GART */ + int *region_offset; /* offset from start of fb or GART */ } drm_radeon_mem_alloc_t; typedef struct drm_radeon_mem_free { -@@ -715,7 +745,7 @@ typedef struct drm_radeon_mem_init_heap { +@@ -715,7 +743,7 @@ typedef struct drm_radeon_mem_init_heap { /* 1.6: Userspace can request & wait on irq's: */ typedef struct drm_radeon_irq_emit { -- int __user *irq_seq; +- int *irq_seq; + int *irq_seq; } drm_radeon_irq_emit_t; typedef struct drm_radeon_irq_wait { -@@ -734,10 +764,10 @@ typedef struct drm_radeon_setparam { +@@ -734,10 +762,10 @@ typedef struct drm_radeon_setparam { #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ @@ -5758,7 +5905,7 @@ index 66cefb7..af7d382 100644 /* 1.14: Clients can allocate/free a surface */ typedef struct drm_radeon_surface_alloc { -@@ -753,4 +783,114 @@ typedef struct drm_radeon_surface_free { +@@ -753,4 +781,106 @@ typedef struct drm_radeon_surface_free { #define DRM_RADEON_VBLANK_CRTC1 1 #define DRM_RADEON_VBLANK_CRTC2 2 @@ -5847,16 +5994,8 @@ index 66cefb7..af7d382 100644 +/* New interface which obsolete all previous interface. + */ + -+ -+struct drm_radeon_cs { -+ uint32_t dwords; -+ uint32_t cs_id; -+ uint64_t packets; -+}; -+ +#define RADEON_CHUNK_ID_RELOCS 0x01 +#define RADEON_CHUNK_ID_IB 0x02 -+#define RADEON_CHUNK_ID_OLD 0xff + +struct drm_radeon_cs_chunk { + uint32_t chunk_id; @@ -5864,7 +6003,7 @@ index 66cefb7..af7d382 100644 + uint64_t chunk_data; +}; + -+struct drm_radeon_cs2 { ++struct drm_radeon_cs { + uint32_t num_chunks; + uint32_t cs_id; + uint64_t chunks; /* this points to uint64_t * which point to @@ -5874,48 +6013,366 @@ index 66cefb7..af7d382 100644 + #endif diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 0f86fdd..4736c27 100644 +index c4bc1bb..22b3147 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c -@@ -43,7 +43,11 @@ +@@ -1,33 +1,33 @@ + /* +- * Copyright 2005 Eric Anholt +- * Copyright 2005 Benjamin Herrenschmidt +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- * +- * Authors: +- * Eric Anholt +- * Zack Rusin +- * Benjamin Herrenschmidt +- * +- */ ++* Copyright 2005 Eric Anholt ++* Copyright 2005 Benjamin Herrenschmidt ++* All Rights Reserved. ++* ++* Permission is hereby granted, free of charge, to any person obtaining a ++* copy of this software and associated documentation files (the "Software"), ++* to deal in the Software without restriction, including without limitation ++* the rights to use, copy, modify, merge, publish, distribute, sublicense, ++* and/or sell copies of the Software, and to permit persons to whom the ++* Software is furnished to do so, subject to the following conditions: ++* ++* The above copyright notice and this permission notice (including the next ++* paragraph) shall be included in all copies or substantial portions of the ++* Software. ++* ++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++* SOFTWARE. ++* ++* Authors: ++* Eric Anholt ++* Zack Rusin ++* Benjamin Herrenschmidt ++* ++*/ + + #ifdef HAVE_CONFIG_H + #include "config.h" +@@ -43,11 +43,15 @@ #include "radeon_version.h" #include "xf86.h" +#include "radeon_bufmgr_gem.h" - -+#define RADEON_PIXMAP_IS_FRONTBUFFER 1 + ++#define RADEON_PIXMAP_IS_FRONTBUFFER 1 + +/* quick hacks lolz */ /***********************************************************************/ #define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86Screens[pScr->myNum]; \ -@@ -181,14 +185,23 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - uint32_t pitch, offset; - int bpp; -+ struct radeon_exa_pixmap_priv *driver_priv; +- RADEONInfoPtr info = RADEONPTR(pScrn) ++RADEONInfoPtr info = RADEONPTR(pScrn) + + #define RADEON_TRACE_FALL 0 + #define RADEON_TRACE_DRAW 0 +@@ -55,9 +59,9 @@ + #if RADEON_TRACE_FALL + #define RADEON_FALLBACK(x) \ + do { \ +- ErrorF("%s: ", __FUNCTION__); \ +- ErrorF x; \ +- return FALSE; \ ++ErrorF("%s: ", __FUNCTION__); \ ++ErrorF x; \ ++return FALSE; \ + } while (0) + #else + #define RADEON_FALLBACK(x) return FALSE +@@ -70,257 +74,386 @@ do { \ + #endif + + static struct { +- int rop; +- int pattern; ++int rop; ++int pattern; + } RADEON_ROP[] = { +- { RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */ +- { RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */ +- { RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */ +- { RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */ +- { RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */ +- { RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */ +- { RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */ +- { RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */ +- { RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */ +- { RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */ +- { RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */ +- { RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */ +- { RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */ +- { RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */ +- { RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */ +- { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ ++{ RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */ ++{ RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */ ++{ RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */ ++{ RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */ ++{ RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */ ++{ RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */ ++{ RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */ ++{ RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */ ++{ RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */ ++{ RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */ ++{ RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */ ++{ RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */ ++{ RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */ ++{ RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */ ++{ RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */ ++{ RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ + }; + + /* Compute log base 2 of val. */ + static __inline__ int + RADEONLog2(int val) + { +- int bits; ++int bits; + #if (defined __i386__ || defined __x86_64__) && (defined __GNUC__) +- __asm volatile("bsrl %1, %0" +- : "=r" (bits) +- : "c" (val) +- ); +- return bits; ++__asm volatile("bsrl %1, %0" ++ : "=r" (bits) ++ : "c" (val) ++); ++return bits; + #else +- for (bits = 0; val != 0; val >>= 1, ++bits) +- ; +- return bits - 1; ++for (bits = 0; val != 0; val >>= 1, ++bits) ++ ; ++return bits - 1; + #endif + } + + static __inline__ uint32_t F_TO_DW(float val) + { +- union { +- float f; +- uint32_t l; +- } tmp; +- tmp.f = val; +- return tmp.l; ++union { ++float f; ++uint32_t l; ++} tmp; ++tmp.f = val; ++return tmp.l; + } + + /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we +- * require src and dest datatypes to be equal. +- */ ++* require src and dest datatypes to be equal. ++*/ + Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type) + { +- switch (bpp) { +- case 8: +- *type = ATI_DATATYPE_CI8; +- return TRUE; +- case 16: +- *type = ATI_DATATYPE_RGB565; +- return TRUE; +- case 24: +- *type = ATI_DATATYPE_CI8; +- return TRUE; +- case 32: +- *type = ATI_DATATYPE_ARGB8888; +- return TRUE; +- default: +- RADEON_FALLBACK(("Unsupported bpp: %d\n", bpp)); +- return FALSE; +- } ++switch (bpp) { ++case 8: ++ *type = ATI_DATATYPE_CI8; ++ return TRUE; ++case 16: ++ *type = ATI_DATATYPE_RGB565; ++ return TRUE; ++case 24: ++ *type = ATI_DATATYPE_CI8; ++ return TRUE; ++case 32: ++ *type = ATI_DATATYPE_ARGB8888; ++ return TRUE; ++default: ++ RADEON_FALLBACK(("Unsupported bpp: %d\n", bpp)); ++ return FALSE; ++} + } - bpp = pPix->drawable.bitsPerPixel; - if (bpp == 24) - bpp = 8; + static Bool RADEONPixmapIsColortiled(PixmapPtr pPix) + { +- RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- +- /* This doesn't account for the back buffer, which we may want to wrap in +- * a pixmap at some point for the purposes of DRI buffer moves. +- */ +- if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0) +- return TRUE; +- else +- return FALSE; ++RINFO_FROM_SCREEN(pPix->drawable.pScreen); ++ ++/* This doesn't account for the back buffer, which we may want to wrap in ++* a pixmap at some point for the purposes of DRI buffer moves. ++*/ ++if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0) ++return TRUE; ++else ++return FALSE; + } + + static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset, +- unsigned int offset, unsigned int pitch) ++ unsigned int offset, unsigned int pitch) + { +- RINFO_FROM_SCREEN(pPix->drawable.pScreen); ++RINFO_FROM_SCREEN(pPix->drawable.pScreen); + +- if (pitch > 16320 || pitch % info->accel_state->exa->pixmapPitchAlign != 0) +- RADEON_FALLBACK(("Bad pitch 0x%08x\n", pitch)); ++if (pitch > 16320 || pitch % info->accel_state->exa->pixmapPitchAlign != 0) ++ RADEON_FALLBACK(("Bad pitch 0x%08x\n", pitch)); + +- if (offset % info->accel_state->exa->pixmapOffsetAlign != 0) +- RADEON_FALLBACK(("Bad offset 0x%08x\n", offset)); ++if (offset % info->accel_state->exa->pixmapOffsetAlign != 0) ++ RADEON_FALLBACK(("Bad offset 0x%08x\n", offset)); + +- pitch = pitch >> 6; +- *pitch_offset = (pitch << 22) | (offset >> 10); ++pitch = pitch >> 6; ++*pitch_offset = (pitch << 22) | (offset >> 10); + +- /* If it's the front buffer, we've got to note that it's tiled? */ +- if (RADEONPixmapIsColortiled(pPix)) +- *pitch_offset |= RADEON_DST_TILE_MACRO; +- return TRUE; ++/* If it's the front buffer, we've got to note that it's tiled? */ ++if (RADEONPixmapIsColortiled(pPix)) ++ *pitch_offset |= RADEON_DST_TILE_MACRO; ++return TRUE; + } + Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) + { +- RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- uint32_t pitch, offset; +- int bpp; +- +- bpp = pPix->drawable.bitsPerPixel; +- if (bpp == 24) +- bpp = 8; +- - offset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; - pitch = exaGetPixmapPitch(pPix); ++RINFO_FROM_SCREEN(pPix->drawable.pScreen); ++uint32_t pitch, offset; ++int bpp; ++struct radeon_exa_pixmap_priv *driver_priv; ++ ++bpp = pPix->drawable.bitsPerPixel; ++if (bpp == 24) ++ bpp = 8; ++ ++ ++/* validate the pixmap somewhere */ ++if (info->new_cs) ++ offset = 0; ++else { ++ offset = exaGetPixmapOffset(pPix); ++ offset += info->fbLocation + pScrn->fbOffset; ++} ++pitch = exaGetPixmapPitch(pPix); -+ /* validate the pixmap somewhere */ -+ if (info->new_cs) -+ offset = 0; -+ else { -+ -+ offset = exaGetPixmapOffset(pPix); -+ -+ offset += info->fbLocation + pScrn->fbOffset; -+ } -+ pitch = exaGetPixmapPitch(pPix); - return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); +- return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); ++return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); } -@@ -196,6 +209,8 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) + /* +- * Used for vblank render stalling. +- * Ideally we'd have one pixmap per crtc. +- * syncing per-blit is unrealistic so, +- * we sync to whichever crtc has a larger area. +- */ ++* Used for vblank render stalling. ++* Ideally we'd have one pixmap per crtc. ++* syncing per-blit is unrealistic so, ++* we sync to whichever crtc has a larger area. ++*/ + int RADEONBiggerCrtcArea(PixmapPtr pPix) + { +- ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; +- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); +- int c, crtc_num = -1, area = 0; ++ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; ++xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++int c, crtc_num = -1, area = 0; + +- for (c = 0; c < xf86_config->num_crtc; c++) { +- xf86CrtcPtr crtc = xf86_config->crtc[c]; ++for (c = 0; c < xf86_config->num_crtc; c++) { ++xf86CrtcPtr crtc = xf86_config->crtc[c]; + +- if (!crtc->enabled) +- continue; ++if (!crtc->enabled) ++ continue; + +- if ((crtc->mode.HDisplay * crtc->mode.VDisplay) > area) { +- area = crtc->mode.HDisplay * crtc->mode.VDisplay; +- crtc_num = c; +- } +- } ++if ((crtc->mode.HDisplay * crtc->mode.VDisplay) > area) { ++ area = crtc->mode.HDisplay * crtc->mode.VDisplay; ++ crtc_num = c; ++} ++} + +- return crtc_num; ++return crtc_num; + } + + #if X_BYTE_ORDER == X_BIG_ENDIAN static unsigned long swapper_surfaces[3]; @@ -5923,206 +6380,307 @@ index 0f86fdd..4736c27 100644 + static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -@@ -203,7 +218,31 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) - uint32_t offset = exaGetPixmapOffset(pPix); - int bpp, soff; - uint32_t size, flags; -+ struct radeon_exa_pixmap_priv *driver_priv; -+ -+ driver_priv = exaGetPixmapDriverPrivate(pPix); -+ if (driver_priv) { +- RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- unsigned char *RADEONMMIO = info->MMIO; +- uint32_t offset = exaGetPixmapOffset(pPix); +- int bpp, soff; +- uint32_t size, flags; +- +- /* Front buffer is always set with proper swappers */ +- if (offset == 0) +- return TRUE; +- +- /* If same bpp as front buffer, just do nothing as the main +- * swappers will apply +- */ +- bpp = pPix->drawable.bitsPerPixel; +- if (bpp == pScrn->bitsPerPixel) +- return TRUE; +- +- /* We need to setup a separate swapper, let's request a +- * surface. We need to align the size first +- */ +- size = exaGetPixmapSize(pPix); +- size = (size + RADEON_BUFFER_ALIGN) & ~(RADEON_BUFFER_ALIGN); +- +- /* Set surface to tiling disabled with appropriate swapper */ +- switch (bpp) { +- case 16: +- flags = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; +- break; +- case 32: +- flags = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; +- break; +- default: +- flags = 0; ++RINFO_FROM_SCREEN(pPix->drawable.pScreen); ++unsigned char *RADEONMMIO = info->MMIO; ++uint32_t offset = exaGetPixmapOffset(pPix); ++int bpp, soff; ++uint32_t size, flags; ++struct radeon_exa_pixmap_priv *driver_priv; ++ ++driver_priv = exaGetPixmapDriverPrivate(pPix); ++if (driver_priv) { ++ ++if (driver_priv->bo) { ++ int ret; + -+ if (driver_priv->bo) { -+ int ret; ++ if (radeon_bufmgr_gem_has_references(driver_priv->bo)) ++ RADEONCPFlushIndirect(pScrn, 0); + -+ if (radeon_bufmgr_gem_has_references(driver_priv->bo)) -+ RADEONCPFlushIndirect(pScrn, 0); ++ radeon_bufmgr_gem_wait_rendering(driver_priv->bo); + -+ radeon_bufmgr_gem_wait_rendering(driver_priv->bo); ++ /* flush IB */ ++ ret = dri_bo_map(driver_priv->bo, 1); ++ if (ret) { ++ FatalError("failed to map pixmap %d\n", ret); ++ return FALSE; + } + -+ /* flush IB */ -+ ret = dri_bo_map(driver_priv->bo, 1); -+ if (ret) { -+ FatalError("failed to map pixmap %d\n", ret); -+ return FALSE; -+ } ++ pPix->devPrivate.ptr = driver_priv->bo->virtual; ++} ++} + -+ pPix->devPrivate.ptr = driver_priv->bo->virtual; -+ } -+ } - +#if X_BYTE_ORDER == X_BIG_ENDIAN - /* Front buffer is always set with proper swappers */ - if (offset == 0) - return TRUE; -@@ -259,6 +298,7 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) - OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset); - OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1); - swapper_surfaces[index] = offset; ++/* Front buffer is always set with proper swappers */ ++if (offset == 0) ++return TRUE; ++ ++/* If same bpp as front buffer, just do nothing as the main ++* swappers will apply ++*/ ++bpp = pPix->drawable.bitsPerPixel; ++if (bpp == pScrn->bitsPerPixel) ++return TRUE; ++ ++/* We need to setup a separate swapper, let's request a ++* surface. We need to align the size first ++*/ ++size = exaGetPixmapSize(pPix); ++size = (size + RADEON_BUFFER_ALIGN) & ~(RADEON_BUFFER_ALIGN); ++ ++/* Set surface to tiling disabled with appropriate swapper */ ++switch (bpp) { ++case 16: ++flags = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; ++break; ++case 32: ++flags = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; ++break; ++default: ++flags = 0; ++} + #if defined(XF86DRI) +- if (info->directRenderingEnabled && info->allowColorTiling) { +- struct drm_radeon_surface_alloc drmsurfalloc; +- int rc; +- +- drmsurfalloc.address = offset; +- drmsurfalloc.size = size; +- drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */ +- +- rc = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, +- &drmsurfalloc, sizeof(drmsurfalloc)); +- if (rc < 0) { +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "drm: could not allocate surface for access" +- " swapper, err: %d!\n", rc); +- return FALSE; +- } +- swapper_surfaces[index] = offset; ++if (info->directRenderingEnabled && info->allowColorTiling) { ++struct drm_radeon_surface_alloc drmsurfalloc; ++int rc; ++ ++drmsurfalloc.address = offset; ++drmsurfalloc.size = size; ++drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */ ++ ++rc = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, ++ &drmsurfalloc, sizeof(drmsurfalloc)); ++if (rc < 0) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "drm: could not allocate surface for access" ++ " swapper, err: %d!\n", rc); ++ return FALSE; ++} ++swapper_surfaces[index] = offset; + +- return TRUE; +- } ++return TRUE; ++} + #endif +- soff = (index + 1) * 0x10; +- OUTREG(RADEON_SURFACE0_INFO + soff, flags); +- OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset); +- OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1); +- swapper_surfaces[index] = offset; +- return TRUE; ++soff = (index + 1) * 0x10; ++OUTREG(RADEON_SURFACE0_INFO + soff, flags); ++OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset); ++OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1); ++swapper_surfaces[index] = offset; +#endif - return TRUE; ++return TRUE; } -@@ -268,7 +308,17 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) - unsigned char *RADEONMMIO = info->MMIO; - uint32_t offset = exaGetPixmapOffset(pPix); - int soff; -+ struct radeon_exa_pixmap_priv *driver_priv; - -+ driver_priv = exaGetPixmapDriverPrivate(pPix); -+ -+ if (driver_priv) { -+ dri_bo_unmap(driver_priv->bo); -+ pPix->devPrivate.ptr = NULL; -+ } + static void RADEONFinishAccess(PixmapPtr pPix, int index) + { +- RINFO_FROM_SCREEN(pPix->drawable.pScreen); +- unsigned char *RADEONMMIO = info->MMIO; +- uint32_t offset = exaGetPixmapOffset(pPix); +- int soff; ++RINFO_FROM_SCREEN(pPix->drawable.pScreen); ++unsigned char *RADEONMMIO = info->MMIO; ++uint32_t offset = exaGetPixmapOffset(pPix); ++int soff; ++struct radeon_exa_pixmap_priv *driver_priv; ++ ++driver_priv = exaGetPixmapDriverPrivate(pPix); + +- /* Front buffer is always set with proper swappers */ +- if (offset == 0) +- return; ++if (driver_priv) { ++dri_bo_unmap(driver_priv->bo); ++pPix->devPrivate.ptr = NULL; ++} + + +#if X_BYTE_ORDER == X_BIG_ENDIAN - /* Front buffer is always set with proper swappers */ - if (offset == 0) - return; -@@ -291,14 +341,100 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) - OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); - OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); - swapper_surfaces[index] = 0; ++/* Front buffer is always set with proper swappers */ ++if (offset == 0) ++return; + +- if (swapper_surfaces[index] == 0) +- return; ++if (swapper_surfaces[index] == 0) ++return; + #if defined(XF86DRI) +- if (info->directRenderingEnabled && info->allowColorTiling) { +- struct drm_radeon_surface_free drmsurffree; +- +- drmsurffree.address = offset; +- drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, +- &drmsurffree, sizeof(drmsurffree)); +- swapper_surfaces[index] = 0; +- return; +- } ++if (info->directRenderingEnabled && info->allowColorTiling) { ++struct drm_radeon_surface_free drmsurffree; ++ ++drmsurffree.address = offset; ++drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, ++ &drmsurffree, sizeof(drmsurffree)); ++swapper_surfaces[index] = 0; ++return; ++} + #endif +- soff = (index + 1) * 0x10; +- OUTREG(RADEON_SURFACE0_INFO + soff, 0); +- OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); +- OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); +- swapper_surfaces[index] = 0; ++soff = (index + 1) * 0x10; ++OUTREG(RADEON_SURFACE0_INFO + soff, 0); ++OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); ++OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); ++swapper_surfaces[index] = 0; +#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ } -#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ +void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align) +{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct radeon_exa_pixmap_priv *new_priv; -+ -+ new_priv = xcalloc(1, sizeof(struct radeon_exa_pixmap_priv)); -+ if (!new_priv) -+ return NULL; -+ -+ if (size == 0) -+ return new_priv; ++ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++RADEONInfoPtr info = RADEONPTR(pScrn); ++struct radeon_exa_pixmap_priv *new_priv; ++ ++new_priv = xcalloc(1, sizeof(struct radeon_exa_pixmap_priv)); ++if (!new_priv) ++return NULL; ++ ++if (size == 0) ++return new_priv; ++ ++new_priv->bo = dri_bo_alloc(info->bufmgr, "exa pixmap", size, ++ align, 0); ++if (!new_priv->bo) { ++xfree(new_priv); ++ErrorF("Failed to alloc memory\n"); ++return NULL; ++} + -+ new_priv->bo = dri_bo_alloc(info->bufmgr, "exa pixmap", size, -+ align, 0); -+ if (!new_priv->bo) { -+ xfree(new_priv); -+ ErrorF("Failed to alloc memory\n"); -+ return NULL; -+ } -+ -+ return new_priv; ++return new_priv; + +} + +static void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv) +{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct radeon_exa_pixmap_priv *driver_priv = driverPriv; -+ int ret; ++ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++RADEONInfoPtr info = RADEONPTR(pScrn); ++struct radeon_exa_pixmap_priv *driver_priv = driverPriv; ++int ret; + -+ dri_bo_unreference(driver_priv->bo); -+ xfree(driverPriv); ++dri_bo_unreference(driver_priv->bo); ++xfree(driverPriv); +} + +static Bool RADEONEXAModifyPixmapHeader(PixmapPtr pPixmap, int width, int height, -+ int depth, int bitsPerPixel, int devKind, -+ pointer pPixData) ++ int depth, int bitsPerPixel, int devKind, ++ pointer pPixData) +{ -+ ScreenPtr pScreen = pPixmap->drawable.pScreen; -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct radeon_exa_pixmap_priv *driver_priv; ++ScreenPtr pScreen = pPixmap->drawable.pScreen; ++ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++RADEONInfoPtr info = RADEONPTR(pScrn); ++struct radeon_exa_pixmap_priv *driver_priv; + -+ driver_priv = exaGetPixmapDriverPrivate(pPixmap); -+ if (!driver_priv) -+ return FALSE; ++driver_priv = exaGetPixmapDriverPrivate(pPixmap); ++if (!driver_priv) ++return FALSE; + + -+ if (info->drm_mode_setting && drmmode_is_rotate_pixmap(pScrn, pPixData, &driver_priv->bo)){ -+ dri_bo_unmap(driver_priv->bo); -+ dri_bo_reference(driver_priv->bo); -+ miModifyPixmapHeader(pPixmap, width, height, depth, -+ bitsPerPixel, devKind, NULL); ++if (info->drm_mode_setting && drmmode_is_rotate_pixmap(pScrn, pPixData, &driver_priv->bo)){ ++dri_bo_unmap(driver_priv->bo); ++dri_bo_reference(driver_priv->bo); ++miModifyPixmapHeader(pPixmap, width, height, depth, ++ bitsPerPixel, devKind, NULL); + -+ return TRUE; -+ } ++return TRUE; ++} + -+ if (pPixData == info->mm.front_buffer->map) { -+ driver_priv->flags |= RADEON_PIXMAP_IS_FRONTBUFFER; ++if (pPixData == info->mm.front_buffer->map) { ++driver_priv->flags |= RADEON_PIXMAP_IS_FRONTBUFFER; + -+ if (info->new_cs) -+ driver_priv->bo = radeon_bo_gem_create_from_name(info->bufmgr, "front", -+ radeon_name_buffer(pScrn, info->mm.front_buffer)); -+ else -+ driver_priv->bo = radeon_bufmgr_exa_create_bo(info->bufmgr, info->mm.front_buffer); ++driver_priv->bo = radeon_bo_gem_create_from_name(info->bufmgr, "front", ++ radeon_name_buffer(pScrn, info->mm.front_buffer)); + -+ miModifyPixmapHeader(pPixmap, width, height, depth, -+ bitsPerPixel, devKind, NULL); -+ return TRUE; -+ } -+ return FALSE; ++miModifyPixmapHeader(pPixmap, width, height, depth, ++ bitsPerPixel, devKind, NULL); ++return TRUE; ++} ++return FALSE; +} + +static Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix) +{ -+ struct radeon_exa_pixmap_priv *driver_priv; ++struct radeon_exa_pixmap_priv *driver_priv; + -+ driver_priv = exaGetPixmapDriverPrivate(pPix); ++driver_priv = exaGetPixmapDriverPrivate(pPix); + -+ if (!driver_priv) -+ return FALSE; -+ if (driver_priv->bo) -+ return TRUE; -+ return FALSE; ++if (!driver_priv) ++return FALSE; ++if (driver_priv->bo) ++return TRUE; ++return FALSE; +} - #define RADEON_SWITCH_TO_2D() \ - do { \ -- uint32_t wait_until = 0; \ -- BEGIN_ACCEL(1); \ -+ uint32_t wait_until = 0; \ - switch (info->accel_state->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \ -@@ -307,15 +443,17 @@ do { \ - case EXA_ENGINEMODE_2D: \ - break; \ - } \ -- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ -- FINISH_ACCEL(); \ -+ if (wait_until) { \ -+ BEGIN_ACCEL(1); \ -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ -+ FINISH_ACCEL(); \ -+ } \ - info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ - } while (0); - - #define RADEON_SWITCH_TO_3D() \ - do { \ -- uint32_t wait_until = 0; \ -- BEGIN_ACCEL(1); \ -+ uint32_t wait_until = 0; \ - switch (info->accel_state->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ -@@ -324,8 +462,11 @@ do { \ - case EXA_ENGINEMODE_3D: \ - break; \ - } \ -- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ -- FINISH_ACCEL(); \ -+ if (wait_until) { \ -+ BEGIN_ACCEL(1); \ -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ -+ FINISH_ACCEL(); \ -+ } \ - info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ - } while (0); - -@@ -338,6 +479,7 @@ do { \ + #define ENTER_DRAW(x) TRACE + #define LEAVE_DRAW(x) TRACE +@@ -331,6 +464,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -6130,7 +6688,7 @@ index 0f86fdd..4736c27 100644 #define FINISH_ACCEL() #ifdef RENDER -@@ -351,6 +493,7 @@ do { \ +@@ -344,6 +478,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F #undef FINISH_ACCEL @@ -6138,7 +6696,7 @@ index 0f86fdd..4736c27 100644 #ifdef XF86DRI -@@ -361,6 +504,7 @@ do { \ +@@ -354,6 +489,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() @@ -6146,7 +6704,7 @@ index 0f86fdd..4736c27 100644 #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) -@@ -378,6 +522,8 @@ do { \ +@@ -371,6 +507,8 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #endif /* XF86DRI */ @@ -6155,7 +6713,7 @@ index 0f86fdd..4736c27 100644 /* * Once screen->off_screen_base is set, this function * allocates the remaining memory appropriately -@@ -399,122 +545,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -392,122 +530,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) if (info->accel_state->exa == NULL) return FALSE; @@ -6385,7 +6943,7 @@ index 0f86fdd..4736c27 100644 return TRUE; } -@@ -527,10 +677,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr); +@@ -520,10 +662,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr); unsigned long long RADEONTexOffsetStart(PixmapPtr pPix) { @@ -6411,10 +6969,10 @@ index 0f86fdd..4736c27 100644 } #endif diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 62224d0..fe104c4 100644 +index 55710ff..2ea4fc9 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c -@@ -74,21 +74,71 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker) +@@ -74,21 +74,73 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -6484,10 +7042,12 @@ index 62224d0..fe104c4 100644 + struct radeon_exa_pixmap_priv *driver_priv; + int ret; + int retry_count = 0; ++ struct radeon_space_check bos[1]; ++ int i; ACCEL_PREAMBLE(); TRACE; -@@ -97,25 +147,49 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) +@@ -97,25 +149,58 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) RADEON_FALLBACK(("24bpp unsupported\n")); if (!RADEONGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); @@ -6496,16 +7056,25 @@ index 62224d0..fe104c4 100644 - RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch failed\n")); + RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch failed\n")); + -+ -+ if (info->new_cs) { + retry: -+ driver_priv = exaGetPixmapDriverPrivate(pPix); -+ ret = dri_bufmgr_check_aperture_space(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); -+ if (ret) { ++ if (info->new_cs) { ++ ++ i = 0; ++ driver_priv = exaGetPixmapDriverPrivate(pPix); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) { ++ RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); ++ } ++ if (ret == BUFMGR_SPACE_FLUSH) { + RADEONCPFlushIndirect(pScrn, 1); + retry_count++; + if (retry_count == 2) -+ RADEON_FALLBACK(("Not enough Video RAM\n")); ++ RADEON_FALLBACK(("Not enough Video RAM for src\n")); + goto retry; + } + } @@ -6552,18 +7121,23 @@ index 62224d0..fe104c4 100644 return TRUE; } -@@ -148,8 +222,10 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) +@@ -145,6 +230,7 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) + + TRACE; + ++ info->state_2d.op = 0; + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); +@@ -152,6 +238,7 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) FINISH_ACCEL(); -+ info->state_2d.op = 0; } + void FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, uint32_t dst_pitch_offset, uint32_t datatype, int rop, -@@ -160,23 +236,28 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, +@@ -162,23 +249,28 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, RADEON_SWITCH_TO_2D(); @@ -6609,7 +7183,7 @@ index 62224d0..fe104c4 100644 } static Bool -@@ -187,7 +268,9 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -189,9 +281,46 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, { RINFO_FROM_SCREEN(pDst->drawable.pScreen); uint32_t datatype, src_pitch_offset, dst_pitch_offset; @@ -6617,10 +7191,47 @@ index 62224d0..fe104c4 100644 + struct radeon_exa_pixmap_priv *driver_priv; + int ret; + int retry_count = 0; ++ struct radeon_space_check bos[2]; ++ int i; TRACE; ++retry: ++ if (info->new_cs) { ++ ++ i = 0; ++ driver_priv = exaGetPixmapDriverPrivate(pSrc); ++ info->state_2d.src_bo = driver_priv->bo; ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ ++ ++ driver_priv = exaGetPixmapDriverPrivate(pDst); ++ info->state_2d.dst_bo = driver_priv->bo; ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) { ++ RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); ++ } ++ if (ret == BUFMGR_SPACE_FLUSH) { ++ RADEONCPFlushIndirect(pScrn, 1); ++ retry_count++; ++ if (retry_count == 2) ++ RADEON_FALLBACK(("Not enough Video RAM for src\n")); ++ goto retry; ++ } ++ } ++ ++ info->accel_state->xdir = xdir; -@@ -197,10 +280,40 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, + info->accel_state->ydir = ydir; + +@@ -199,10 +328,11 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, RADEON_FALLBACK(("24bpp unsupported")); if (!RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); @@ -6631,48 +7242,18 @@ index 62224d0..fe104c4 100644 if (!RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset)) - RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch dest failed\n")); + RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch dest failed\n")); -+ -+ retry: -+ if (info->new_cs) { -+ driver_priv = exaGetPixmapDriverPrivate(pSrc); -+ if (driver_priv) { -+ ret = dri_bufmgr_check_aperture_space(driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); -+ if (ret) { -+ RADEONCPFlushIndirect(pScrn, 1); -+ retry_count++; -+ if (retry_count == 2) -+ RADEON_FALLBACK(("Not enough Video RAM\n")); -+ goto retry; -+ } -+ info->state_2d.src_bo = driver_priv->bo; -+ -+ driver_priv = exaGetPixmapDriverPrivate(pDst); -+ if (driver_priv) { -+ ret = dri_bufmgr_check_aperture_space(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); -+ if (ret) { -+ RADEONCPFlushIndirect(pScrn, 1); -+ retry_count++; -+ if (retry_count == 2) -+ RADEON_FALLBACK(("Not enough Video RAM\n")); -+ goto retry; -+ } -+ info->state_2d.dst_bo = driver_priv->bo; -+ } -+ } -+ } FUNC_NAME(RADEONDoPrepareCopy)(pScrn, src_pitch_offset, dst_pitch_offset, datatype, rop, planemask); -@@ -250,6 +363,8 @@ FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); -+ -+ info->state_2d.op = 0; - } +@@ -249,6 +379,7 @@ FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) - static Bool -@@ -260,6 +375,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + TRACE; + ++ info->state_2d.op = 0; + BEGIN_ACCEL(2); + OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, +@@ -264,6 +395,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, uint8_t *dst = info->FB + exaGetPixmapOffset(pDst); unsigned int dst_pitch = exaGetPixmapPitch(pDst); unsigned int bpp = pDst->drawable.bitsPerPixel; @@ -6681,11 +7262,11 @@ index 62224d0..fe104c4 100644 #ifdef ACCEL_CP unsigned int hpass; uint32_t buf_pitch, dst_pitch_off; -@@ -276,10 +393,45 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -280,10 +413,50 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, if (bpp < 8) return FALSE; -+ if (info->new_cs) ++ if (info->new_cs) + dst = info->mm.front_buffer->map + exaGetPixmapOffset(pDst); + #ifdef ACCEL_CP @@ -6703,6 +7284,11 @@ index 62224d0..fe104c4 100644 + return FALSE; + + ++ if (radeon_bufmgr_gem_has_references(driver_priv->bo)) ++ RADEONCPFlushIndirect(pScrn, 0); ++ ++ radeon_bufmgr_gem_wait_rendering(driver_priv->bo); ++ + /* use pwrites - maybe require some sort of fallback */ + bo_width = w * (bpp / 8); + offset = (x * bpp / 8) + (y * dst_pitch); @@ -6730,7 +7316,7 @@ index 62224d0..fe104c4 100644 int cpp = bpp / 8; ACCEL_PREAMBLE(); -@@ -294,9 +446,10 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -301,9 +474,10 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, exaMarkSync(pDst->drawable.pScreen); return TRUE; @@ -6743,7 +7329,7 @@ index 62224d0..fe104c4 100644 /* Do we need that sync here ? probably not .... */ exaWaitSync(pDst->drawable.pScreen); -@@ -335,14 +488,20 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -342,14 +516,20 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, #ifdef ACCEL_CP /* Emit blit with arbitrary source and destination offsets and pitches */ static void @@ -6766,7 +7352,7 @@ index 62224d0..fe104c4 100644 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | -@@ -353,8 +512,14 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, +@@ -360,8 +540,14 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, RADEON_DP_SRC_SOURCE_MEMORY | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); @@ -6781,12 +7367,45 @@ index 62224d0..fe104c4 100644 OUT_ACCEL_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX); OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); -@@ -365,6 +530,107 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, +@@ -372,6 +558,174 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); FINISH_ACCEL(); } + +static Bool ++RADEON_DFS_CS2(PixmapPtr pSrc, int x, int y, int w, int h, ++ char *dst, int dst_pitch) ++{ ++ RINFO_FROM_SCREEN(pSrc->drawable.pScreen); ++ struct radeon_exa_pixmap_priv *driver_priv; ++ int src_pitch = exaGetPixmapPitch(pSrc); ++ int bpp = pSrc->drawable.bitsPerPixel; ++ uint32_t src_offset; ++ /* force into GTT? */ ++ ++ if (!info->accelDFS) ++ return FALSE; ++ ++ driver_priv = exaGetPixmapDriverPrivate(pSrc); ++ ++ radeon_bufmgr_gem_force_gtt(driver_priv->bo); ++ radeon_bufmgr_gem_wait_rendering(driver_priv->bo); ++ ++ dri_bo_map(driver_priv->bo, 0); ++ ++ src_offset = (x * bpp / 8) + (y * src_pitch); ++ w *= bpp / 8; ++ ++ while (h--) { ++ memcpy(dst, driver_priv->bo->virtual + src_offset, w); ++ src_offset += src_pitch; ++ dst += dst_pitch; ++ } ++ dri_bo_unmap(driver_priv->bo); ++ return TRUE; ++} ++ ++static Bool +RADEON_DFS_CS(PixmapPtr pSrc, int x, int y, int w, int h, + char *dst, int dst_pitch) +{ @@ -6801,12 +7420,21 @@ index 62224d0..fe104c4 100644 + int src_pitch = exaGetPixmapPitch(pSrc); + dri_bo *cur_scratch; + uint32_t src_pitch_offset; -+ ++ struct radeon_space_check bos[3]; ++ int retry_count; ++ + if (!info->accelDFS) + return FALSE; + + driver_priv = exaGetPixmapDriverPrivate(pSrc); + ++ if (radeon_bufmgr_gem_has_references(driver_priv->bo)) ++ RADEONCPFlushIndirect(pScrn, 0); ++ ++ /* if we haven't put this buffer in VRAM then just force gtt and memcpy from it */ ++ if (!radeon_bufmgr_gem_in_vram(driver_priv->bo)) { ++ return RADEON_DFS_CS2(pSrc, x, y, w, h, dst, dst_pitch); ++ } + RADEONGetDatatypeBpp(bpp, &datatype); + scratch_bo[0] = scratch_bo[1] = NULL; + for (i = 0; i < 2; i++) { @@ -6814,7 +7442,32 @@ index 62224d0..fe104c4 100644 + if (!scratch_bo[i]) + goto fail; + } -+ ++ ++retry: ++ i = 0; ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ bos[i].buf = scratch_bo[0]; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_GTT; ++ i++; ++ bos[i].buf = scratch_bo[1]; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_GTT; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) ++ goto fail; ++ if (ret == BUFMGR_SPACE_FLUSH) { ++ RADEONCPFlushIndirect(pScrn, 1); ++ retry_count++; ++ if (retry_count == 2) ++ goto fail; ++ goto retry; ++ } + + /* we want to blit from the BO to the scratch and memcpy out of the scratch */ + { @@ -6889,13 +7542,15 @@ index 62224d0..fe104c4 100644 #endif static Bool -@@ -389,12 +655,16 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -396,12 +750,18 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, TRACE; #ifdef ACCEL_CP + -+ if (info->new_cs) ++ if (info->new_cs) { + return RADEON_DFS_CS(pSrc, x, y, w, h, dst, dst_pitch); ++ } ++ /* * Try to accelerate download. Use an indirect buffer as scratch space, * blitting the bits to one half while copying them out of the other one and @@ -6907,7 +7562,7 @@ index 62224d0..fe104c4 100644 RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset) && (scratch = RADEONCPGetBuffer(pScrn))) { -@@ -409,7 +679,8 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -416,7 +776,8 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, RADEON_SWITCH_TO_2D(); /* Kick the first blit as early as possible */ @@ -6917,7 +7572,7 @@ index 62224d0..fe104c4 100644 x, y, 0, 0, w, hpass); FLUSH_RING(); -@@ -436,7 +707,8 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -443,7 +804,8 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, /* Prepare next blit if anything's left */ if (hpass) { scratch_off = scratch->total/2 - scratch_off; @@ -6927,7 +7582,7 @@ index 62224d0..fe104c4 100644 x, y, 0, 0, w, hpass); } -@@ -543,14 +815,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -550,14 +912,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->accel_state->exa->UploadToScreen = FUNC_NAME(RADEONUploadToScreen); info->accel_state->exa->DownloadFromScreen = FUNC_NAME(RADEONDownloadFromScreen); @@ -6948,7 +7603,7 @@ index 62224d0..fe104c4 100644 #ifdef RENDER if (info->RenderAccel) { -@@ -560,7 +835,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -567,7 +932,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) else if (IS_R300_3D || IS_R500_3D) { if ((info->ChipFamily < CHIP_FAMILY_RS400) #ifdef XF86DRI @@ -6957,7 +7612,7 @@ index 62224d0..fe104c4 100644 #endif ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " -@@ -595,6 +870,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -602,6 +967,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) } #endif @@ -6975,10 +7630,21 @@ index 62224d0..fe104c4 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 97199ae..c19ca0b 100644 +index 55e55be..b8e3095 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c -@@ -355,12 +355,14 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -54,6 +54,10 @@ + #define ONLY_ONCE + #endif + ++#define VTX_COUNT_MASK 6 ++#define VTX_COUNT 4 ++ ++ + /* Only include the following (generic) bits once. */ + #ifdef ONLY_ONCE + +@@ -355,12 +359,14 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, Bool repeat = pPict->repeat && !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y)); int i; @@ -6995,7 +7661,7 @@ index 97199ae..c19ca0b 100644 RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset)); if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -@@ -402,23 +404,43 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -402,23 +408,43 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, if (repeat) txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP; @@ -7042,16 +7708,60 @@ index 97199ae..c19ca0b 100644 } FINISH_ACCEL(); -@@ -523,6 +545,8 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, +@@ -523,10 +549,52 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, uint32_t dst_format, dst_offset, dst_pitch, colorpitch; uint32_t pp_cntl, blendcntl, cblend, ablend; int pixel_shift; + struct radeon_exa_pixmap_priv *driver_priv; + int qwords; ++ int retry_count = 0; ++ struct radeon_space_check bos[3]; ++ int i, ret; ACCEL_PREAMBLE(); TRACE; -@@ -540,15 +564,13 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, + ++ retry: ++ if (info->new_cs) { ++ ++ i = 0; ++ driver_priv = exaGetPixmapDriverPrivate(pSrc); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ ++ if (pMask) { ++ driver_priv = exaGetPixmapDriverPrivate(pMask); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ } ++ ++ driver_priv = exaGetPixmapDriverPrivate(pDst); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) { ++ RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); ++ } ++ if (ret == BUFMGR_SPACE_FLUSH) { ++ RADEONCPFlushIndirect(pScrn, 1); ++ retry_count++; ++ if (retry_count == 2) ++ RADEON_FALLBACK(("Not enough Video RAM for src\n")); ++ goto retry; ++ } ++ } ++ + if (!RADEONGetDestFormat(pDstPicture, &dst_format)) + return FALSE; + +@@ -540,19 +608,18 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, pixel_shift = pDst->drawable.bitsPerPixel >> 4; @@ -7069,13 +7779,16 @@ index 97199ae..c19ca0b 100644 RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset)); if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); -@@ -569,11 +591,19 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, + ++ + if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) + return FALSE; + +@@ -570,10 +637,18 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, + info->accel_state->is_transform[1] = FALSE; } - RADEON_SWITCH_TO_3D(); -- - BEGIN_ACCEL(8); -+ + qwords = info->new_cs ? 9 : 8; + BEGIN_ACCEL(qwords); OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl); @@ -7092,7 +7805,7 @@ index 97199ae..c19ca0b 100644 OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); /* IN operator: Multiply src by mask components or mask alpha. -@@ -669,13 +699,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -669,13 +744,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, Bool repeat = pPict->repeat && !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y)); int i; @@ -7113,7 +7826,7 @@ index 97199ae..c19ca0b 100644 if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -@@ -718,7 +752,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -718,7 +797,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, if (repeat) txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP; @@ -7123,7 +7836,7 @@ index 97199ae..c19ca0b 100644 if (unit == 0) { OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); -@@ -726,7 +761,15 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -726,7 +806,15 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, OUT_ACCEL_REG(R200_PP_TXSIZE_0, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_0, txpitch - 32); @@ -7140,7 +7853,7 @@ index 97199ae..c19ca0b 100644 } else { OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter); OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat); -@@ -734,7 +777,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -734,7 +822,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, OUT_ACCEL_REG(R200_PP_TXSIZE_1, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch - 32); @@ -7159,16 +7872,60 @@ index 97199ae..c19ca0b 100644 } FINISH_ACCEL(); -@@ -823,6 +876,8 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -823,10 +921,52 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, uint32_t dst_format, dst_offset, dst_pitch; uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch; int pixel_shift; + struct radeon_exa_pixmap_priv *driver_priv; + int qwords; ++ int retry_count = 0; ++ struct radeon_space_check bos[3]; ++ int i, ret; ACCEL_PREAMBLE(); TRACE; -@@ -840,13 +895,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, + ++ retry: ++ if (info->new_cs) { ++ ++ i = 0; ++ driver_priv = exaGetPixmapDriverPrivate(pSrc); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ ++ if (pMask) { ++ driver_priv = exaGetPixmapDriverPrivate(pMask); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ } ++ ++ driver_priv = exaGetPixmapDriverPrivate(pDst); ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) { ++ RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); ++ } ++ if (ret == BUFMGR_SPACE_FLUSH) { ++ RADEONCPFlushIndirect(pScrn, 1); ++ retry_count++; ++ if (retry_count == 2) ++ RADEON_FALLBACK(("Not enough Video RAM for src\n")); ++ goto retry; ++ } ++ } ++ + if (!RADEONGetDestFormat(pDstPicture, &dst_format)) + return FALSE; + +@@ -840,13 +980,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, pixel_shift = pDst->drawable.bitsPerPixel >> 4; @@ -7184,9 +7941,9 @@ index 97199ae..c19ca0b 100644 RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset)); if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); -@@ -868,11 +923,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, - - RADEON_SWITCH_TO_3D(); +@@ -868,11 +1008,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, + info->accel_state->is_transform[1] = FALSE; + } - BEGIN_ACCEL(11); + qwords = info->new_cs ? 12 : 11; @@ -7209,7 +7966,37 @@ index 97199ae..c19ca0b 100644 OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); if (pMask) -@@ -999,15 +1065,19 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -941,6 +1092,10 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, + int unit, + Bool is_r500) + { ++ ScreenPtr pScreen = pDstPict->pDrawable->pScreen; ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ + int w = pPict->pDrawable->width; + int h = pPict->pDrawable->height; + int i; +@@ -966,8 +1121,17 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, + RADEON_FALLBACK(("Unsupported picture format 0x%x\n", + (int)pPict->format)); + +- if (!RADEONCheckTexturePOT(pPict, unit == 0)) ++ if (!RADEONCheckTexturePOT(pPict, unit == 0)) { ++ if (info->new_cs) { ++ struct radeon_exa_pixmap_priv *driver_priv; ++ PixmapPtr pPix; ++ ++ pPix = RADEONGetDrawablePixmap(pPict->pDrawable); ++ driver_priv = exaGetPixmapDriverPrivate(pPix); ++ radeon_bufmgr_gem_force_gtt(driver_priv->bo); ++ } + return FALSE; ++ } + + if (pPict->filter != PictFilterNearest && + pPict->filter != PictFilterBilinear) +@@ -999,15 +1163,19 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; int i, pixel_shift; @@ -7232,7 +8019,7 @@ index 97199ae..c19ca0b 100644 if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -@@ -1068,13 +1138,26 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -1068,13 +1236,26 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } @@ -7261,7 +8048,7 @@ index 97199ae..c19ca0b 100644 if (!pPict->repeat) OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); FINISH_ACCEL(); -@@ -1173,6 +1256,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP +@@ -1173,6 +1354,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP return TRUE; } @@ -7269,60 +8056,60 @@ index 97199ae..c19ca0b 100644 #endif /* ONLY_ONCE */ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, -@@ -1184,10 +1268,52 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1184,10 +1366,51 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, uint32_t txenable, colorpitch; uint32_t blendcntl; int pixel_shift; + int qwords, ret; + int retry_count = 0; + struct radeon_exa_pixmap_priv *driver_priv; ++ struct radeon_space_check bos[3]; ++ int i; ACCEL_PREAMBLE(); - +- TRACE; + retry: + if (info->new_cs) { ++ ++ i = 0; + driver_priv = exaGetPixmapDriverPrivate(pSrc); -+ ret = dri_bufmgr_check_aperture_space(driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); -+ if (ret) { -+ RADEONCPFlushIndirect(pScrn, 1); -+ retry_count++; -+ if (retry_count == 2) -+ RADEON_FALLBACK(("Not enough Video RAM\n")); -+ goto retry; -+ } ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; + + if (pMask) { + driver_priv = exaGetPixmapDriverPrivate(pMask); -+ ret = dri_bufmgr_check_aperture_space(driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); -+ if (ret) { -+ RADEONCPFlushIndirect(pScrn, 1); -+ retry_count++; -+ if (retry_count == 2) -+ RADEON_FALLBACK(("Not enough Video RAM\n")); -+ goto retry; -+ } ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; + } + + driver_priv = exaGetPixmapDriverPrivate(pDst); -+ if (driver_priv) { -+ ret = dri_bufmgr_check_aperture_space(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); -+ if (ret) { -+ RADEONCPFlushIndirect(pScrn, 1); -+ retry_count++; -+ if (retry_count == 2) -+ RADEON_FALLBACK(("Not enough Video RAM\n")); -+ goto retry; -+ } ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) { ++ RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); ++ } ++ if (ret == BUFMGR_SPACE_FLUSH) { ++ RADEONCPFlushIndirect(pScrn, 1); ++ retry_count++; ++ if (retry_count == 2) ++ RADEON_FALLBACK(("Not enough Video RAM - this really shouldn't happen\nm")); ++ goto retry; + } + } -+ -+ + - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); + if (!R300GetDestFormat(pDstPicture, &dst_format)) + return FALSE; -@@ -1201,7 +1327,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1198,7 +1421,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, pixel_shift = pDst->drawable.bitsPerPixel >> 4; @@ -7331,7 +8118,7 @@ index 97199ae..c19ca0b 100644 dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; -@@ -1210,7 +1336,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1207,7 +1430,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, colorpitch |= dst_format; @@ -7340,9 +8127,19 @@ index 97199ae..c19ca0b 100644 RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset)); if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); -@@ -1829,9 +1955,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - FINISH_ACCEL(); - } +@@ -1216,6 +1439,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + return FALSE; + + RADEON_SWITCH_TO_3D(); ++ BEGIN_ACCEL(1); ++ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); ++ FINISH_ACCEL(); + + if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0)) + return FALSE; +@@ -1868,9 +2094,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + (8191 << R300_SCISSOR_Y_SHIFT))); + FINISH_ACCEL(); - BEGIN_ACCEL(3); + qwords = info->new_cs ? 4 : 3; @@ -7361,6 +8158,51 @@ index 97199ae..c19ca0b 100644 OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); +@@ -1888,7 +2123,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + return TRUE; + } + +- + #ifdef ACCEL_CP + + #define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ +@@ -2082,9 +2316,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]); + } + +- if (IS_R300_3D || IS_R500_3D) ++ if (IS_R300_3D || IS_R500_3D) { + /* flushing is pipelined, free/finish is not */ + OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); ++ } + + #ifdef ACCEL_CP + ADVANCE_RING(); +@@ -2167,14 +2402,23 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) + + if (IS_R300_3D || IS_R500_3D) { + BEGIN_ACCEL(3); +- OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); + OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xaaaa); + } else + BEGIN_ACCEL(1); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + FINISH_ACCEL(); + + LEAVE_DRAW(0); ++ ++#if 0 ++ /* workaround hang on RS4xx and RS6xx chips */ ++ if(info->ChipFamily == CHIP_FAMILY_RS400 || ++ info->ChipFamily == CHIP_FAMILY_RS480 || ++ info->ChipFamily == CHIP_FAMILY_RS600 || ++ info->ChipFamily == CHIP_FAMILY_RS690) ++ RADEONCPFlushIndirect(pScrn, 1); ++#endif + } + + #undef ONLY_ONCE diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c index 2a9ee94..0423571 100644 --- a/src/radeon_legacy_memory.c @@ -7399,10 +8241,10 @@ index 2a9ee94..0423571 100644 ExaOffscreenArea *area = mem_struct; diff --git a/src/radeon_memory.c b/src/radeon_memory.c new file mode 100644 -index 0000000..94ff656 +index 0000000..766f977 --- /dev/null +++ b/src/radeon_memory.c -@@ -0,0 +1,407 @@ +@@ -0,0 +1,418 @@ + +#include +#include @@ -7603,13 +8445,15 @@ index 0000000..94ff656 +Bool radeon_free_all_memory(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct radeon_memory *mem; ++ struct radeon_memory *mem, *tmp; + int i; + + for (i = 0; i < 2; i++) { -+ for (mem = info->mm.bo_list[i]; mem != NULL; -+ mem = mem->next) { ++ ++ for (mem = info->mm.bo_list[i]; mem != NULL; ) { ++ tmp = mem->next; + radeon_free_memory(pScrn, mem); ++ mem = tmp; + } + } + return TRUE; @@ -7664,9 +8508,9 @@ index 0000000..94ff656 + int cpp = info->CurrentLayout.pixel_bytes; + int screen_size; + int stride = pScrn->displayWidth * cpp; -+ int total_size_bytes = (16*1024*1024)+32*1024, remain_size_bytes; ++ int total_size_bytes = 0, remain_size_bytes; + int fb_size_bytes; -+ ++ int pagesize = 4096; + + screen_size = RADEON_ALIGN(pScrn->virtualY, 16) * stride; + @@ -7676,6 +8520,7 @@ index 0000000..94ff656 + int cursor_size = 64 * 4 * 64; + int c; + ++ cursor_size = RADEON_ALIGN(cursor_size, pagesize); + for (c = 0; c < xf86_config->num_crtc; c++) { + /* cursor objects */ + info->mm.cursor[c] = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, cursor_size, 0, 1, "Cursor", 1); @@ -7700,6 +8545,7 @@ index 0000000..94ff656 + } + } + ++ screen_size = RADEON_ALIGN(screen_size, pagesize); + /* keep area front front buffer - but don't allocate it yet */ + total_size_bytes += screen_size; + @@ -7716,6 +8562,7 @@ index 0000000..94ff656 + { + int depthCpp = (info->dri->depthBits - 8) / 4; + int depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp; ++ depth_size = RADEON_ALIGN(depth_size, pagesize); + info->mm.depth_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, depth_size, 0, 1, "Depth Buffer", 1); + if (!info->mm.depth_buffer) { + return FALSE; @@ -7728,14 +8575,19 @@ index 0000000..94ff656 + /* work out from the mm size what the exa / tex sizes need to be */ + remain_size_bytes = info->mm.vram_size - total_size_bytes; + -+ info->dri->textureSize = remain_size_bytes / 2; ++ if (info->dri->textureSize > 0) ++ info->dri->textureSize = (remain_size_bytes / 100) * info->dri->textureSize; ++ else ++ info->dri->textureSize = remain_size_bytes / 2; ++ ++ info->dri->textureSize = RADEON_ALIGN(info->dri->textureSize, pagesize); + -+ ErrorF("texture size is %dK, exa is %dK\n", info->dri->textureSize / 1024, (remain_size_bytes - info->dri->textureSize)/1024); ++ remain_size_bytes -= info->dri->textureSize; + -+ fb_size_bytes = screen_size + (remain_size_bytes - info->dri->textureSize); ++ ErrorF("texture size is %dK, exa is %dK\n", info->dri->textureSize / 1024, remain_size_bytes/1024); ++ ++ fb_size_bytes = screen_size; + -+ if (info->new_cs) -+ fb_size_bytes = screen_size; + ErrorF("fb size is %dK %dK\n", fb_size_bytes / 1024, total_size_bytes / 1024); + + info->mm.front_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, fb_size_bytes, 0, 1, "Front Buffer + EXA", 1); @@ -7749,16 +8601,6 @@ index 0000000..94ff656 + } + info->dri->frontPitch = pScrn->displayWidth; + -+ if (!info->new_cs) { -+ info->accel_state->exa->memoryBase = info->mm.front_buffer->map; -+ info->accel_state->exa->offScreenBase = screen_size; -+ info->accel_state->exa->memorySize = fb_size_bytes; -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, -+ "Will use %ld kb for X Server offscreen at offset 0x%08lx\n", -+ (info->accel_state->exa->memorySize - info->accel_state->exa->offScreenBase) / -+ 1024, info->accel_state->exa->offScreenBase); -+ } -+ + if (info->directRenderingEnabled) { + info->mm.texture_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, info->dri->textureSize, 0, 1, "Texture Buffer", 1); + if (!info->mm.texture_buffer) { @@ -7770,7 +8612,17 @@ index 0000000..94ff656 + if (info->drm_mode_setting) { + drmmode_set_fb(pScrn, &info->drmmode, pScrn->virtualX, RADEON_ALIGN(pScrn->virtualY, 16), stride, info->mm.front_buffer->kernel_bo_handle); + } -+ radeon_bufmgr_gem_set_vram_limit(info->bufmgr, remain_size_bytes / 2); ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK at 0x%08x\n", info->mm.front_buffer->size/1024, info->mm.front_buffer->offset); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Back buffer size: %dK at 0x%08x\n", info->mm.back_buffer->size/1024, info->mm.back_buffer->offset); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Depth buffer size: %dK at 0x%08x\n", info->mm.depth_buffer->size/1024, info->mm.depth_buffer->offset); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Texture size: %dK at 0x%08x\n", info->mm.texture_buffer->size/1024, info->mm.texture_buffer->offset); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Remaining VRAM size (used for pixmaps): %dK\n", remain_size_bytes/1024); ++ ++ /* set the emit limit at 90% of VRAM */ ++ remain_size_bytes = (remain_size_bytes / 10) * 9; ++ ++ radeon_bufmgr_gem_set_limit(info->bufmgr, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes); + return TRUE; +} + @@ -7790,6 +8642,7 @@ index 0000000..94ff656 + } + + radeon_bind_memory(pScrn, info->mm.gart_texture_buffer); ++ + return TRUE; +} + @@ -7811,10 +8664,10 @@ index 0000000..94ff656 +} + diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index c14241e..8ef7381 100644 +index 5cd610c..907c52b 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h -@@ -184,6 +184,27 @@ typedef struct +@@ -183,6 +183,27 @@ typedef struct Bool hw_capable; } RADEONI2CBusRec, *RADEONI2CBusPtr; @@ -7842,7 +8695,7 @@ index c14241e..8ef7381 100644 typedef struct _RADEONCrtcPrivateRec { void *crtc_rotate_mem; void *cursor_mem; -@@ -196,6 +217,8 @@ typedef struct _RADEONCrtcPrivateRec { +@@ -195,6 +216,8 @@ typedef struct _RADEONCrtcPrivateRec { uint32_t crtc_offset; int can_tile; Bool enabled; @@ -7852,7 +8705,7 @@ index c14241e..8ef7381 100644 typedef struct { diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index c185b46..1c54256 100644 +index 7712344..b147495 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -39,6 +39,7 @@ @@ -7863,7 +8716,7 @@ index c185b46..1c54256 100644 #include #include "fourcc.h" -@@ -85,6 +86,7 @@ static __inline__ uint32_t F_TO_DW(float val) +@@ -111,6 +112,7 @@ static __inline__ uint32_t F_TO_24(float val) #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -7871,7 +8724,7 @@ index c185b46..1c54256 100644 #define FINISH_ACCEL() #include "radeon_textured_videofuncs.c" -@@ -94,6 +96,7 @@ static __inline__ uint32_t F_TO_DW(float val) +@@ -120,6 +122,7 @@ static __inline__ uint32_t F_TO_24(float val) #undef BEGIN_ACCEL #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F @@ -7879,7 +8732,7 @@ index c185b46..1c54256 100644 #undef FINISH_ACCEL #ifdef XF86DRI -@@ -107,6 +110,7 @@ static __inline__ uint32_t F_TO_DW(float val) +@@ -133,6 +136,7 @@ static __inline__ uint32_t F_TO_24(float val) #define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val)) #define FINISH_ACCEL() ADVANCE_RING() #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) @@ -7887,17 +8740,17 @@ index c185b46..1c54256 100644 #include "radeon_textured_videofuncs.c" -@@ -189,7 +193,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -214,7 +218,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + break; } - #ifdef XF86DRI -- if (info->directRenderingEnabled && info->DMAForXv) -+ if ((info->directRenderingEnabled || info->drm_mode_setting) -+ && info->DMAForXv ) - /* The upload blit only supports multiples of 64 bytes */ - dstPitch = (dstPitch + 63) & ~63; - else -@@ -207,6 +212,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +- dstPitch = (dstPitch + 63) & ~63; ++ /* always align to 64 bytes - fixes issue with non-CP code */ ++ dstPitch = (dstPitch + 63) & ~63; + + if (pPriv->video_memory != NULL && size != pPriv->size) { + radeon_legacy_free_memory(pScrn, pPriv->video_memory); +@@ -227,6 +232,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, size * 2, 64); if (pPriv->video_offset == 0) return BadAlloc; @@ -7906,8 +8759,8 @@ index c185b46..1c54256 100644 + pPriv->src_bo = pPriv->video_memory; } - /* Bicubic filter loading */ -@@ -219,6 +227,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + /* Bicubic filter setup */ +@@ -250,6 +258,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset; if (pPriv->bicubic_offset == 0) pPriv->bicubic_enabled = FALSE; @@ -7917,7 +8770,7 @@ index c185b46..1c54256 100644 } if (pDraw->type == DRAWABLE_WINDOW) -@@ -248,8 +259,19 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -279,8 +290,19 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, left = (x1 >> 16) & ~1; npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; @@ -7939,7 +8792,7 @@ index c185b46..1c54256 100644 pPriv->src_pitch = dstPitch; pPriv->size = size; pPriv->pDraw = pDraw; -@@ -290,8 +312,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -321,8 +343,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, } /* Upload bicubic filter tex */ @@ -7966,7 +8819,7 @@ index c185b46..1c54256 100644 /* update cliplist */ if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { -@@ -308,8 +346,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -339,8 +377,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->w = width; pPriv->h = height; @@ -7979,25 +8832,60 @@ index c185b46..1c54256 100644 else #endif diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index c5ad0e1..61fecc8 100644 +index 410430c..b51637a 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c -@@ -95,6 +95,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -92,6 +92,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; + struct radeon_exa_pixmap_priv *driver_priv; ++ struct radeon_space_check bos[2]; ++ int i, ret; ++ int retry_count = 0; + dri_bo *dst_bo; uint32_t txformat; uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; uint32_t dst_offset, dst_pitch, dst_format; -@@ -103,19 +105,25 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -100,19 +105,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); + int qwords; ACCEL_PREAMBLE(); ++ retry: ++ if (info->new_cs) { ++ ++ i = 0; ++ bos[i].buf = pPriv->src_bo; ++ bos[i].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; ++ bos[i].write_domain = 0; ++ i++; ++ ++ driver_priv = exaGetPixmapDriverPrivate(pPixmap); ++ dst_bo = driver_priv->bo; ++ bos[i].buf = driver_priv->bo; ++ bos[i].read_domains = 0; ++ bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;; ++ i++; ++ ++ ret = dri_bufmgr_check_aperture_space(bos, i); ++ if (ret == BUFMGR_SPACE_OP_TO_BIG) { ++ ErrorF("Not enough RAM to hw accel composite operation\n"); ++ return; ++ } ++ if (ret == BUFMGR_SPACE_FLUSH) { ++ RADEONCPFlushIndirect(pScrn, 1); ++ retry_count++; ++ if (retry_count == 2) { ++ ErrorF("Not enough RAM to hw accel composite operation\n"); ++ return; ++ } ++ goto retry; ++ } ++ } ++ pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; #ifdef USE_EXA @@ -8020,7 +8908,7 @@ index c5ad0e1..61fecc8 100644 dst_pitch = pPixmap->devKind; } -@@ -210,13 +218,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -213,13 +256,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txoffset = pPriv->src_offset; @@ -8043,7 +8931,7 @@ index c5ad0e1..61fecc8 100644 FINISH_ACCEL(); txenable = R300_TEX_0_ENABLE; -@@ -237,13 +252,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -240,13 +290,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); @@ -8065,7 +8953,7 @@ index c5ad0e1..61fecc8 100644 FINISH_ACCEL(); /* Enable tex 1 */ -@@ -980,11 +1001,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1332,11 +1388,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv } } @@ -8086,7 +8974,7 @@ index c5ad0e1..61fecc8 100644 OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; -@@ -1029,6 +1057,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1381,6 +1444,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE); @@ -8095,7 +8983,7 @@ index c5ad0e1..61fecc8 100644 OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset); OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); -@@ -1066,7 +1096,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1418,7 +1483,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); @@ -8105,7 +8993,7 @@ index c5ad0e1..61fecc8 100644 OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_ZERO | -@@ -1099,8 +1130,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1451,8 +1517,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST | RADEON_YUV_TO_RGB); @@ -8118,10 +9006,10 @@ index c5ad0e1..61fecc8 100644 RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | diff --git a/src/radeon_video.c b/src/radeon_video.c -index 6249cea..5874335 100644 +index 423ea28..ae62549 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c -@@ -257,7 +257,7 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -287,7 +287,7 @@ void RADEONInitVideo(ScreenPtr pScreen) memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); adaptors = newAdaptors; @@ -8130,7 +9018,7 @@ index 6249cea..5874335 100644 overlayAdaptor = RADEONSetupImageVideo(pScreen); if (overlayAdaptor != NULL) { adaptors[num_adaptors++] = overlayAdaptor; -@@ -270,7 +270,7 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -300,7 +300,7 @@ void RADEONInitVideo(ScreenPtr pScreen) if (info->ChipFamily != CHIP_FAMILY_RV250) { if ((info->ChipFamily < CHIP_FAMILY_RS400) #ifdef XF86DRI @@ -8139,7 +9027,7 @@ index 6249cea..5874335 100644 #endif ) { texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -@@ -2173,7 +2173,7 @@ RADEONCopyData( +@@ -2203,7 +2203,7 @@ RADEONCopyData( #ifdef XF86DRI @@ -8149,16 +9037,16 @@ index 6249cea..5874335 100644 uint8_t *buf; uint32_t bufPitch, dstPitchOff; diff --git a/src/radeon_video.h b/src/radeon_video.h -index 11b8029..a1bd20c 100644 +index 7f1891e..7a5f740 100644 --- a/src/radeon_video.h +++ b/src/radeon_video.h -@@ -111,6 +111,9 @@ typedef struct { - int src_w, src_h, dst_w, dst_h; +@@ -116,6 +116,9 @@ typedef struct { int w, h; int drw_x, drw_y; + int vsync; + + dri_bo *src_bo; + dri_bo *bicubic_bo; } RADEONPortPrivRec, *RADEONPortPrivPtr; - void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); + int diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index ce7ee1a..09e8087 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -47,7 +47,7 @@ X.Org X11 ati video driver. %patch6 -p1 -b .bgnr %build -autoreconf +autoreconf -iv %configure --disable-static make %{?_smp_mflags}