diff --git a/radeon-modeset.patch b/radeon-modeset.patch index db3a548..0239d93 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -1,3 +1,25 @@ +commit 4e24123007f8dd8bb2aee5398778bf36d920521e +Author: Dave Airlie +Date: Tue Oct 21 15:50:31 2008 +1000 + + radeon: avoid unnecessary emits + +commit e207eb6181692d8afe893fcd3b39f38bd3cf202b +Author: Dave Airlie +Date: Tue Oct 21 15:50:17 2008 +1000 + + radeon: cleanup reserved space calcs + +commit 21d9f5b0d9507404e6a2c55955420747bee2cbfb +Author: Dave Airlie +Date: Tue Oct 21 15:49:48 2008 +1000 + + radeon: fixup Owen's optimisation - this fixes corruption + + I haven't a good explaination why mapping the buffer twice in a row + seems to cause this failure. but I probably don't have time to track + it down before release. + commit dab489dc784bb14ef4a64b3ecec1c46568210c22 Author: Dave Airlie Date: Sun Oct 19 18:27:53 2008 +1000 @@ -1631,7 +1653,7 @@ index f7ae1a8..b179421 100644 do { \ if (RADEON_VERBOSE) \ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index a6e332d..035e87d 100644 +index a6e332d..f0a81c8 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -311,6 +311,9 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) @@ -1767,10 +1789,11 @@ index a6e332d..035e87d 100644 switch (info->CurrentLayout.pixel_code) { case 8: datatype = 2; break; -@@ -550,6 +556,75 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) +@@ -550,6 +556,76 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) } } ++#define RADEON_IB_RESERVE (16 * sizeof(uint32_t)) +drmBufPtr RADEONCSGetBuffer(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); @@ -1780,7 +1803,7 @@ index a6e332d..035e87d 100644 + return NULL; + + info->cp->ib_gem_fake.used = 0; -+ info->cp->ib_gem_fake.total = RADEON_BUFFER_SIZE - (16*4); // reserve 16 dwords ++ info->cp->ib_gem_fake.total = RADEON_BUFFER_SIZE - RADEON_IB_RESERVE; // reserve 16 dwords + return &info->cp->ib_gem_fake; +} + @@ -1792,7 +1815,7 @@ index a6e332d..035e87d 100644 + RING_LOCALS; + + /* always add the cache flushes to the end of the IB */ -+ info->cp->indirectBuffer->total += 16 * 4; ++ info->cp->indirectBuffer->total += RADEON_IB_RESERVE; + + /* end of IB purge caches */ + if (info->cs_used_depth) { @@ -1817,7 +1840,7 @@ index a6e332d..035e87d 100644 + + info->cp->indirectStart = 0; + info->cp->indirectBuffer->used = 0; -+ info->cp->indirectBuffer->total -= 16*4; ++ info->cp->indirectBuffer->total -= RADEON_IB_RESERVE; + + if (info->bufmgr) + radeon_gem_bufmgr_post_submit(info->bufmgr); @@ -1843,7 +1866,7 @@ index a6e332d..035e87d 100644 /* Get an indirect buffer for the CP 2D acceleration commands */ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) { -@@ -560,6 +635,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -560,6 +636,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) int size = 0; int i = 0; int ret; @@ -1853,7 +1876,7 @@ index a6e332d..035e87d 100644 #if 0 /* FIXME: pScrn->pScreen has not been initialized when this is first -@@ -625,6 +703,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -625,6 +704,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) if (!buffer) return; if (start == buffer->used && !discard) return; @@ -1865,7 +1888,7 @@ index a6e332d..035e87d 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", buffer->idx); -@@ -659,10 +742,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -659,10 +743,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) int start = info->cp->indirectStart; drm_radeon_indirect_t indirect; @@ -1882,7 +1905,7 @@ index a6e332d..035e87d 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n", -@@ -789,6 +878,7 @@ RADEONHostDataBlit( +@@ -789,6 +879,7 @@ RADEONHostDataBlit( ret = ( uint8_t* )&__head[__count]; __count += dwords; @@ -1890,7 +1913,7 @@ index a6e332d..035e87d 100644 ADVANCE_RING(); *y += *hpass; -@@ -926,7 +1016,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -926,7 +1017,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) #ifdef USE_EXA if (info->useEXA) { # ifdef XF86DRI @@ -1899,7 +1922,7 @@ index a6e332d..035e87d 100644 if (!RADEONDrawInitCP(pScreen)) return FALSE; } else -@@ -947,7 +1037,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -947,7 +1038,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) } #ifdef XF86DRI @@ -1908,7 +1931,7 @@ index a6e332d..035e87d 100644 RADEONAccelInitCP(pScreen, a); else #endif /* XF86DRI */ -@@ -969,11 +1059,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -969,11 +1060,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR (pScrn); #ifdef XF86DRI @@ -1926,7 +1949,7 @@ index a6e332d..035e87d 100644 RADEONInit3DEngineCP(pScrn); } else #endif -@@ -981,7 +1073,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -981,7 +1074,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) info->accel_state->XInited3D = TRUE; } @@ -2325,10 +2348,10 @@ index 0000000..0d79b58 +#endif diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c new file mode 100644 -index 0000000..dde1caf +index 0000000..3a82645 --- /dev/null +++ b/src/radeon_bufmgr_gem.c -@@ -0,0 +1,421 @@ +@@ -0,0 +1,426 @@ +/************************************************************************** + * + * Copyright © 2007-2008 Red Hat Inc. @@ -2404,6 +2427,7 @@ index 0000000..dde1caf + struct _dri_bo_gem *next; + struct _dri_bo_gem *reloc_next; + int in_vram; /* have we migrated this bo to VRAM ever */ ++ int touched; +} dri_bo_gem; + +typedef struct _dri_bufmgr_gem { @@ -2447,6 +2471,7 @@ index 0000000..dde1caf + gem_bo->map_count = 0; + gem_bo->in_vram = 0; + gem_bo->name = name; ++ gem_bo->touched = 0; + + DBG("bo_create: buf %d (%s) %ldb\n", + gem_bo->gem_handle, gem_bo->name, size); @@ -2503,7 +2528,8 @@ index 0000000..dde1caf + + if (gem_bo->map_count++ != 0) + return 0; -+ ++ ++ gem_bo->touched = 1; + args.handle = gem_bo->gem_handle; + args.offset = 0; + args.size = gem_bo->bo.size; @@ -2634,6 +2660,7 @@ index 0000000..dde1caf + gem_bo->in_vram = 1; + } + ++ gem_bo->touched = 1; + gem_bo->reloc_count++; + BUF_OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 2)); + BUF_OUT_RING(gem_bo->gem_handle); @@ -2744,15 +2771,16 @@ index 0000000..dde1caf + radeon_bufmgr->emit_reloc(buf, head, count_p, read_domains, write_domain); +} + -+int radeon_bufmgr_gem_in_vram(dri_bo *buf) ++/* if the buffer is references by the current IB we need to flush the IB */ ++int radeon_bufmgr_gem_has_references(dri_bo *buf) +{ + dri_bo_gem *gem_bo = (dri_bo_gem *)buf; -+ -+ return gem_bo->in_vram; ++ ++ return gem_bo->touched; +} diff --git a/src/radeon_bufmgr_gem.h b/src/radeon_bufmgr_gem.h new file mode 100644 -index 0000000..4c74c28 +index 0000000..f7fc757 --- /dev/null +++ b/src/radeon_bufmgr_gem.h @@ -0,0 +1,14 @@ @@ -2768,7 +2796,7 @@ index 0000000..4c74c28 +void radeon_bufmgr_pin(dri_bo *buf); +void radeon_bufmgr_unpin(dri_bo *buf); +uint32_t radeon_bufmgr_get_handle(dri_bo *buf); -+int radeon_bufmgr_gem_in_vram(dri_bo *buf); ++int radeon_bufmgr_gem_has_references(dri_bo *buf); +#endif diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index dba197e..10d146e 100644 @@ -5568,7 +5596,7 @@ index 66cefb7..ce20c59 100644 + #endif diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 0f86fdd..f7b890f 100644 +index 0f86fdd..77a15c9 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -43,7 +43,11 @@ @@ -5630,9 +5658,9 @@ index 0f86fdd..f7b890f 100644 + if (driver_priv->bo) { + int ret; + -+ if (radeon_bufmgr_gem_in_vram (driver_priv->bo)) ++ if (radeon_bufmgr_gem_has_references(driver_priv->bo)) + RADEONCPFlushIndirect(pScrn, 0); - ++ + //radeon_bufmgr_gem_wait_rendering(driver_priv->bo); + + /* flush IB */ @@ -5645,7 +5673,7 @@ index 0f86fdd..f7b890f 100644 + pPix->devPrivate.ptr = driver_priv->bo->virtual; + } + } -+ + +#if X_BYTE_ORDER == X_BIG_ENDIAN /* Front buffer is always set with proper swappers */ if (offset == 0) @@ -5663,7 +5691,7 @@ index 0f86fdd..f7b890f 100644 uint32_t offset = exaGetPixmapOffset(pPix); int soff; + struct radeon_exa_pixmap_priv *driver_priv; -+ + + driver_priv = exaGetPixmapDriverPrivate(pPix); + + if (driver_priv) { @@ -5671,12 +5699,12 @@ index 0f86fdd..f7b890f 100644 + pPix->devPrivate.ptr = NULL; + } + - ++ +#if X_BYTE_ORDER == X_BIG_ENDIAN /* Front buffer is always set with proper swappers */ if (offset == 0) return; -@@ -291,13 +341,100 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -291,14 +341,100 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); swapper_surfaces[index] = 0; @@ -5775,20 +5803,48 @@ index 0f86fdd..f7b890f 100644 #define RADEON_SWITCH_TO_2D() \ do { \ - uint32_t wait_until = 0; \ +- BEGIN_ACCEL(1); \ + uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ switch (info->accel_state->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ -@@ -314,7 +451,7 @@ do { \ + wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \ +@@ -307,15 +443,17 @@ do { \ + case EXA_ENGINEMODE_2D: \ + break; \ + } \ +- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ +- FINISH_ACCEL(); \ ++ if (wait_until) { \ ++ BEGIN_ACCEL(1); \ ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ ++ FINISH_ACCEL(); \ ++ } \ + info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ + } while (0); #define RADEON_SWITCH_TO_3D() \ do { \ - uint32_t wait_until = 0; \ +- BEGIN_ACCEL(1); \ + uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ switch (info->accel_state->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ -@@ -338,6 +475,7 @@ do { \ + wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ +@@ -324,8 +462,11 @@ do { \ + case EXA_ENGINEMODE_3D: \ + break; \ + } \ +- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ +- FINISH_ACCEL(); \ ++ if (wait_until) { \ ++ BEGIN_ACCEL(1); \ ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ ++ FINISH_ACCEL(); \ ++ } \ + info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ + } while (0); + +@@ -338,6 +479,7 @@ do { \ #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -5796,7 +5852,7 @@ index 0f86fdd..f7b890f 100644 #define FINISH_ACCEL() #ifdef RENDER -@@ -351,6 +489,7 @@ do { \ +@@ -351,6 +493,7 @@ do { \ #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F #undef FINISH_ACCEL @@ -5804,7 +5860,7 @@ index 0f86fdd..f7b890f 100644 #ifdef XF86DRI -@@ -361,6 +500,7 @@ do { \ +@@ -361,6 +504,7 @@ do { \ #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() @@ -5812,7 +5868,7 @@ index 0f86fdd..f7b890f 100644 #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) -@@ -378,6 +518,8 @@ do { \ +@@ -378,6 +522,8 @@ do { \ #endif /* XF86DRI */ @@ -5821,7 +5877,7 @@ index 0f86fdd..f7b890f 100644 /* * Once screen->off_screen_base is set, this function * allocates the remaining memory appropriately -@@ -399,122 +541,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -399,122 +545,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) if (info->accel_state->exa == NULL) return FALSE; @@ -6051,7 +6107,7 @@ index 0f86fdd..f7b890f 100644 return TRUE; } -@@ -527,10 +673,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr); +@@ -527,10 +677,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr); unsigned long long RADEONTexOffsetStart(PixmapPtr pPix) { diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 98c0556..6c85eb2 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.9.0 -Release: 28%{?dist} +Release: 29%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -72,6 +72,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Tue Oct 21 2008 Dave Airlie 6.9.0-29 +- fix most obvious glyph corruption issues in modesetting mode + * Sun Oct 19 2008 Dave Airlie 6.9.0-28 - fix set tex offset for non modesetting cases