From 931a65adcf0d77010388c39c13d10e7e0938d829 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: May 28 2008 06:27:52 +0000 Subject: - fix multiple VT switch issues on r600 cards - assorted upstream goodness --- diff --git a/radeon-git-upstream-fixes2.patch b/radeon-git-upstream-fixes2.patch index 53c24d9..059c938 100644 --- a/radeon-git-upstream-fixes2.patch +++ b/radeon-git-upstream-fixes2.patch @@ -1,8 +1,1500 @@ +commit faea008806802ec0e045754ec1eca492ebae320e +Author: Alex Deucher +Date: Tue May 27 18:36:01 2008 -0400 + + R3/4/5xx: use get_param to get the num_gb_pipes from the drm + +commit 965a5dbcd9dc4bf1cdd7f2bbdec15e9733b2e090 +Author: Alex Deucher +Date: Tue May 27 16:48:41 2008 -0400 + + RADEON: improve support for secondary cards + + this should fix bugs 16115, 16035 + +commit 5f951a5573f0c7572230c9aa4d3f75d67f91ed71 +Author: Alex Deucher +Date: Wed May 21 00:35:14 2008 -0400 + + ATOM: remove duplicate code + +commit edce33e87fb79a540d8c285f205d4c3f2c2bc9f4 +Author: Dave Airlie +Date: Wed May 28 06:43:40 2008 +1000 + + radeon: fix surface access on avivo chips. + + This should fix VT switch on vesafb + +commit 307bd65a25ee425d8359dd30572b002ce2338f91 +Author: Michael Babej +Date: Tue May 27 19:13:49 2008 +1000 + + r600: fix vt switch issue + + RH BZ 441492 + +commit bf48c9eb8ec592515be9d1732d60283af715674d +Author: Dave Airlie +Date: Sat May 24 11:51:20 2008 +1000 + + atombios: for LVDS set use ref div as per legacy + +commit 04500c8419b1aeaeac7968492b82e1d7cad1d05b +Author: Alan Coopersmith +Date: Tue May 20 20:34:31 2008 -0700 + + Strip ^M's from src/AtomBios/includes/ObjectID.h + +commit 521a0488d1c414209c3534dc242000faa332a441 +Author: Alan Coopersmith +Date: Tue May 20 20:33:37 2008 -0700 + + On non-gcc compilers, use C99's __func__ instead of gcc's __FUNCTION__ + +commit b7c80d0c86646105d2bce5d4d59ba6c45aa7cafc +Author: Tobias Diedrich +Date: Tue May 20 19:16:54 2008 -0400 + + R200/R300: fix gamma setup for overlay + + More pending. See bug 16001 + +commit 69423482e2e94637142a9ba675589a1449a346a8 +Author: Alex Deucher +Date: Tue May 20 18:57:13 2008 -0400 + + RADEON: cleanup connection detection and remove duplicate code + +commit 55e4469f59c82bb5762673de5f3f27d18b0bd9a3 +Author: Alex Deucher +Date: Tue May 20 17:46:58 2008 -0400 + + RADEON: enable cloning on multi-crtc cards + +commit 12f185634071980041aaac6265d89708b181b215 +Author: Alex Deucher +Date: Tue May 20 16:05:41 2008 -0400 + + ATOM: Ignore invalid connector entries + +commit 19e97f74e39fc2b35727708ac429de33d0b70162 +Author: Egbert Eich +Date: Tue May 20 11:16:15 2008 +0200 + + Change RMX code to follow the programming algorithm suggested by ATI. + + ATI provides the following algorithm to calculate the RMX scaling ratios + in its programming specs: + when RMX_AUTO_RATIO_HORZ_INC set to 1,Horizontal auto ratio result trucated, + and then incremented by 1. + Horz_Ratio = ( ((Active display width in characters (including overscan) + 1) + / (Panel width in characters)) x 4096 + 1 ) + else + Horz_Ratio = ( ((Active display width in characters (including overscan)) + / (Panel width in characters)) x 4096 + 1 ) + + when RMX_AUTO_RATIO_VERT_INC set to 1, Vertical auto ratio result trucated, + and then incremented by 1. + Vert_Ration = ( ((Active display width in characters (including overscan) + 1) + / (Panel width in characters)) x 4096 + 1) + else + Vert_Ration = ( ((Active display width in characters (including overscan)) + / (Panel width in characters)) x 4096 + 1) + + This patch implements this behavor. Additionally it avoids the use of floats. + +commit a4f3d0088ba763ed8eab1d331959b5ecde8262e8 +Author: Alex Deucher +Date: Tue May 20 11:42:53 2008 -0400 + + R3/4/5xx: fixup logic from last commit + + Spotted by otaylor and MrCooper + +commit 130e55738047f2a073bcc47e3e1400f7b694a81b +Author: Alex Deucher +Date: Tue May 20 11:32:42 2008 -0400 + + R3/4/5xx: fix EXA rotation + + xrandr uses PictOpSrc for rotation which we were falling back on since + render semanties require alpha=0 for REPEAT_NONE when there is no alpha + channel and there is a transform. If the dst has no alpha channel we + should be ok I think. + + Otayler and I discussed this on IRC. the more general fix would be + to clip the dst to the src and mask for bounded ops like in/add/over + in the pixel exact transform case. + +commit cc9f510770700228e5d597c872e926a4e99bd950 +Author: Corbin Simpson +Date: Wed May 14 16:49:01 2008 -0400 + + RADEON: missing stdint.h includes + +commit 71fa57f871dba03260dba2180ce1dab44048ac1a +Author: Alex Deucher +Date: Wed May 14 13:36:38 2008 -0400 + + Add RS600 support + +commit 582c1a1b2c7b1032e9f9f54ca36100c57f580c5c +Author: Alex Deucher +Date: Tue May 13 20:50:25 2008 -0400 + + RS4xx: Split out RS400 and RS480 as separate families + + RS400 (intel based IGP) and RS480 (AMD based IGP) have different + MC setups and need to be handled differently + +commit 708e7c98f636738fbcc47a597bc94b309a4dc1c4 +Author: Michel Dänzer +Date: Tue May 13 11:00:38 2008 +0200 + + Reinstate CARD* types that are part of external interfaces. + + The compiler pointed this out... + +commit 908b7b940e3ef296836bc94680ebb8ab67650e31 +Author: Matt Turner +Date: Mon May 12 12:06:33 2008 -0400 + + Replace CARD{8,16,32} with uint{8,16,32}_t + + As has been done with xf86-video-intel, replace all CARD* datatypes with + uint*_t datatypes available from stdint.h. + +commit 87e66ce76430890ab4939ffcd42f72b9288eb598 +Author: Avi Rozen +Date: Mon May 12 08:33:38 2008 -0400 + + RADEON: fix lockup on start + + see debian bug 480312 + +commit 94bf8f01bd43cb103fffecfe04d04a214f892baf +Author: Dave Airlie +Date: Mon May 12 20:02:51 2008 +1000 + + radeon: fix set_cursor_colours remove fb offset + +commit 1d0f1d31e2ed1d91ee87cb3e02ce48c8c07aa418 +Author: Dave Airlie +Date: Mon May 12 15:44:35 2008 +1000 + + radeon: rs485 vs rs485m.. mobile? non-mobile? bi? + + So it appears we have in the wild two chipsets with the same PCI ID (0x1002:0x5974) + that are mobile and non-mobile. + + the RH bug references is a desktop system. + The Dell Vostro 1100 also has this chipset with LVDS bits. + +commit 25e0c3945a51ae8c14b3a847ec75a256e1397f24 +Author: Alex Deucher +Date: Mon May 12 10:28:33 2008 +1000 + + radeon: add initial support for cloning outputs. (single-CRTC cards only) + + airlied - This code was originally written by Alex, and I've modified it to + only run on single-CRTC cards for now until we can test it some more. + +commit 94405eb1c9e4e0ababc6aef03b753d6ed9eb7838 +Author: Alex Deucher +Date: Fri May 9 05:28:44 2008 -0400 + + RADEON: fixup ifdef from last commit + +commit 18e20bc22a55ecfee9798c01079d7b24d19f0051 +Author: Alex Deucher +Date: Thu May 8 08:45:51 2008 -0400 + + RADEON: disable MMIO paths for EXA composite/texvid on IGP/R5xx + + The MMIO paths eventually lead to a hang on r5xx/IGP. I haven't + been able to find out why yet. + +commit c3532268875fd24e6519bea2fb1b814d612bbdb4 +Author: Dave Airlie +Date: Wed May 7 02:37:18 2008 +1000 + + radeon: fix zaphod EXA with texture video + +commit ffc437f3606ab8ceba1ff152e4bb08988a58b54c +Author: Dave Airlie +Date: Wed May 7 02:30:28 2008 +1000 + + avivo: fix zaphod cursor in theory + +commit e36ef14e3a1087e1fe41baa26ade2937f396001f +Author: Dave Airlie +Date: Wed May 7 01:39:28 2008 +1000 + + radeon: fix textured-xv on zaphod + +commit 8fc19bee27c0f151d2ab3354f6ac0992b358436d +Author: Dave Airlie +Date: Wed May 7 01:38:24 2008 +1000 + + radeon: zaphod: fix render accel for EXA + +commit fc41b9042a5220a8419cc7b69ca3850cae6b903c +Author: Dave Airlie +Date: Wed May 7 01:32:23 2008 +1000 + + radeon: fix EXA pixmap offset on zaphod + +commit 4568cb820d567c6909a4be956d7e79b91232535e +Author: Dave Airlie +Date: Wed May 7 01:19:39 2008 +1000 + + radeon: zaphod fixes for pciaccess not allowing multiple MMIO maps + +commit ca81fa086b21633a7fd926833fb6d1d4fa080646 +Author: Dave Airlie +Date: Wed May 7 01:12:01 2008 +1000 + + radeon: zaphod fix for cursor on second head + + We don't need to add fbOffset here as the mmap we have of the framebuffer + starts half way. + +commit 24b60c8965f6a0b3f0c2bb1e7236b4d6642c5918 +Author: Julien Cristau +Date: Fri May 2 15:30:45 2008 -0400 + + Add a test for __GLIBC__ to CD_Common_Types.h. + + Atombios redefines the standard types but the definitions conflict + with the ones from glibc (causes build failures on GNU/Hurd + and GNU/kFreeBSD). + +commit f051359ac09c6b9416e39b9ca7d9dc0880aa1557 +Author: thegraze +Date: Fri May 2 14:02:16 2008 -0400 + + ATOM: add support for DragonFlyBSD + +commit 3d469cbc3225d890a895dac7cbc1ab7e08054b48 +Author: Alex Deucher +Date: Wed Apr 30 18:33:04 2008 -0400 + + RADEON: lock the cursors when updating + + this should fix occasional corruption seen when updating + the cursor. + +commit 445b71021843665ba32f37b2ce5c9d2857c07cc7 +Author: Alex Deucher +Date: Tue Apr 29 21:01:41 2008 -0400 + + RADEON: assorted fixes + + - free rotate pixmaps on VT switch + - save crtc/output status so we only turn on + crtcs/outputs if they are off + - show/hide cursors when changing modes + +commit 070cce5255a5c311f9d8b85ec54bd56655014933 +Author: Stephan Wolf +Date: Mon Apr 28 11:26:37 2008 -0400 + + R3xx+: further fix for IGP chips + + see bug 15538 + +commit 211e0041c7fc2df494b77428553943a2b526ee4e +Author: Alex Deucher +Date: Sun Apr 27 21:08:00 2008 -0400 + + IGP: fix EXA composite corruption + +commit 656b06bdde129ca4fc370f5a2cf7311c9179b0ff +Author: Alex Deucher +Date: Sun Apr 27 20:20:49 2008 -0400 + + RADEON: remove duplicate register define + + Also add more bit defs to wait_until register + +commit 8a9820a3aa49bc667f90ac291a27e4d7b4ae38b3 +Author: Alex Deucher +Date: Sun Apr 27 19:02:22 2008 -0400 + + RADEON: decrease crtc/output verbosity + +commit c5d62fa0e8f52c3264ff9db3ff10cdf5a806bfc0 +Author: Owen Taylor +Date: Thu Apr 17 13:14:53 2008 +0200 + + Emulate repeats by drawing in tiles + + When we can't turn on hardware repeats, because the texture + is non-power-of-two, or has padding at the ends of lines, + try to draw the image in multiple tiles rather than falling + back to software. (We can only do this when there is no + transform.) + +commit eeb7b74bb6c813b0e3afa4b704f6ffb0d0aab92b +Author: Owen Taylor +Date: Thu Apr 17 13:14:25 2008 +0200 + + Turn on wrapping when repeating on R100 + R200 + + Actually enable repeats for R100 and R200. This corresponds + to a R300 change made in the patch in: + http://bugs.freedesktop.org/show_bug.cgi?id=15333 + +commit e511f39dfef503006cf249b9f6934091eaade9b5 +Author: Alex Deucher +Date: Thu Apr 17 05:04:34 2008 -0400 + + R300+: move more common code into init3d() + + - pre-load r3xx tex instructions + - setup RS instructions in init3d() + +commit 99435b7c18d931ea620044d0fdb4cc93dfcc6331 +Author: Owen Taylor +Date: Thu Apr 17 02:46:11 2008 -0400 + + Radeon: Omit mask coordinates + + Adapted from Owen's patch on bug 15546 + This fixes the slowness with aatext on r300 + and may speed up other chips marginally. + +commit 37614e1db9a595fbe8a21d7a045895e11d272db9 +Author: Alex Deucher +Date: Tue Apr 15 09:48:16 2008 -0400 + + fix up some things from the last commit + +commit 1286fe5ce1c77453d57817b9b26b1bdb32ca7bc8 +Author: Alex Deucher +Date: Mon Apr 14 20:02:14 2008 -0400 + + R300+: properly setup vap_cntl + + this fixes tcl/pvs on RV515 among other things + +commit f72a4b805db26f10f69330b88459cbeae661189b +Author: Alex Deucher +Date: Mon Apr 14 14:10:40 2008 -0400 + + EXA: Don't wait for 3D idle after each Composite() + + wait in CompositeDone() instead + +commit 4cd4acf1092aeb696b086a382a033aee471d2de9 +Author: Alex Deucher +Date: Mon Apr 14 11:50:59 2008 -0400 + + R300: move more common code to init3d() + +commit 3c523c9a07402e17dff588fad842224c57e98223 +Author: Alex Deucher +Date: Mon Apr 14 11:21:42 2008 -0400 + + R3xx+: 3D engine documentation and minor cleanups + + - document the R300 exa/textured video code + - minor cleanups of textured video code to clarify meaning + +commit ce025bbb2496d4de94b8d4ac450c64441b64ee04 +Author: Alex Deucher +Date: Sat Apr 12 21:22:03 2008 -0400 + + R300+: consolidate some tcl/non-tcl paths + + - Move more code to init3d() + - MMIO textured video seems more reliable now on newer chips + +commit 11b54a319c7c9dd52e3fb13372697059dafe1cd3 +Author: Alex Deucher +Date: Sat Apr 12 16:50:22 2008 -0400 + + R3xx+: fix XAA + textured video on non-TCL path + +commit dd15a2f5906725116b8cd9954243099055e88e37 +Author: Alex Deucher +Date: Sat Apr 12 16:49:03 2008 -0400 + + R3xx+: more fixes to 2D/3D engine init + +commit f3e68d4b7afd2e23675bf6361c496814c9cb4b94 +Author: Alex Deucher +Date: Fri Apr 11 10:59:07 2008 -0400 + + Fix exa glyph corruption on newer chips + +commit b59686d6427cbf8b35e36b020cbbc6a0c5149b22 +Author: Alex Deucher +Date: Fri Apr 11 10:15:25 2008 -0400 + + R300+: pre-load vertex programs in init3D() + +commit acc5833a35ad6c29a57f659607afb27eebdc2ea5 +Author: Alex Deucher +Date: Thu Apr 10 17:52:52 2008 -0400 + + R3xx+: consolidate more tcl code + +commit 6f8f75bd19ef1919c0291141675be2d0e29b3251 +Author: Alex Deucher +Date: Thu Apr 10 17:08:50 2008 -0400 + + R3xx+: consolidate some common 3D code + +commit 4b9234e1c4f7c7f419cb4245d64f3f9756c98bb6 +Author: Alex Deucher +Date: Thu Apr 10 16:58:22 2008 -0400 + + R3xx+: tcl wip + +commit 865c463e3afb4759758f569132be8bf1386da5cc +Author: Alex Deucher +Date: Thu Apr 10 16:51:04 2008 -0400 + + R300+: textured video tcl cleanup + +commit 79c8d4ca36a1c3e5fe759d4ccc379c36af8f1676 +Author: Alex Deucher +Date: Thu Apr 10 16:28:18 2008 -0400 + + RADEON: cleanup + +commit c4821a287d29a65f3bcb7d60dc72ec13c0384008 +Author: Alex Deucher +Date: Thu Apr 10 16:20:17 2008 -0400 + + Revert "R3xx/R5xx: move more VAP, etc. state setup into common init3d() function" + + This reverts commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02. + + Conflicts: + + src/radeon_commonfuncs.c + src/radeon_exa_render.c + src/radeon_textured_videofuncs.c + +commit 0032c80bf30bab189204e3e6929e18a19d753138 +Author: Alex Deucher +Date: Thu Apr 10 14:35:00 2008 -0400 + + RADEON: store tcl status in driver rec + +commit 9e2ffe66d106abe34a670d2edc9905ed62c485e8 +Author: Alex Deucher +Date: Thu Apr 10 14:24:04 2008 -0400 + + R3xx+: use the right register for engine flush + +commit e1a9f26c2d2cbca9ad159e723ec95b95be1ef349 +Author: Alex Deucher +Date: Thu Apr 10 14:12:15 2008 -0400 + + R3xx+: minor textured video fixes + + - set shader output swizzling correctly + - flush the right cache register on r3xx+ + +commit d79040906cd25bd494feb5901f465bbd050aa923 +Author: Alex Deucher +Date: Thu Apr 10 13:59:58 2008 -0400 + + R3xx+: EXA/textured video fixes + + - get pipe config based on GB_PIPE_SELECT where applicable + (adapted from a similar patch from Dave) + - only flush the dst cache after submitting vertices, freeing + the cache lines stalls the pipe + - no need to wait for 3D idle after submitting vertices + - fix PURGE_CACHE() and PURGE_ZCACHE() for r3xx+ + - fix depth 16 with EXA composite + +commit 0a96173cc38e506728d4c3f2dd383ba56e856578 +Author: Michel Dänzer +Date: Mon Apr 7 18:15:34 2008 +0200 + + Increase default CP timeout. + + Helps avoid spurious timeouts causing problems, see + http://bugs.freedesktop.org/show_bug.cgi?id=15203 . + +commit 255fbf465f5e7db2609a5a151bfa810249db52a0 +Author: Owen W. Taylor +Date: Thu Apr 3 02:25:41 2008 -0400 + + Fix rendering of transformed sources for REPEAT_NONE with EXA on >= R300. + + Use the border color when possible, otherwise fall back to software. + +commit bc0407e53237d7968808110bc0243076377acf6e +Author: Alex Deucher +Date: Fri Apr 4 18:40:16 2008 -0400 + + ATOMBIOS: Add support for DynamicClocks option + + This patch adds support for dynamic clock gating and static + power management using the atom command tables. In some cases + the bios may already set this up during post, so YMMV. + + I was only able to test on desktop cards, so I haven't tested + to see how much (if any) power this saves or how it affects the + thermal footprint. + +commit 5f5e21bb50555c56bd371576074c28c929307ff1 +Author: Alex Deucher +Date: Fri Apr 4 14:29:45 2008 -0400 + + RADEON: warning fixes + +commit c8e9a973aaded24aad567a0e36d0c78a05d6b2fd +Author: Alex Deucher +Date: Fri Apr 4 14:26:19 2008 -0400 + + RADEON: add some quirks + +commit 091963a635b79884afe77c026eabb48972fbe175 +Author: Alex Deucher +Date: Thu Apr 3 22:35:16 2008 -0400 + + Minor cleanup + +commit 950e9860643c20acde0eca4e4ff26baacc1f2b69 +Author: Alex Deucher +Date: Thu Apr 3 22:11:48 2008 -0400 + + Revert "RADEON: memmap rework 1" + + This reverts commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94. + + Conflicts: + + src/radeon.h + src/radeon_driver.c + + This rework seems to have caused more trouble than it was worth. + +commit 88a1fe4a94c5d11aff22734b21c89890e4428cd5 +Author: Alex Deucher +Date: Thu Apr 3 22:04:43 2008 -0400 + + Revert "RADEON: remove driver rec copies of mc info, use save rec directly" + + This reverts commit be0858a84fbdf74c0b844f462933a221d48c707d. + + Conflicts: + + src/radeon_driver.c + +commit c40a7aa3989576a8144213e2f31b892d21df8686 +Author: Owen W. Taylor +Date: Thu Apr 3 14:43:55 2008 -0400 + + R3xx/R5xx: Fix pitch and clamp mode for repeating textures + + - We can always use TXPITCH on a R300 even when repeating, + (previous check for pitch matching width was also wrong) + - Fix clamp mode for repeating textures to be WRAP + +commit a8593482c1f2e0f2dbac06c2e5325ba8c83ed9ff +Author: Dave Airlie +Date: Wed Apr 2 09:58:05 2008 +1000 + + atombios: fix the dual-head hopefully. + + tested on r600 with DVI and VGA + +commit 61d883d116fab3e9b513432d65e705afc5bb39f1 +Author: Dave Airlie +Date: Wed Apr 2 09:57:38 2008 +1000 + + Revert "Revert "atombios: fixup the width/height to use the mode values not the scrn ones"" + + This reverts commit fc9af578997b6f22ee8b17e83f37d98689291b0e. + + I see your revert and raise you one... + +commit fc9af578997b6f22ee8b17e83f37d98689291b0e +Author: Alex Deucher +Date: Tue Apr 1 09:25:45 2008 -0400 + + Revert "atombios: fixup the width/height to use the mode values not the scrn ones" + + This reverts commit c2b1c8b706a6c7c1fd0af80091958473133d54e7. + + These registers hold surface size. Using the mode values + breaks dualhead. + +commit 959509dd54de053f526b534e379a46934127231f +Author: Dave Airlie +Date: Mon Mar 31 14:29:44 2008 +1000 + + radeon: use correct DDC interfaces so quirks get applied + + Radeon seemed to mess up applying certain quirks, hopefully this will fix it. + +commit 18f5f1cd2f52afed89fc11ade0920f3dfea87306 +Author: Dave Airlie +Date: Mon Mar 31 14:11:49 2008 +1000 + + radeon: split quirks into separate function and new quirk for IBM RN50 + + Add a connector table quirk for the IBM RN50. + +commit c2b1c8b706a6c7c1fd0af80091958473133d54e7 +Author: Dave Airlie +Date: Sun Mar 30 11:44:14 2008 +1000 + + atombios: fixup the width/height to use the mode values not the scrn ones + + this fixes it properly, legacy appears to be okay. + +commit c5edea3d8c9254d3a21e390b8309e39e4c9635db +Author: Dave Airlie +Date: Sun Mar 30 11:11:22 2008 +1000 + + r500/r600: fix rotation to fill screen + + I'm not 100% sure this is the correct fix (maybe we shouldn't be using scrn + virtualX/Y)... this will fix it for now until I get more time. + +commit 9c62c820ba45ebc14d5f36f5d7885863800b6adb +Author: Michel Dänzer +Date: Fri Mar 28 12:37:29 2008 +0100 + + Include config.h, so FGL_LINUX can actually be defined when it's tested... + +commit a00d9260a85b94a522c442aee24bc5ea4dc31c5c +Author: Alex Deucher +Date: Thu Mar 27 20:03:13 2008 -0400 + + RADEON: fix lid issues on AVIVO chips for real this time :) + +commit f0e89c09074b2c7e641f73692bb39b0bf68eb49c +Author: Alex Deucher +Date: Thu Mar 27 19:15:18 2008 -0400 + + Revert "RADEON: attempt to fix lid issues" + + This reverts commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4. + This doesn't help. + +commit 1442d396b938049b83f009a78ddabe2bf85641b6 +Author: Dave Airlie +Date: Thu Mar 27 14:02:51 2008 +1000 + + radeon: size bios to max of bar vs 64k. + + reported by dwmw2: rhbz 438299 + +commit de2f609ff0004ef8b74727bfebc2c74fb91205ea +Author: Alex Deucher +Date: Wed Mar 26 18:35:21 2008 -0400 + + AVIVO: no need to call PreinitXv() on AVIVO chips as they have no overlay + +commit 75884c257bc2bcfa5b498a77d4c403f09face036 +Author: Alex Deucher +Date: Wed Mar 26 18:16:47 2008 -0400 + + XAA: update message about render so as to not confuse users + +commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4 +Author: Alex Deucher +Date: Wed Mar 26 18:01:29 2008 -0400 + + RADEON: attempt to fix lid issues + + On some laptops the bios attempts to re-program the chip + when a lid event comes in. This should hopefully prevent + the bios from doing that. + +commit 8b144830fe9b4a0cee4745023de5e7d387070f60 +Author: Alex Deucher +Date: Tue Mar 25 01:15:05 2008 -0400 + + RV250: disable textured video due to HW bug + + The YUV->RGB conversion in the texture engine is broken + on RV250 so the colors come out wrong. + +commit 1789f11ab91633d3928f8b71988d51ff44bda9d1 +Author: Alex Deucher +Date: Mon Mar 24 19:03:30 2008 -0400 + + R3xx/R5xx: flush PVS state before enabling pvs-bypass + +commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02 +Author: Alex Deucher +Date: Mon Mar 24 14:25:03 2008 -0400 + + R3xx/R5xx: move more VAP, etc. state setup into common init3d() function + + Also some minor code cleanups + +commit 399b1d405e602c62d6deebea6d7e1f38886cd8e2 +Author: Alex Deucher +Date: Mon Mar 24 13:04:57 2008 -0400 + + R3xx/R5xx: use non VAP/TCP for textured video + + Just extra state to emit. + +commit cd77ec18f32a7b36acb655c927bbfd7044019f97 +Author: Dave Airlie +Date: Mon Mar 24 18:42:21 2008 +1000 + + r300: don't bother with VAP/TCL for render. + + We just send more data to the card to process per transaction, without getting + any actual gains, as we already pre-compute the vertices without needing + any clipping or transforms from the card. + + Perhaps some stuff could be done on-card, but so far the code is a lot + faster if we avoid sending this extra info. + + pre: 150000 glyphs/sec + post: 185000 glyphs/sec + +commit 301c6739b88676a0c78fc72194e993f894b8dc28 +Author: Alex Deucher +Date: Sun Mar 23 11:14:02 2008 -0400 + + RS4xx: Revert back to previous fifo settings for now + + Setup of these registers needs more investigation. + +commit 9bea60b3eb378de5e1d44cc02a2763f4feae7882 +Author: Alex Deucher +Date: Sat Mar 22 11:46:15 2008 -0400 + + RS4xx: more work on disp/disp2 fifo setup + +commit 90f11c3986c28daa7b600b9662da145af325d264 +Author: Alex Deucher +Date: Sat Mar 22 11:29:51 2008 -0400 + + RS4xx: missed this on the last commit. + +commit 6d5066a451017a2683addc9e2496987626795dda +Author: Alex Deucher +Date: Fri Mar 21 16:21:54 2008 -0400 + + RS4xx: attempt to set up disp/disp2 fifos correctly + + If you have an XPRESS chip, please test!!! + +commit fb1cffac05ae20c8365b25a2042b0ae961880faf +Author: Alex Deucher +Date: Fri Mar 21 15:24:36 2008 -0400 + + RS4xx: attempt to fix TMDS/DVO support + + XPRESS chips added a second set of FP control registers. + I don't have the hw to test however. + +commit 5e3b21284482df9974c9a58f248f0100def2bb0c +Author: Alex Deucher +Date: Wed Mar 19 19:15:05 2008 -0400 + + Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST + + See bug 11796 + +commit 17cd42ed31814ba329a6a68edd0d75390a7da40e +Author: Matt Turner +Date: Wed Mar 19 18:17:10 2008 -0400 + + Enable BSR in Log2 functions + + This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead + of looping through bits. It should provide a somewhat of a speed increase in + this function on x86 and AMD64 architectures. + + Note: the BSR instruction was added with the 80386 CPU and is therefore not + compatible with earlier CPUs, though I highly doubt it's even possible to use a + 286 in conjunction with a Radeon. + + The inline assembly also works with Intel's compiler (icc). + +commit c83827b4d2b6f03c54429e757a756eb99ff8be6b +Author: Paulo Cesar Pereira de Andrade +Date: Wed Mar 19 17:58:34 2008 -0400 + + [PATCH] Compile warning fixes. + + Minor changes to avoid declarations mixed with code. + Ansified functions with empty prototype to specify they don't + receive arguments. + Added some prototypes to radeon.h, and major reorder on radeon.h + adding prototypes in alphabetical order and specifying to file that + defines it. + +commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb +Merge: 55e446b... f71ac0e... +Author: Alex Deucher +Date: Wed Mar 19 16:06:41 2008 -0400 + + Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render + +commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246 +Author: Alex Deucher +Date: Wed Mar 19 13:15:32 2008 -0400 + + R3xx/R5xx: Make sure to clamp the output of the FS + +commit b6aa4279cbe68cc8e4523795e9714fb798b62d98 +Author: Alex Deucher +Date: Wed Mar 19 12:45:01 2008 -0400 + + R5xx: bump textured video limits to 4096 + +commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1 +Author: Alex Deucher +Date: Wed Mar 19 12:31:51 2008 -0400 + + RADEON: add new macros to distinguish between R3xx and R5xx 3D + +commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0 +Author: Alex Deucher +Date: Wed Mar 19 12:07:33 2008 -0400 + + RADEON: fixed textured video with XAA and tiling + +commit f5951db7b3522e0fe6af7f46a170c9c9a60a9bff +Author: Alex Deucher +Date: Wed Mar 19 12:01:50 2008 -0400 + + RV515: fix textured video and EXA Composite + + There seems to be an issue with the PVS setup on RV515, but + bypassing it seems to work fine. + +commit 13573879fe56368ad06234712b677c23fabc56c6 +Author: Dave Airlie +Date: Wed Mar 19 15:06:47 2008 +1000 + + r500: make it work from startup. + + I'm not sure why this worked or what is going wrong here, really the + VAP internal architecture escapes me :) + +commit d331dd64d644a18ec99a2136cd0943b5edca1f03 +Author: Alex Deucher +Date: Tue Mar 18 19:44:26 2008 -0400 + + R3xx/R5xx: remove extra return after last commit + +commit bc34df7a9c35cdd38c49d5c22471f3f487a33d6e +Author: Alex Deucher +Date: Tue Mar 18 19:39:47 2008 -0400 + + R3xx/R5xx: switch an ErrorF() to RADEONFALLBACK() + +commit 6f03f8fe0ecf4181dcf125049cf63bece0451fb2 +Author: Alex Deucher +Date: Tue Mar 18 19:36:05 2008 -0400 + + R3xx: we only use 2 temps, not 3 + +commit 8bb71ab4a3eb4fb6ef7f709e87c8df387cb70ee3 +Author: Tilman Sauerbeck +Date: Tue Mar 18 14:36:08 2008 -0400 + + R3xx/R5xx: fix up a8-src-something_with_colors + +commit c362591d9b496df30668543158e4de44de742dc3 +Author: Alex Deucher +Date: Tue Mar 18 11:15:17 2008 -0400 + + R3xx/R5xx: remove some cruft + +commit 89fe6d2c7d7471e6088558130f6e49f46c31dd47 +Author: Dave Airlie +Date: Tue Mar 18 09:43:43 2008 -0400 + + R5xx: fix typ in r5xx render accel + + This gets render working on r5xx + +commit 79b40ebcd8dedfc83e484c1024beeeaccc6124f3 +Author: Alex Deucher +Date: Tue Mar 18 02:46:49 2008 -0400 + + R5xx: first pass at render support (untested) + +commit 71292c8f193230255d1d980c2e996bb01d04fab6 +Author: Alex Deucher +Date: Tue Mar 18 00:45:37 2008 -0400 + + R5xx: bump tex/dst limits to 4096 + +commit 30b52f8aa6a471455284f59b5b27252743892b13 +Author: Alex Deucher +Date: Mon Mar 17 23:20:10 2008 -0400 + + R3xx/R5xx: whitespace cleanup and cruft removal + +commit 9c9f1b538ed710c3066775fba0a8e936b63087b1 +Author: Alex Deucher +Date: Mon Mar 17 23:01:37 2008 -0400 + + R3xx: get masks working and cleanup + + RS offset was wrong for mask texture + +commit ef94febd74f8ee63081b61e42f093a5a2b8fbf1e +Author: Alex Deucher +Date: Mon Mar 17 22:27:19 2008 -0400 + + R3xx: minor adjustments + +commit f71ac0e40b9d950bcb3bba42a75d41f45b6ed1bf +Author: Alban Browaeys +Date: Mon Mar 17 20:48:48 2008 -0400 + + RADEON: Revert to old behavior when resetting the memmap on VT switch + + Not sure why this needs to be done twice. Should fix bug 14980 + Probably needs more investigation. + +commit bedbbf196dc97ee5142e7dfae16fb6f317fca5a7 +Author: Alex Deucher +Date: Mon Mar 17 20:16:25 2008 -0400 + + R3xx: some progress + +commit af0e626c132de2dd9958fec657fcc85d4c0fe5e1 +Author: Alex Deucher +Date: Mon Mar 17 18:07:12 2008 -0400 + + R3xx: fix errant w + +commit 29ea5bfc0eb3194e2454fc3ee863df54f0300880 +Author: Alex Deucher +Date: Mon Mar 17 16:41:57 2008 -0400 + + RADEON: fix typo in RADEONAdjustMemMapRegisters() + +commit ab317e85c5ab1a249a510c34aeb3a908be1a66fc +Author: Alex Deucher +Date: Mon Mar 17 15:28:09 2008 -0400 + + RADEON: make sure var is initialized properly in RADEONAdjustMemMapRegisters() + +commit 208d307227e15f37a6af5194398ed23266ff743a +Author: Dave Airlie +Date: Sun Mar 16 19:39:23 2008 +1000 + + radeon: the 0x5974 appears to be a mobility chip... + + After debugging with partymola on #radeon, adding this allowed his + Dell Vostro 1000 to work properly + +commit 9bc7c2ec4048e1677547c1d60c51ccb954f7589a +Author: Alex Deucher +Date: Fri Mar 14 20:12:22 2008 -0400 + + R3xx: odds and ends... + + still not working. + - swizzle US output for BGR formats + - no need to write to temps in ALU ops, + write to output only + - flush the PVS before updating + +commit 96bea7906c4706fcd57a9cd8f1ce3feab6ac676d +Author: Alex Deucher +Date: Fri Mar 14 15:59:36 2008 -0400 + + R3xx: theoretical support for component alpha + + masks are still broken so... + +commit cffe3dcc8991cd7c457a9c1a9f41055aa9ea3436 +Author: Alex Deucher +Date: Fri Mar 14 14:37:43 2008 -0400 + + R3xx: VS WIP + +commit b73f52a50dfd6ff8d92f04d6b510c39582c6ac67 +Author: Alex Deucher +Date: Fri Mar 14 14:20:49 2008 -0400 + + R3xx/R5xx: enable VS for mask texture + +commit 569a14ca9be1e18fe9921edc816ac3dc32d6cca7 +Author: Alex Deucher +Date: Fri Mar 14 13:32:12 2008 -0400 + + R3xx/R5xx: Fix magic numbers in vertex shaders + +commit 4878997529601d62e257aa1c9112bd460561de73 +Author: Alex Deucher +Date: Thu Mar 13 21:23:40 2008 -0400 + + R3xx: make sure to set the FS code size correctly + +commit 22f46b88ef05afb6a6b6d70007ac4980a446430e +Author: Alex Deucher +Date: Thu Mar 13 20:25:33 2008 -0400 + + R3xx: attempt to setup the rasterizer properly for mask texture + + Not working yet + +commit 081fc9e892fa3d2e07b7db65b2e2719646255463 +Author: Alex Deucher +Date: Thu Mar 13 18:38:26 2008 -0400 + + R3xx: more mask work + +commit 2bf0236c03538ace3ce6d0e68f0829fc47d1385b +Author: Alex Deucher +Date: Thu Mar 13 18:32:00 2008 -0400 + + R3xx: enable composite for non-mask cases + +commit 74286ba41302107d2fc626fee2181f7c4bc18164 +Author: Alex Deucher +Date: Thu Mar 13 18:25:32 2008 -0400 + + R3xx: add basic mask support + +commit a2bbe10d866567911b68f222b4758624bfe9bf84 +Author: Alex Deucher +Date: Thu Mar 13 18:16:53 2008 -0400 + + R300: setup source selects and output swizzling + +commit b9974ecce7d1932595226004858b08a7a6b188dc +Author: Alex Deucher +Date: Thu Mar 13 17:35:38 2008 -0400 + + R3xx: set the texture id and add some register info + +commit 0ef700b7da5e554a0d0d166f3fde85ff45c9eb1f +Author: Alex Deucher +Date: Thu Mar 13 17:02:25 2008 -0400 + + R3xx/R5xx: enable blending + +commit b35c09a597c93a1d9f06ef0091c96822b0653f98 +Author: Dave Airlie +Date: Thu Mar 13 18:42:29 2008 +1000 + + xv: fixup XAA on r500 textured video + + the XAA area should never end up tiled. This may break with nooffscreen pixmaps + +commit d4446461c3630caff166456c351ace34f57cc119 +Author: Matt Turner +Date: Tue Mar 11 21:20:53 2008 -0400 + + Properly fix uninitialized variables warnings + + According to commit 9fd13e6773371c82b9799a5bda7c96ffa5cafe8c to + xf86-video-intel by Kristian Høgsberg, there is a better way to fix the + possibly initialized variables warnings. This patch will use Kristian's fix. + +commit 20adfd7390d9b1f100e0c4a14f175377b8335c82 +Author: Alex Deucher +Date: Tue Mar 11 20:09:35 2008 -0400 + + RADEON: enable output attributes that require a modeset immediately + + This should fix bug 14915 + +commit 53ba7f5771b0b53fb0d3bc29d64bdd3813756d10 +Author: Alex Deucher +Date: Tue Mar 11 19:12:40 2008 -0400 + + RADEON: fix vblank interrupts after VT switch or suspend/resume + +commit e946c097f0438afbea6f3dd37ee39d67d415708c +Author: Matt Turner +Date: Tue Mar 11 19:07:58 2008 -0400 + + [PATCH] Fix a few warnings + +commit 8e160508520c0a24ca90aad182f296461ca0d9b6 +Author: Alex Deucher +Date: Tue Mar 11 18:11:13 2008 -0400 + + DCE3: add support for PCIEPHY (untested) + +commit fbded88a2925f9f049936dad0736721e7b84a6ee +Author: Alex Deucher +Date: Tue Mar 11 14:10:31 2008 -0400 + + ATOM: remove some cruft + +commit 3263f6e4a410281d620c288a92bb4521f7b6fc06 +Author: Alex Deucher +Date: Tue Mar 11 14:05:48 2008 -0400 + + DCE3: enable DPMS on DIG ports + +commit eb90e235b58c94f3d4d75394725ab2fe246a42ff +Author: Alex Deucher +Date: Tue Mar 11 13:53:54 2008 -0400 + + DCE3: adjust PLL for DCE3 chips + + this fixes stability issues on digital outputs and certain modes. + +commit 552615ccc5360baafb8bb41698c1ca27816fd4b2 +Author: Alex Deucher +Date: Tue Mar 11 13:38:29 2008 -0400 + + ATOMBIOS: enable load detection by default on both DACs + + Load detection is reliable with atom, so enable it by default + on both DACA and DACB, rather than just DACA. + +commit 78b10487cf222c96f8944ba25e2ea970506b3535 +Author: Alex Deucher +Date: Tue Mar 11 13:16:00 2008 -0400 + + DCE3: add output attribute to enable/disable coherent mode + + Enabled by default. The TMDS transmitter can be programmed + slightly differently depending on the chips in the panel. If you + have problems with tmds on a particular panel, try disabling it. + +commit d20be31c46fbec623af4c3628a7c603ceacf500f +Author: Alex Deucher +Date: Mon Mar 10 21:05:43 2008 -0400 + + RV550: MC setup is like RV515 not RV530 + +commit 38606b08b68842fbcc81c233009c1117269f3be9 +Author: Matthieu Herrb +Date: Sat Mar 8 23:22:59 2008 +0100 + + Makefile.am: nuke RCS Id + +commit 9d710ee1a44cf2f3a948fbdbe17ef09521cbe744 +Author: Alex Deucher +Date: Fri Mar 7 15:09:14 2008 -0500 + + AVIVO: clean up some unused variables + +commit c28c30c9f3d7bfebfd56a5c982c96f0090982054 +Author: Alex Deucher +Date: Fri Mar 7 14:10:49 2008 -0500 + + RADEON: Fix crash in last commit + +commit c3a3635865e380c784a226c8ead069d4716d6b75 +Author: Dave Airlie +Date: Thu Mar 6 20:17:45 2008 -0500 + + RADEON: fix tiling/interlaced interaction with randr 1.2 + +commit df1b94dc4eb1f35b636dbf2ec0ab1c2da9937c0d +Author: Alex Deucher +Date: Thu Mar 6 19:22:08 2008 -0500 + + DCE3: Ignore outputs with DIN connectors for now + +commit cb2dc19387c7b6494c47c76d683cf38a48700768 +Author: Alex Deucher +Date: Thu Mar 6 18:33:12 2008 -0500 + + AVIVO: fix typo from a previous commit + + Leave tv dpms hook disabled or you may get bad interactions + with the shared DAC + +commit 77355de48057e5e7e0d5b3f3cf5a7a92220a53b1 +Author: Alex Deucher +Date: Thu Mar 6 17:46:00 2008 -0500 + + AVIVO: don't add outputs for invalid connectors + +commit 600dbe080997a01ceaf6be86723189d518bc1281 +Merge: 594743a... 5b7875d... +Author: Alex Deucher +Date: Thu Mar 6 17:31:37 2008 -0500 + + Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati + +commit 594743a99811a8b0f391412892414fcd158eeb56 +Author: Alex Deucher +Date: Thu Mar 6 17:30:21 2008 -0500 + + AVIVO: fix up memsize detection for IGP chips + +commit 5b7875d0cbfbdbcd1515c4e942d30de298b49dff +Author: Doug Chapman +Date: Thu Mar 6 14:31:06 2008 -0500 + + Bug #14826: Fix a bogus check around xf86SetOperatingState. + +commit 651fe23f4c650ed91843dec48db24e18e8b91219 +Merge: 3de2dc8... 766f464... +Author: Adam Jackson +Date: Thu Mar 6 14:28:27 2008 -0500 + + Merge branch 'master' of git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati + +commit 41171c25cd235bafad26bcbabced16ead4b8c54b +Author: Alex Deucher +Date: Thu Mar 6 14:05:18 2008 -0500 + + DCE3.0: add support for crtc memreq table + +commit 766f464dfdfccadef23e4232f2bce5db22195513 +Author: Alex Deucher +Date: Thu Mar 6 13:35:43 2008 -0500 + + RADEON: take 2 on proper pragma pack support for bsds + + See bug 14594. Based on suggestion by Henry Zhao + +commit a842ce9ca6494e724a7828cead9b61c9ef02b6aa +Author: Alex Deucher +Date: Thu Mar 6 12:32:18 2008 -0500 + + DCE3.0: Minor fixups + +commit 8a1ba374033591c725a78923aa30829e4de2a5ae +Author: Alex Deucher +Date: Thu Mar 6 09:53:51 2008 -0500 + + RADEON: option to override TVDAC adj values from bios with driver defaults + + If you have a washed out image on the tv dac, try this option. + Option "DefaultTVDACAdj" "TRUE" + +commit 0ed48f8f651a28e189f9fee8c6b593da0178d21c +Author: Alex Deucher +Date: Wed Mar 5 18:41:01 2008 -0500 + + AVIVO: Initial support for DCE 3.0 using atombios + + DACs are working well, DIG support (DVI, HDMI, LVDS, etc.) + still has some issues. + +commit 2901e99f1942842856cd39c1dcc8b22f3cf7d9e3 +Author: Alex Deucher +Date: Wed Mar 5 10:40:06 2008 -0500 + + RADEON: fix fetching of dac2 adj values from newer bios tables + +commit 74eb981287d76836327830bd51272f605a07e0cc +Author: Alex Deucher +Date: Mon Mar 3 12:02:44 2008 -0500 + + ATOMBIOS: fix atombios parser support on *bsd + + bsd requires a different pragma pack than Linux. + See bug 14594. + +commit f7769ea86e265f347eb58c517ccb5ef8b35eec27 +Author: Paulo Cesar Pereira de Andrade +Date: Sun Mar 2 14:49:21 2008 -0500 + + [PATCH] Ensure symbols used by other modules are visible. + + The xf86-video-ati drivers are one of the cases where LoaderSymbol is + widely used in some obscure ways. This patch fixes the problem, and + allows compiling with -fvisibility=hidden. + +commit a4398ac3ad77216f2c8aa628425bef5f2912a0a9 +Author: Alex Deucher +Date: Sat Mar 1 18:52:26 2008 -0500 + + RS6xx: change isIGP checks to CHIP_FAMILY_RS690 + + these paths are only relevant on RS6xx chips + +commit 67d4d04836c05293b844bc505f303cfb04c0f8a4 +Author: Alex Deucher +Date: Sat Mar 1 18:33:18 2008 -0500 + + RADEON: use xf86SetDesiredModes() in screeninit and enterVT + + this should restore the proper output state on VT switches + +commit be0858a84fbdf74c0b844f462933a221d48c707d +Author: Maciej Cencora +Date: Sat Mar 1 18:11:58 2008 -0500 + + RADEON: remove driver rec copies of mc info, use save rec directly + + info->mc_* were used and the immediately copied into info->ModeReg + ones. Just use the ModeReg copies directly. + +commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94 +Author: Alex Deucher +Date: Sat Mar 1 16:23:51 2008 -0500 + + RADEON: memmap rework 1 + + Don't restore memmap regs on every mode switch. + Just do memmap save/restore/setup on server start and VT switch. + +commit 1f6a23000001f3d1c21b5c04f94714a8caa7aa8b +Author: Alex Deucher +Date: Sat Mar 1 15:53:42 2008 -0500 + + RADEON: only restore legacy dac regs on legacy radeons + +commit dee6cef8e62d0651c00319e03eea92940fd24aa4 +Author: Alex Deucher +Date: Sat Mar 1 14:39:32 2008 -0500 + + RS4xx: enable exa render accel and textured video + + RS6xx paths seem to work fine on RS4xx + +commit 129f737efe4e8d1a368e7db4b063bdcd9339cb09 +Author: Alex Deucher +Date: Sat Mar 1 14:32:30 2008 -0500 + + AVIVO: save/restore regs by block + + Save/Restore the entire block for each output. + This should fix VT switch problems. + +commit b069aadaa63a95d7a71b5cfbab83577b49501094 +Author: Alex Deucher +Date: Fri Feb 29 22:36:02 2008 -0500 + + AVIVO: LVDS panels need dithering enabled + + Fixes bug 14760 + +commit fe87bdee815372b4b4d7d4c705e34681625b90f2 +Author: Alex Deucher +Date: Fri Feb 29 13:10:13 2008 -0500 + + AVIVO: disable pageflipping on avivo chips until we have proper drm support + +commit fb3678c7f511d539a51cd090cb8b5041d7d2ba26 +Author: Alex Deucher +Date: Fri Feb 29 13:01:21 2008 -0500 + + R5xx: fix register count when sending fragment program for textured video + +commit a66d37d1a896ec934989592457c2beff8e6f1639 +Author: Alex Deucher +Date: Fri Feb 29 04:07:05 2008 -0500 + + fix off-by-one in last commit + +commit e56062960be0c8d3947861dd5e0691fce6516b99 +Author: Alex Deucher +Date: Thu Feb 28 19:16:39 2008 -0500 + + AVIVO: save/restore scaler regs + +commit ae1c39a9b3e666404d0931679c9078c2e125a8bc +Author: Alex Deucher +Date: Thu Feb 28 18:53:55 2008 -0500 + + RS6xx: rework output parsing + + Turns out it's not as complex as I originially thought. + IGP chips just have non-standard GPIO entires for DDC. + +commit d8d6c9fe4ae7e1ab67dd041a251e901d97c29ed6 +Author: Alex Deucher +Date: Thu Feb 28 17:01:14 2008 -0500 + + RS6xx: fix typos in previous commit + + Noted by Maciej Cencora on IRC + +commit 46547ae8bdbc5c10f1fd028b95ec4c5c31a5b318 +Author: Alex Deucher +Date: Thu Feb 28 14:29:30 2008 -0500 + + AVIVO: disable dithering on DFPs + + This should fix the color banding some people have noticed. + Also save/restore DDIA regs on RS6xx + +commit 72a53d6f20ac29b3baddb7d8af04f19b76d2e04f +Author: Michel Dänzer +Date: Thu Feb 28 17:38:04 2008 +0100 + + Handle EXA coordinate limits more cleverly. + + Generally set the 2D engine limits, and only enforce the 3D engine limits in the + CheckComposite hook. This should still prevent useless migration of pixmaps the + 3D engine can't handle but allows for basic acceleration of bigger ones. + + Fixes http://bugs.freedesktop.org/show_bug.cgi?id=14708 . + +commit 5249f450a2487475a95531603cc8668db2c21c33 +Author: Michel Dänzer +Date: Thu Feb 28 12:23:58 2008 +0100 + + Fix 16 bit packed YUV XVideo playback on big endian systems with DRI disabled. + + http://bugs.freedesktop.org/show_bug.cgi?id=14668 + +commit e40d75fd8b2aece9dae8076fac822a4a83025fb2 +Author: Alex Deucher +Date: Wed Feb 27 22:53:10 2008 -0500 + + R500: fragment program clean up and magic number conversion + +commit 140dadba36b2191f0e18e41dd987785abd5f55d2 +Author: Alex Deucher +Date: Wed Feb 27 22:21:12 2008 -0500 + + R300: fix up magic numbers in fragment program + +commit e521476bb5e2dfabc93747e43eb911a8a101357e +Author: Alex Deucher +Date: Wed Feb 27 21:26:55 2008 -0500 + + R300/R400: bump up the clip limits for textured video + + This allows up to 2560x2560 (hw limit) + +commit 10db46f11d7e1c055c9ad6034c65ad163dad17dc +Author: Alex Deucher +Date: Wed Feb 27 15:28:50 2008 -0500 + + AVIVO: make sure we select the right LUT for each crtc + +commit ea944f38dcfd871b27345698afea1cb986ecb049 +Author: Alex Deucher +Date: Wed Feb 27 14:37:52 2008 -0500 + + R300+: update RADEONCP_REFRESH() to reflect new location of scissor regs + +commit b865faf95666e2172c3eec143f77fe9c524e4983 +Author: Alex Deucher +Date: Wed Feb 27 14:05:44 2008 -0500 + + R100/R200: move r100/r200 specific 3D setup into appropriate blocks + + R3xx+ doesn't have these regs. + +commit 3de2dc88cf26ff5932f11cecdf975777b8aa2a4a +Author: Adam Jackson +Date: Wed Jan 16 14:55:05 2008 -0500 + + Bump CRTC size limits on AVIVO chips so 30" displays work without tweaking. + + Note that the CRTC size limits we're using right now are _not_ the + hardware limits, they're just heuristics until we can resize the front + buffer properly. diff --git a/configure.ac b/configure.ac -index 2412d4f..ab8bd97 100644 +index 2412d4f..a63f5e8 100644 --- a/configure.ac +++ b/configure.ac -@@ -176,6 +176,14 @@ AC_CHECK_DECL(xf86_crtc_clip_video_helper, +@@ -176,6 +176,18 @@ AC_CHECK_DECL(xf86_crtc_clip_video_helper, #include "xf86i2c.h" #include "xf86Crtc.h"]) @@ -13,11 +1505,15 @@ index 2412d4f..ab8bd97 100644 + #include + #include ]) + ++AC_CHECK_DECL(pci_device_enable, ++ [AC_DEFINE(HAVE_PCI_DEVICE_ENABLE, 1, [Have pci_device_enable prototype])], ++ [], ++ [#include ]) + AC_CHECK_DECL(XSERVER_LIBPCIACCESS, [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no], [#include "xorg-server.h"]) -@@ -232,6 +240,11 @@ if test "x$XSERVER_LIBPCIACCESS" = xyes; then +@@ -232,6 +244,11 @@ if test "x$XSERVER_LIBPCIACCESS" = xyes; then fi AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes) @@ -3871,7 +5367,7 @@ index aba3c0f..9363c29 100644 #endif /* XF86DRI */ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 8b2f167..92777c6 100644 +index 8b2f167..778d43e 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -158,17 +158,32 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) @@ -3969,11 +5465,32 @@ index 8b2f167..92777c6 100644 ~(RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | -@@ -355,7 +370,54 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -355,7 +370,78 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->CurrentLayout.pixel_code, info->CurrentLayout.bitsPerPixel); - OUTREG(RADEON_RB3D_CNTL, 0); ++#ifdef XF86DRI ++ if (IS_R300_3D | IS_R500_3D) { ++ drmRadeonGetParam np; ++ int num_pipes; ++ ++ memset(&np, 0, sizeof(np)); ++ np.param = RADEON_PARAM_NUM_GB_PIPES; ++ np.value = &num_pipes; ++ ++ if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np, ++ sizeof(np)) < 0) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "Failed to determine num pipes from DRM, falling back to " ++ "manual look-up!\n"); ++ info->num_gb_pipes = 0; ++ } else { ++ info->num_gb_pipes = num_pipes; ++ } ++ } ++#endif ++ + if ((info->ChipFamily == CHIP_FAMILY_RV410) || + (info->ChipFamily == CHIP_FAMILY_R420) || + (info->ChipFamily == CHIP_FAMILY_RS600) || @@ -3982,14 +5499,13 @@ index 8b2f167..92777c6 100644 + (info->ChipFamily == CHIP_FAMILY_RS400) || + (info->ChipFamily == CHIP_FAMILY_RS480) || + IS_R500_3D) { -+ uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); + if (info->num_gb_pipes == 0) { ++ uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); ++ + info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, -+ "%s: num pipes is %d\n", __FUNCTION__, info->num_gb_pipes); ++ if (IS_R500_3D) ++ OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); + } -+ if (IS_R500_3D) -+ OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); + } else { + if (info->num_gb_pipes == 0) { + if ((info->ChipFamily == CHIP_FAMILY_R300) || @@ -4003,6 +5519,10 @@ index 8b2f167..92777c6 100644 + } + } + ++ if (IS_R300_3D | IS_R500_3D) ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "num pipes is %d\n", info->num_gb_pipes); ++ + if (IS_R300_3D | IS_R500_3D) { + uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); + @@ -4025,7 +5545,7 @@ index 8b2f167..92777c6 100644 RADEONEngineReset(pScrn); -@@ -390,8 +452,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -390,8 +476,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->sc_bottom = RADEON_DEFAULT_SC_BOTTOM_MAX; info->re_top_left = 0x00000000; @@ -4040,7 +5560,7 @@ index 8b2f167..92777c6 100644 info->aux_sc_cntl = 0x00000000; #endif -@@ -617,11 +683,11 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -617,11 +707,11 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) * about tiling etc. */ void @@ -4055,7 +5575,7 @@ index 8b2f167..92777c6 100644 *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10; *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch; -@@ -632,21 +698,21 @@ RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, +@@ -632,21 +722,21 @@ RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, * framebuffer. Returns the address where the data can be written to and sets * the dstPitch and hpass variables as required. */ @@ -4082,7 +5602,7 @@ index 8b2f167..92777c6 100644 RING_LOCALS; if ( *h == 0 ) -@@ -719,7 +785,7 @@ RADEONHostDataBlit( +@@ -719,7 +809,7 @@ RADEONHostDataBlit( OUT_RING( *hpass << 16 | (*bufPitch / cpp) ); OUT_RING( dwords ); @@ -4091,7 +5611,7 @@ index 8b2f167..92777c6 100644 __count += dwords; ADVANCE_RING(); -@@ -730,7 +796,7 @@ RADEONHostDataBlit( +@@ -730,7 +820,7 @@ RADEONHostDataBlit( return ret; } @@ -4100,7 +5620,7 @@ index 8b2f167..92777c6 100644 { switch(swap) { case RADEON_HOST_DATA_SWAP_HDW: -@@ -785,8 +851,8 @@ void +@@ -785,8 +875,8 @@ void RADEONHostDataBlitCopyPass( ScrnInfoPtr pScrn, unsigned int cpp, @@ -4111,7 +5631,7 @@ index 8b2f167..92777c6 100644 unsigned int hpass, unsigned int dstPitch, unsigned int srcPitch -@@ -1075,7 +1141,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1075,7 +1165,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) /* Reserve space for textures */ info->textureOffset = ((info->FbMapSize - info->textureSize + RADEON_BUFFER_ALIGN) & @@ -4120,7 +5640,7 @@ index 8b2f167..92777c6 100644 } /* Reserve space for the shared depth -@@ -1083,7 +1149,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1083,7 +1173,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) */ info->depthOffset = ((info->textureOffset - depthSize + RADEON_BUFFER_ALIGN) & @@ -4129,7 +5649,7 @@ index 8b2f167..92777c6 100644 /* Reserve space for the shared back buffer */ if (info->noBackBuffer) { -@@ -1091,7 +1157,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +@@ -1091,7 +1181,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) } else { info->backOffset = ((info->depthOffset - bufferSize + RADEON_BUFFER_ALIGN) & @@ -4205,7 +5725,7 @@ index e3b37c1..3c0b8a0 100644 a->SetupForCPUToScreenTexture2 = diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index 88c220b..fb7d002 100644 +index 88c220b..5cc21d5 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -35,6 +35,8 @@ @@ -4237,6 +5757,15 @@ index 88c220b..fb7d002 100644 if ((fb_base + fb_size) > (start + size)) { xf86DrvMsg(handle->scrnIndex, X_WARNING, "%s: FW FB scratch area %i (size: %i)" +@@ -490,7 +492,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, + } + + # ifdef ATOM_BIOS_PARSER +-static Bool ++Bool + rhdAtomASICInit(atomBiosHandlePtr handle) + { + ASIC_INIT_PS_ALLOCATION asicInit; @@ -517,25 +519,52 @@ rhdAtomASICInit(atomBiosHandlePtr handle) return FALSE; } @@ -4305,7 +5834,92 @@ index 88c220b..fb7d002 100644 } # endif -@@ -658,7 +687,7 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, +@@ -546,69 +575,30 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, + { + int scrnIndex = data->val; + RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]); +- unsigned char *ptr; + atomDataTablesPtr atomDataPtr; + unsigned int cmd_offset; + atomBiosHandlePtr handle = NULL; + unsigned int BIOSImageSize = 0; + data->atomhandle = NULL; + +- //RHDFUNCI(scrnIndex); +- +- /*if (info->BIOSCopy) { +- xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from INT10\n"); +- ptr = info->BIOSCopy; +- info->BIOSCopy = NULL; +- +- BIOSImageSize = ptr[2] * 512; +- if (BIOSImageSize > legacyBIOSMax) { +- xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n"); +- return ATOM_FAILED; +- } +- } else*/ { +- /*if (!xf86IsEntityPrimary(info->entityIndex)) { +- if (!(BIOSImageSize = RHDReadPCIBios(info, &ptr))) +- return ATOM_FAILED; +- } else*/ { +- int read_len; +- unsigned char tmp[32]; +- xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from legacy VBIOS location\n"); +- if (xf86ReadBIOS(legacyBIOSLocation, 0, tmp, 32) < 0) { +- xf86DrvMsg(scrnIndex,X_ERROR, +- "Cannot obtain POSTed BIOS header\n"); +- return ATOM_FAILED; +- } +- BIOSImageSize = tmp[2] * 512; +- if (BIOSImageSize > legacyBIOSMax) { +- xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n"); +- return ATOM_FAILED; +- } +- if (!(ptr = xcalloc(1,BIOSImageSize))) { +- xf86DrvMsg(scrnIndex,X_ERROR, +- "Cannot allocate %i bytes of memory " +- "for BIOS image\n",BIOSImageSize); +- return ATOM_FAILED; +- } +- if ((read_len = xf86ReadBIOS(legacyBIOSLocation, 0, ptr, BIOSImageSize) +- < 0)) { +- xf86DrvMsg(scrnIndex,X_ERROR,"Cannot read POSTed BIOS\n"); +- goto error; +- } +- } +- } ++#ifdef XSERVER_LIBPCIACCESS ++ BIOSImageSize = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; ++#else ++ BIOSImageSize = RADEON_VBIOS_SIZE; ++#endif + + if (!(atomDataPtr = xcalloc(1, sizeof(atomDataTables)))) { + xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for " + "ATOM BIOS data tabes\n"); + goto error; + } +- if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr, &cmd_offset, BIOSImageSize)) ++ if (!rhdAtomGetDataTable(scrnIndex, info->VBIOS, atomDataPtr, &cmd_offset, BIOSImageSize)) + goto error1; + if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) { + xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n"); + goto error1; + } +- handle->BIOSBase = ptr; ++ handle->BIOSBase = info->VBIOS; + handle->atomDataPtr = atomDataPtr; + handle->cmd_offset = cmd_offset; + handle->scrnIndex = scrnIndex; +@@ -636,7 +626,6 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, + error1: + xfree(atomDataPtr); + error: +- xfree(ptr); + return ATOM_FAILED; + } + +@@ -658,7 +647,7 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4314,7 +5928,7 @@ index 88c220b..fb7d002 100644 //RHDFUNC(handle); atomDataPtr = handle->atomDataPtr; -@@ -683,7 +712,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, +@@ -683,7 +672,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4323,7 +5937,7 @@ index 88c220b..fb7d002 100644 int idx = *val; atomDataPtr = handle->atomDataPtr; -@@ -778,7 +807,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) +@@ -778,7 +767,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) } static unsigned char* @@ -4332,7 +5946,7 @@ index 88c220b..fb7d002 100644 { unsigned char *EDIDBlock; -@@ -848,7 +877,7 @@ rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, +@@ -848,7 +837,7 @@ rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4341,7 +5955,7 @@ index 88c220b..fb7d002 100644 DisplayModePtr last = NULL; DisplayModePtr new = NULL; DisplayModePtr first = NULL; -@@ -938,7 +967,7 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, +@@ -938,7 +927,7 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4350,7 +5964,7 @@ index 88c220b..fb7d002 100644 unsigned long offset; //RHDFUNC(handle); -@@ -1002,8 +1031,8 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, +@@ -1002,8 +991,8 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4361,7 +5975,7 @@ index 88c220b..fb7d002 100644 //RHDFUNC(handle); -@@ -1112,8 +1141,8 @@ rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, +@@ -1112,8 +1101,8 @@ rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4372,7 +5986,7 @@ index 88c220b..fb7d002 100644 //RHDFUNC(handle); -@@ -1169,8 +1198,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, +@@ -1169,8 +1158,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4383,7 +5997,7 @@ index 88c220b..fb7d002 100644 unsigned short size; //RHDFUNC(handle); -@@ -1209,8 +1238,8 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, +@@ -1209,8 +1198,8 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -4394,7 +6008,7 @@ index 88c220b..fb7d002 100644 //RHDFUNC(handle); -@@ -1399,7 +1428,7 @@ const int object_connector_convert[] = +@@ -1399,7 +1388,7 @@ const int object_connector_convert[] = CONNECTOR_NONE, CONNECTOR_NONE, CONNECTOR_NONE, @@ -4403,7 +6017,7 @@ index 88c220b..fb7d002 100644 }; static void -@@ -1434,13 +1463,13 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle, +@@ -1434,13 +1423,13 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle, } static RADEONI2CBusRec @@ -4419,7 +6033,7 @@ index 88c220b..fb7d002 100644 memset(&i2c, 0, sizeof(RADEONI2CBusRec)); i2c.valid = FALSE; -@@ -1495,10 +1524,11 @@ Bool +@@ -1495,10 +1484,11 @@ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); @@ -4432,7 +6046,7 @@ index 88c220b..fb7d002 100644 int i, j, ddc_line = 0; atomDataPtr = info->atomBIOS->atomDataPtr; -@@ -1507,7 +1537,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1507,7 +1497,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if (crev < 2) return FALSE; @@ -4441,7 +6055,7 @@ index 88c220b..fb7d002 100644 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) ((char *)&atomDataPtr->Object_Header->sHeader + atomDataPtr->Object_Header->usConnectorObjectTableOffset); -@@ -1515,7 +1545,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1515,7 +1505,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) for (i = 0; i < con_obj->ucNumberOfObjects; i++) { ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; ATOM_COMMON_RECORD_HEADER *Record; @@ -4450,7 +6064,7 @@ index 88c220b..fb7d002 100644 int record_base; obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; -@@ -1527,18 +1557,42 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1527,18 +1517,42 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) ((char *)&atomDataPtr->Object_Header->sHeader + con_obj->asObjects[i].usSrcDstTableOffset); @@ -4498,7 +6112,7 @@ index 88c220b..fb7d002 100644 switch(sobj_id) { case ENCODER_OBJECT_ID_INTERNAL_LVDS: info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX); -@@ -1548,6 +1602,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1548,6 +1562,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX); info->BiosConnector[i].TMDSType = TMDS_INT; break; @@ -4512,7 +6126,7 @@ index 88c220b..fb7d002 100644 case ENCODER_OBJECT_ID_INTERNAL_TMDS2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX); -@@ -1560,7 +1621,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1560,7 +1581,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: @@ -4527,7 +6141,7 @@ index 88c220b..fb7d002 100644 info->BiosConnector[i].DACType = DAC_PRIMARY; break; case ENCODER_OBJECT_ID_INTERNAL_DAC2: -@@ -1568,7 +1635,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1568,7 +1595,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || info->BiosConnector[i].ConnectorType == CONNECTOR_STV || info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) @@ -4537,7 +6151,7 @@ index 88c220b..fb7d002 100644 else info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); info->BiosConnector[i].DACType = DAC_TVDAC; -@@ -1588,7 +1656,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1588,7 +1616,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) ErrorF("record type %d\n", Record->ucRecordType); switch (Record->ucRecordType) { case ATOM_I2C_RECORD_TYPE: @@ -4546,7 +6160,7 @@ index 88c220b..fb7d002 100644 (ATOM_I2C_RECORD *)Record, &ddc_line); info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); -@@ -1708,12 +1776,28 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ +@@ -1708,12 +1736,28 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ return TRUE; } @@ -4576,7 +6190,7 @@ index 88c220b..fb7d002 100644 int i, j; atomDataPtr = info->atomBIOS->atomDataPtr; -@@ -1745,13 +1829,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1745,13 +1789,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) info->BiosConnector[i].valid = TRUE; info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; @@ -4597,7 +6211,7 @@ index 88c220b..fb7d002 100644 info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; /* don't assign a gpio for tv */ -@@ -1759,14 +1844,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1759,14 +1804,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) (i == ATOM_DEVICE_TV2_INDEX) || (i == ATOM_DEVICE_CV_INDEX)) info->BiosConnector[i].ddc_i2c.valid = FALSE; @@ -4619,7 +6233,7 @@ index 88c220b..fb7d002 100644 } else info->BiosConnector[i].ddc_i2c = RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); -@@ -1774,16 +1861,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1774,16 +1821,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) if (i == ATOM_DEVICE_DFP1_INDEX) info->BiosConnector[i].TMDSType = TMDS_INT; else if (i == ATOM_DEVICE_DFP2_INDEX) { @@ -4643,7 +6257,7 @@ index 88c220b..fb7d002 100644 info->BiosConnector[i].TMDSType = TMDS_NONE; /* Always set the connector type to VGA for CRT1/CRT2. if they are -@@ -1816,6 +1902,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1816,6 +1862,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) } else { info->BiosConnector[i].hpd_mask = 0; } @@ -4653,7 +6267,7 @@ index 88c220b..fb7d002 100644 } /* CRTs/DFPs may share a port */ -@@ -1859,689 +1948,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1859,689 +1908,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) return TRUE; } @@ -5343,7 +6957,7 @@ index 88c220b..fb7d002 100644 # ifdef ATOM_BIOS_PARSER static AtomBiosResult rhdAtomExec (atomBiosHandlePtr handle, -@@ -2566,9 +1972,9 @@ rhdAtomExec (atomBiosHandlePtr handle, +@@ -2566,9 +1932,9 @@ rhdAtomExec (atomBiosHandlePtr handle, __func__); return ATOM_FAILED; } @@ -5355,7 +6969,7 @@ index 88c220b..fb7d002 100644 } ret = ParseTableWrapper(pspace, idx, handle, handle->BIOSBase, -@@ -2673,7 +2079,7 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) +@@ -2673,7 +2039,7 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) usleep(delay); @@ -5364,7 +6978,7 @@ index 88c220b..fb7d002 100644 } UINT32 -@@ -2686,7 +2092,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx) +@@ -2686,7 +2052,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx) CAILFUNC(CAIL); ret = INREG(idx << 2); @@ -5373,7 +6987,7 @@ index 88c220b..fb7d002 100644 return ret; } -@@ -2699,7 +2105,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) +@@ -2699,7 +2065,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) CAILFUNC(CAIL); OUTREG(idx << 2,data); @@ -5382,7 +6996,7 @@ index 88c220b..fb7d002 100644 } UINT32 -@@ -2712,12 +2118,12 @@ CailReadFBData(VOID* CAIL, UINT32 idx) +@@ -2712,12 +2078,12 @@ CailReadFBData(VOID* CAIL, UINT32 idx) CAILFUNC(CAIL); if (((atomBiosHandlePtr)CAIL)->fbBase) { @@ -5400,7 +7014,7 @@ index 88c220b..fb7d002 100644 } else { xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); -@@ -2731,13 +2137,13 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) +@@ -2731,13 +2097,13 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) { CAILFUNC(CAIL); @@ -5418,7 +7032,7 @@ index 88c220b..fb7d002 100644 } else xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); -@@ -2752,7 +2158,7 @@ CailReadMC(VOID *CAIL, ULONG Address) +@@ -2752,7 +2118,7 @@ CailReadMC(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = INMC(pScrn, Address); @@ -5427,7 +7041,7 @@ index 88c220b..fb7d002 100644 return ret; } -@@ -2762,7 +2168,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) +@@ -2762,7 +2128,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); @@ -5436,7 +7050,7 @@ index 88c220b..fb7d002 100644 OUTMC(pScrn, Address, data); } -@@ -2793,13 +2199,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) +@@ -2793,13 +2159,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) switch (size) { case 8: @@ -5453,7 +7067,7 @@ index 88c220b..fb7d002 100644 break; default: xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, -@@ -2808,7 +2214,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) +@@ -2808,7 +2174,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) return; break; } @@ -5462,7 +7076,7 @@ index 88c220b..fb7d002 100644 } -@@ -2818,16 +2224,16 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) +@@ -2818,16 +2184,16 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; CAILFUNC(CAIL); @@ -5483,7 +7097,7 @@ index 88c220b..fb7d002 100644 break; default: xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, -@@ -2846,7 +2252,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) +@@ -2846,7 +2212,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = RADEONINPLL(pScrn, Address); @@ -5492,7 +7106,7 @@ index 88c220b..fb7d002 100644 return ret; } -@@ -2856,7 +2262,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) +@@ -2856,7 +2222,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); @@ -5502,7 +7116,7 @@ index 88c220b..fb7d002 100644 } diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h -index 9cb279e..b4a19aa 100644 +index 9cb279e..fe7044d 100644 --- a/src/radeon_atombios.h +++ b/src/radeon_atombios.h @@ -98,7 +98,7 @@ typedef struct AtomFb { @@ -5527,7 +7141,17 @@ index 9cb279e..b4a19aa 100644 extern Bool RADEONGetATOMTVInfo(xf86OutputPtr output); -@@ -236,7 +242,7 @@ typedef struct _atomBiosHandle { +@@ -125,6 +131,9 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); + extern void + atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor); + ++Bool ++rhdAtomASICInit(atomBiosHandlePtr handle); ++ + # include "xf86int10.h" + # ifdef ATOM_BIOS_PARSER + # define INT8 INT8 +@@ -236,7 +245,7 @@ typedef struct _atomBiosHandle { atomDataTablesPtr atomDataPtr; unsigned int cmd_offset; pointer *scratchBase; @@ -5550,20 +7174,282 @@ index 259366c..3e7ae01 100644 #define INT32 INT32 #include "CD_Common_Types.h" diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 8e6bd8d..fa09aae 100644 +index 8e6bd8d..bc041c3 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c -@@ -75,7 +75,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -65,17 +65,216 @@ typedef enum + CONNECTOR_UNSUPPORTED_LEGACY + } RADEONLegacyConnectorType; + ++static Bool ++radeon_read_bios(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++#ifdef XSERVER_LIBPCIACCESS ++ if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Failed to read PCI ROM!\n"); ++ return FALSE; ++ } ++#else ++ xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); ++ if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Video BIOS not detected in PCI space!\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Attempting to read Video BIOS from " ++ "legacy ISA space!\n"); ++ info->BIOSAddr = 0x000c0000; ++ xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, ++ RADEON_VBIOS_SIZE, info->VBIOS); ++ } ++#endif ++ if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) ++ return FALSE; ++ else ++ return TRUE; ++} ++ ++static Bool ++radeon_read_unposted_bios(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ Bool ret; ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); ++ uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); ++ uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); ++ uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); ++ uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); ++ uint32_t rom_cntl = INREG(R600_ROM_CNTL); ++ uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); ++ uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); ++ uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); ++ uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); ++ uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); ++ uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); ++ ++ /* disable VIP */ ++ OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); ++ ++ /* enable the rom */ ++ OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); ++ ++ /* Disable VGA mode */ ++ OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | ++ AVIVO_DVGA_CONTROL_TIMING_SELECT))); ++ OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | ++ AVIVO_DVGA_CONTROL_TIMING_SELECT))); ++ OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); ++ ++ OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | ++ (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | ++ R600_SCK_OVERWRITE)); ++ ++ OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); ++ ++ OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); ++ ++ OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); ++ ++ OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); ++ ++ OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); ++ ++ OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); ++ ++ ret = radeon_read_bios(pScrn); ++ ++ /* restore regs */ ++ OUTREG(RADEON_VIPH_CONTROL, viph_control); ++ OUTREG(RADEON_BUS_CNTL, bus_cntl); ++ OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); ++ OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); ++ OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); ++ OUTREG(R600_ROM_CNTL, rom_cntl); ++ OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); ++ OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); ++ OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); ++ OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); ++ OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); ++ OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); ++ ++ } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { ++ uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); ++ uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); ++ uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); ++ uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); ++ uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); ++ uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); ++ uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); ++ uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); ++ uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); ++ ++ OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | ++ (0xc << RADEON_SCK_PRESCALE_SHIFT))); ++ ++ OUTREG(RADEON_GPIOPAD_A, 0); ++ OUTREG(RADEON_GPIOPAD_EN, 0); ++ OUTREG(RADEON_GPIOPAD_MASK, 0); ++ ++ /* disable VIP */ ++ OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); ++ ++ /* enable the rom */ ++ OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); ++ ++ /* Disable VGA mode */ ++ OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | ++ AVIVO_DVGA_CONTROL_TIMING_SELECT))); ++ OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | ++ AVIVO_DVGA_CONTROL_TIMING_SELECT))); ++ OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); ++ ++ ret = radeon_read_bios(pScrn); ++ ++ /* restore regs */ ++ OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); ++ OUTREG(RADEON_VIPH_CONTROL, viph_control); ++ OUTREG(RADEON_BUS_CNTL, bus_cntl); ++ OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); ++ OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); ++ OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); ++ OUTREG(RADEON_GPIOPAD_A, gpiopad_a); ++ OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); ++ OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); ++ ++ } else { ++ uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); ++ uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); ++ uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); ++ uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); ++ uint32_t crtc2_gen_cntl = 0; ++ uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); ++ uint32_t fp2_gen_cntl = 0; ++ ++ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) ++ fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); ++ ++ if (pRADEONEnt->HasCRTC2) ++ crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); ++ ++ OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | ++ (0xc << RADEON_SCK_PRESCALE_SHIFT))); ++ ++ /* disable VIP */ ++ OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); ++ ++ /* enable the rom */ ++ OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); ++ ++ /* Turn off mem requests and CRTC for both controllers */ ++ OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | ++ (RADEON_CRTC_DISP_REQ_EN_B | ++ RADEON_CRTC_EXT_DISP_EN))); ++ if (pRADEONEnt->HasCRTC2) ++ OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | ++ RADEON_CRTC2_DISP_REQ_EN_B)); ++ ++ /* Turn off CRTC */ ++ OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | ++ (RADEON_CRTC_SYNC_TRISTAT | ++ RADEON_CRTC_DISPLAY_DIS))); ++ ++ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) ++ OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); ++ ++ ret = radeon_read_bios(pScrn); ++ ++ /* restore regs */ ++ OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); ++ OUTREG(RADEON_VIPH_CONTROL, viph_control); ++ OUTREG(RADEON_BUS_CNTL, bus_cntl); ++ OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); ++ if (pRADEONEnt->HasCRTC2) ++ OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); ++ OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); ++ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) ++ OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); ++ } ++ return ret; ++} + + /* Read the Video BIOS block and the FP registers (if applicable). */ +-Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) ++Bool ++RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + int tmp; + unsigned short dptr; #ifdef XSERVER_LIBPCIACCESS - //info->VBIOS = xalloc(info->PciInfo->rom_size); +- //info->VBIOS = xalloc(info->PciInfo->rom_size); - info->VBIOS = xalloc(RADEON_VBIOS_SIZE); + int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; + info->VBIOS = xalloc(size); #else info->VBIOS = xalloc(RADEON_VBIOS_SIZE); #endif -@@ -216,6 +217,55 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -88,25 +287,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + info->BIOSAddr = pInt10->BIOSseg << 4; + (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), + RADEON_VBIOS_SIZE); +- } else { +-#ifdef XSERVER_LIBPCIACCESS +- if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Failed to read PCI ROM!\n"); +- } +-#else +- xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); +- if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Video BIOS not detected in PCI space!\n"); +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Attempting to read Video BIOS from " +- "legacy ISA space!\n"); +- info->BIOSAddr = 0x000c0000; +- xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, +- RADEON_VBIOS_SIZE, info->VBIOS); +- } +-#endif ++ } else if (!radeon_read_bios(pScrn)) { ++ (void)radeon_read_unposted_bios(pScrn); + } + } + +@@ -160,7 +342,6 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + info->IsAtomBios ? "ATOM":"Legacy"); + + if (info->IsAtomBios) { +-#if 1 + AtomBiosArgRec atomBiosArg; + + if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) +@@ -194,8 +375,14 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, + GET_REF_CLOCK, &atomBiosArg); + +-#endif + info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); ++ } else { ++ /* non-primary card may need posting */ ++ if (!pInt10) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via BIOS tables\n"); ++ RADEONGetBIOSInitTableOffsets(pScrn); ++ RADEONPostCardFromBIOSTables(pScrn); ++ } + } + + return TRUE; +@@ -216,6 +403,55 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) return FALSE; } @@ -5619,7 +7505,7 @@ index 8e6bd8d..fa09aae 100644 static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); -@@ -297,28 +347,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -297,28 +533,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) else info->BiosConnector[i].TMDSType = TMDS_INT; @@ -5649,7 +7535,7 @@ index 8e6bd8d..fa09aae 100644 } } else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); -@@ -541,7 +571,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -541,7 +757,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); RADEONPLLPtr pll = &info->pll; @@ -5658,7 +7544,7 @@ index 8e6bd8d..fa09aae 100644 if (!info->VBIOS) { return FALSE; -@@ -620,6 +650,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -620,6 +836,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) if (!info->VBIOS) return FALSE; @@ -5668,7 +7554,7 @@ index 8e6bd8d..fa09aae 100644 if (info->IsAtomBios) { /* not implemented yet */ return FALSE; -@@ -628,7 +661,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -628,7 +847,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); if (offset) { rev = RADEON_BIOS8(offset + 0x3); @@ -5691,7 +7577,7 @@ index 8e6bd8d..fa09aae 100644 bg = RADEON_BIOS8(offset + 0xc) & 0xf; dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20); -@@ -656,6 +703,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -656,6 +889,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj; return TRUE; @@ -5706,7 +7592,7 @@ index 8e6bd8d..fa09aae 100644 } } } -@@ -793,16 +848,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) +@@ -793,16 +1034,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) memcpy(EDID, (char*)(info->VBIOS + tmp), 256); @@ -5733,7 +7619,7 @@ index 8e6bd8d..fa09aae 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); } return TRUE; -@@ -813,7 +868,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -813,7 +1054,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -5742,7 +7628,7 @@ index 8e6bd8d..fa09aae 100644 int i, n; if (!info->VBIOS) return FALSE; -@@ -934,7 +989,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -934,7 +1175,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) unsigned char *RADEONMMIO = info->MMIO; RADEONOutputPrivatePtr radeon_output = output->driver_private; int offset, index, id; @@ -5751,7 +7637,7 @@ index 8e6bd8d..fa09aae 100644 if (!info->VBIOS) return FALSE; -@@ -1044,11 +1099,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1044,11 +1285,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) #define RADEON_PLL_WAIT_DLL_READY_MASK 4 #define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 @@ -5766,7 +7652,7 @@ index 8e6bd8d..fa09aae 100644 if (revision > 0x10) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -@@ -1069,7 +1124,7 @@ Bool +@@ -1069,7 +1310,7 @@ Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); @@ -5775,7 +7661,7 @@ index 8e6bd8d..fa09aae 100644 if (!info->VBIOS) { return FALSE; -@@ -1163,14 +1218,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) +@@ -1163,14 +1404,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) } static void @@ -5795,7 +7681,7 @@ index 8e6bd8d..fa09aae 100644 if (offset == 0) return; -@@ -1271,14 +1326,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1271,14 +1512,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) } static void @@ -5815,7 +7701,7 @@ index 8e6bd8d..fa09aae 100644 if (offset == 0) return; -@@ -1315,7 +1370,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1315,7 +1556,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) val = (val & RADEON_SDRAM_MODE_MASK) | ormask; OUTREG(RADEON_MM_DATA, val); @@ -5824,7 +7710,7 @@ index 8e6bd8d..fa09aae 100644 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", RADEON_B3MEM_RESET_MASK, (unsigned)ormask); -@@ -1330,13 +1385,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1330,13 +1571,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) } static void @@ -5843,7 +7729,7 @@ index 8e6bd8d..fa09aae 100644 if (offset == 0) return; -@@ -1398,11 +1453,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1398,11 +1639,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) offset++; andmask = @@ -6017,6 +7903,19 @@ index e6890be..b60e7e8 100644 + { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, { -1, NULL } }; +diff --git a/src/radeon_common.h b/src/radeon_common.h +index 467addf..193c1f9 100644 +--- a/src/radeon_common.h ++++ b/src/radeon_common.h +@@ -422,6 +422,8 @@ typedef union { + #define RADEON_PARAM_SCRATCH_OFFSET 11 + #define RADEON_PARAM_CARD_TYPE 12 + #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ ++#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ ++#define RADEON_PARAM_NUM_GB_PIPES 15 + + typedef struct drm_radeon_getparam { + int param; diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index 0250aef..b1dd6e8 100644 --- a/src/radeon_commonfuncs.c @@ -7115,7 +9014,7 @@ index 3b54626..67892a6 100644 #define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 5cf8d51..83e0f85 100644 +index 5cf8d51..91421b5 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -126,35 +126,6 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); @@ -7605,6 +9504,15 @@ index 5cf8d51..83e0f85 100644 /* Some production boards of m6 will return 0 if it's 8 MB */ if (pScrn->videoRam == 0) { pScrn->videoRam = 8192; +@@ -1614,7 +1631,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + break; + } + } +- ++ + switch (info->Chipset) { + case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ + case PCI_CHIP_RN50_5969: @@ -1636,6 +1653,13 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); } @@ -7641,16 +9549,50 @@ index 5cf8d51..83e0f85 100644 return TRUE; } -@@ -1939,7 +1978,7 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -1939,7 +1978,21 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) #if !defined(__powerpc__) && !defined(__sparc__) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 fp2_gen_ctl_save = 0; + uint32_t fp2_gen_ctl_save = 0; ++ ++#ifdef XSERVER_LIBPCIACCESS ++#if HAVE_PCI_DEVICE_ENABLE ++ pci_device_enable(info->PciInfo); ++#endif ++#endif ++ /* don't need int10 on atom cards. ++ * in theory all radeons, but the older stuff ++ * isn't 100% yet ++ */ ++ if ((info->ChipFamily == CHIP_FAMILY_R420) || ++ (info->ChipFamily == CHIP_FAMILY_RV410) || ++ (info->ChipFamily >= CHIP_FAMILY_RV515)) ++ return TRUE; if (xf86LoadSubModule(pScrn, "int10")) { /* The VGA BIOS on the RV100/QY cannot be read when the digital output -@@ -1996,13 +2035,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -1952,13 +2005,15 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); + } + } +- ++ + xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); + *ppInt10 = xf86InitInt10(info->pEnt->index); + +- if (fp2_gen_ctl_save & RADEON_FP2_ON) { +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); +- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); ++ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { ++ if (fp2_gen_ctl_save & RADEON_FP2_ON) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); ++ OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); ++ } + } + } + #endif +@@ -1996,13 +2051,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) info->Chipset == PCI_CHIP_RC410_5A61 || info->Chipset == PCI_CHIP_RC410_5A62 || info->Chipset == PCI_CHIP_RS485_5975 || @@ -7668,7 +9610,7 @@ index 5cf8d51..83e0f85 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering not officially supported on RN50/RC410/R600\n"); return FALSE; -@@ -2163,7 +2203,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2163,7 +2219,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) } else { from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, &info->allowPageFlip) ? X_CONFIG : X_DEFAULT; @@ -7684,7 +9626,7 @@ index 5cf8d51..83e0f85 100644 } #else from = X_DEFAULT; -@@ -2221,7 +2268,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2221,7 +2284,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) info->pKernelDRMVersion->version_minor, info->pKernelDRMVersion->version_patchlevel); info->allowColorTiling = FALSE; @@ -7693,7 +9635,7 @@ index 5cf8d51..83e0f85 100644 } #endif /* XF86DRI */ -@@ -2236,9 +2283,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2236,9 +2299,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -7706,7 +9648,7 @@ index 5cf8d51..83e0f85 100644 #ifdef XvExtension char* microc_path = NULL; char* microc_type = NULL; -@@ -2366,7 +2413,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) +@@ -2366,7 +2429,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) } bios_header=info->VBIOS[0x48]; @@ -7715,7 +9657,18 @@ index 5cf8d51..83e0f85 100644 mm_table=info->VBIOS[bios_header+0x38]; if(mm_table==0) -@@ -2636,8 +2683,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2423,10 +2486,6 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) + static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + { + RADEONGetBIOSInfo(pScrn, pInt10); +-#if 0 +- RADEONGetBIOSInitTableOffsets(pScrn); +- RADEONPostCardFromBIOSTables(pScrn); +-#endif + } + + static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) +@@ -2636,8 +2695,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; @@ -7725,7 +9678,7 @@ index 5cf8d51..83e0f85 100644 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; -@@ -2689,7 +2735,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2689,7 +2747,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitWeight(pScrn)) goto fail; @@ -7734,7 +9687,7 @@ index 5cf8d51..83e0f85 100644 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { if (strcmp(s, "AUTO") == 0) { info->DispPriority = 1; -@@ -2698,7 +2744,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2698,17 +2756,17 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } else if (strcmp(s, "HIGH") == 0) { info->DispPriority = 2; } else @@ -7742,8 +9695,21 @@ index 5cf8d51..83e0f85 100644 + info->DispPriority = 1; } ++ if (!RADEONPreInitChipType(pScrn)) ++ goto fail; ++ if (!RADEONPreInitInt10(pScrn, &pInt10)) -@@ -2739,17 +2785,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + goto fail; + + RADEONPostInt10Check(pScrn, int10_save); + +- if (!RADEONPreInitChipType(pScrn)) +- goto fail; +- + RADEONPreInitBIOS(pScrn, pInt10); + + #ifdef XF86DRI +@@ -2739,17 +2797,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (crtc_max_Y > 8192) crtc_max_Y = 8192; } else { @@ -7773,7 +9739,7 @@ index 5cf8d51..83e0f85 100644 } } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", -@@ -2793,14 +2844,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2793,14 +2856,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitAccel(pScrn)) goto fail; @@ -7793,7 +9759,7 @@ index 5cf8d51..83e0f85 100644 if (pScrn->modes == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); goto fail; -@@ -2858,7 +2911,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, +@@ -2858,7 +2923,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int i; int index, j; @@ -7802,7 +9768,7 @@ index 5cf8d51..83e0f85 100644 int c; #ifdef XF86DRI -@@ -3001,7 +3054,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) +@@ -3001,7 +3066,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) /* let the bios control the backlight */ save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; /* tell the bios not to handle mode switching */ @@ -7812,7 +9778,7 @@ index 5cf8d51..83e0f85 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) { OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); -@@ -3014,7 +3068,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) +@@ -3014,7 +3080,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) /* let the bios control the backlight */ save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; /* tell the bios not to handle mode switching */ @@ -7822,7 +9788,7 @@ index 5cf8d51..83e0f85 100644 /* tell the bios a driver is loaded */ save->bios_7_scratch |= RADEON_DRV_LOADED; -@@ -3032,9 +3087,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3032,9 +3099,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -7832,7 +9798,7 @@ index 5cf8d51..83e0f85 100644 #ifdef RENDER int subPixelOrder = SubPixelUnknown; char* s; -@@ -3080,11 +3133,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3080,11 +3145,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONBlank(pScrn); if (info->IsMobility && !IS_AVIVO_VARIANT) { @@ -7852,7 +9818,7 @@ index 5cf8d51..83e0f85 100644 } if (IS_R300_VARIANT || IS_RV100_VARIANT) -@@ -3139,12 +3197,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3139,12 +3209,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONInitMemoryMap(pScrn); /* empty the surfaces */ @@ -7873,7 +9839,22 @@ index 5cf8d51..83e0f85 100644 } #ifdef XF86DRI -@@ -3340,28 +3400,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3164,9 +3236,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + #endif + + /* Initial setup of surfaces */ +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "Setting up initial surfaces\n"); +- RADEONChangeSurfaces(pScrn); ++ if (info->ChipFamily < CHIP_FAMILY_R600) { ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "Setting up initial surfaces\n"); ++ RADEONChangeSurfaces(pScrn); ++ } + + /* Memory manager setup */ + +@@ -3340,28 +3414,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* xf86CrtcRotate() accesses pScrn->pScreen */ pScrn->pScreen = pScreen; @@ -7902,7 +9883,23 @@ index 5cf8d51..83e0f85 100644 RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); -@@ -3544,7 +3584,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3417,10 +3471,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + #endif + + /* Make sure surfaces are allright since DRI setup may have changed them */ +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "Setting up final surfaces\n"); ++ if (info->ChipFamily < CHIP_FAMILY_R600) { ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "Setting up final surfaces\n"); + +- RADEONChangeSurfaces(pScrn); ++ RADEONChangeSurfaces(pScrn); ++ } + + + /* Enable aceleration */ +@@ -3544,7 +3600,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; int timeout; @@ -7911,7 +9908,7 @@ index 5cf8d51..83e0f85 100644 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, &mc_agp_loc, &mc_agp_loc_hi); -@@ -3564,7 +3604,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3564,7 +3620,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, if (mc_fb_loc != restore->mc_fb_location || mc_agp_loc != restore->mc_agp_location) { @@ -7920,7 +9917,7 @@ index 5cf8d51..83e0f85 100644 RADEONWaitForIdleMMIO(pScrn); -@@ -3620,8 +3660,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3620,8 +3676,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, */ if (mc_fb_loc != restore->mc_fb_location || mc_agp_loc != restore->mc_agp_location) { @@ -7931,7 +9928,7 @@ index 5cf8d51..83e0f85 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, " Map Changed ! Applying ...\n"); -@@ -3759,16 +3799,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3759,16 +3815,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -7953,7 +9950,17 @@ index 5cf8d51..83e0f85 100644 changed = 1; if (changed) { -@@ -4039,12 +4079,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -3997,7 +4053,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + } + + /* Update surface images */ +- RADEONSaveSurfaces(pScrn, info->ModeReg); ++ if (info->ChipFamily < CHIP_FAMILY_R600) ++ RADEONSaveSurfaces(pScrn, info->ModeReg); + } + + /* Read memory map */ +@@ -4039,12 +4096,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) } #endif @@ -7968,7 +9975,7 @@ index 5cf8d51..83e0f85 100644 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); -@@ -4110,8 +4151,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4110,8 +4168,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); @@ -7977,7 +9984,7 @@ index 5cf8d51..83e0f85 100644 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); -@@ -4151,57 +4190,208 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4151,57 +4207,208 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); @@ -8179,8 +10186,8 @@ index 5cf8d51..83e0f85 100644 + j++; + } + } - } - ++ } ++ + /* scalers */ + j = 0; + for (i = 0x6578; i <= 0x65e4; i += 4) { @@ -8192,7 +10199,7 @@ index 5cf8d51..83e0f85 100644 + state->d1scl[j] = INREG(i); + state->d2scl[j] = INREG(i + 0x800); + j++; -+ } + } + j = 0; + for (i = 0x66e8; i <= 0x66fc; i += 4) { + state->dxscl[j] = INREG(i); @@ -8200,7 +10207,7 @@ index 5cf8d51..83e0f85 100644 + } + state->dxscl[6] = INREG(0x6e30); + state->dxscl[7] = INREG(0x6e34); -+ + if (state->crtc1.control & AVIVO_CRTC_EN) info->crtc_on = TRUE; - @@ -8221,7 +10228,7 @@ index 5cf8d51..83e0f85 100644 // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); -@@ -4266,8 +4456,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4266,8 +4473,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); @@ -8230,7 +10237,7 @@ index 5cf8d51..83e0f85 100644 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); -@@ -4306,49 +4494,200 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4306,49 +4511,200 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); @@ -8433,8 +10440,8 @@ index 5cf8d51..83e0f85 100644 + j++; + } + } - } - ++ } ++ + /* scalers */ + j = 0; + for (i = 0x6578; i <= 0x65e4; i += 4) { @@ -8451,10 +10458,10 @@ index 5cf8d51..83e0f85 100644 + for (i = 0x66e8; i <= 0x66fc; i += 4) { + OUTREG(i, state->dxscl[j]); + j++; -+ } + } + OUTREG(0x6e30, state->dxscl[6]); + OUTREG(0x6e34, state->dxscl[7]); -+ + OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); } @@ -8466,7 +10473,7 @@ index 5cf8d51..83e0f85 100644 RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; struct avivo_state *state = &restore->avivo; -@@ -4434,6 +4773,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) +@@ -4434,6 +4790,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) * setup in the card at all !! */ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ @@ -8476,7 +10483,14 @@ index 5cf8d51..83e0f85 100644 # else /* Save mode * & fonts & cmap */ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); -@@ -4471,7 +4813,7 @@ static void RADEONSave(ScrnInfoPtr pScrn) +@@ -4466,12 +4825,13 @@ static void RADEONSave(ScrnInfoPtr pScrn) + } + + RADEONSaveBIOSRegisters(pScrn, save); +- RADEONSaveSurfaces(pScrn, save); ++ if (info->ChipFamily < CHIP_FAMILY_R600) ++ RADEONSaveSurfaces(pScrn, save); + } /* Restore the original (text) mode */ @@ -8485,7 +10499,28 @@ index 5cf8d51..83e0f85 100644 { RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -@@ -4555,7 +4897,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4522,9 +4882,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) + } + + RADEONRestoreBIOSRegisters(pScrn, restore); +- RADEONRestoreSurfaces(pScrn, restore); + } + ++ + #if 1 + /* Temp fix to "solve" VT switch problems. When switching VTs on + * some systems, the console can either hang or the fonts can be +@@ -4534,6 +4894,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) + usleep(100000); + #endif + ++ if (info->ChipFamily < CHIP_FAMILY_R600) ++ RADEONRestoreSurfaces(pScrn, restore); ++ + /* need to make sure we don't enable a crtc by accident or we may get a hang */ + if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { + if (info->crtc2_on && xf86_config->num_crtc > 1) { +@@ -4555,7 +4918,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) * write VGA fonts, will find a better solution in the future */ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); @@ -8496,7 +10531,7 @@ index 5cf8d51..83e0f85 100644 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); # endif vgaHWLock(hwp); -@@ -4567,7 +4911,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4567,7 +4932,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) */ if (IS_AVIVO_VARIANT) avivo_restore_vga_regs(pScrn, restore); @@ -8507,16 +10542,52 @@ index 5cf8d51..83e0f85 100644 #if 0 RADEONWaitForVerticalSync(pScrn); -@@ -4885,8 +5231,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4885,63 +5252,68 @@ Bool RADEONEnterVT(int scrnIndex, int flags) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; ++ uint32_t mem_size; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); -@@ -4907,41 +5251,34 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + +- if ((INREG(RADEON_CONFIG_MEMSIZE)) == 0) { /* Softboot V_BIOS */ +- xf86Int10InfoPtr pInt; +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); +- pInt = xf86InitInt10 (info->pEnt->index); +- if (pInt) { +- pInt->num = 0xe6; +- xf86ExecX86int10 (pInt); +- xf86FreeInt10 (pInt); +- } ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ mem_size = INREG(R600_CONFIG_MEMSIZE); ++ else ++ mem_size = INREG(RADEON_CONFIG_MEMSIZE); ++ ++ if (mem_size == 0) { /* Softboot V_BIOS */ ++ if (info->IsAtomBios) { ++ rhdAtomASICInit(info->atomBIOS); ++ } else { ++ xf86Int10InfoPtr pInt; ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); ++ pInt = xf86InitInt10 (info->pEnt->index); ++ if (pInt) { ++ pInt->num = 0xe6; ++ xf86ExecX86int10 (pInt); ++ xf86FreeInt10 (pInt); ++ } else { ++ RADEONGetBIOSInitTableOffsets(pScrn); ++ RADEONPostCardFromBIOSTables(pScrn); ++ } ++ } + } + + /* Makes sure the engine is idle before doing anything */ RADEONWaitForIdleMMIO(pScrn); if (info->IsMobility && !IS_AVIVO_VARIANT) { @@ -8558,7 +10629,9 @@ index 5cf8d51..83e0f85 100644 + if (!xf86SetDesiredModes(pScrn)) + return FALSE; - RADEONRestoreSurfaces(pScrn, info->ModeReg); +- RADEONRestoreSurfaces(pScrn, info->ModeReg); ++ if (info->ChipFamily < CHIP_FAMILY_R600) ++ RADEONRestoreSurfaces(pScrn, info->ModeReg); #ifdef XF86DRI if (info->directRenderingEnabled) { - if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) @@ -8573,7 +10646,7 @@ index 5cf8d51..83e0f85 100644 } /* get the DRI back into shape after resume */ -@@ -4966,8 +5303,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4966,8 +5338,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) } #endif @@ -8582,7 +10655,7 @@ index 5cf8d51..83e0f85 100644 return TRUE; } -@@ -4978,6 +5313,10 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4978,6 +5348,10 @@ void RADEONLeaveVT(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -8593,7 +10666,7 @@ index 5cf8d51..83e0f85 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT\n"); -@@ -4988,8 +5327,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4988,8 +5362,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); @@ -8605,7 +10678,7 @@ index 5cf8d51..83e0f85 100644 /* we need to backup the PCIE GART TABLE from fb memory */ memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize); } -@@ -5009,6 +5349,23 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5009,6 +5384,23 @@ void RADEONLeaveVT(int scrnIndex, int flags) } #endif @@ -8629,7 +10702,7 @@ index 5cf8d51..83e0f85 100644 RADEONRestore(pScrn); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5121,7 +5478,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) +@@ -5121,7 +5513,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) { /* It appears from r300 and rv100 may need some clocks forced-on */ @@ -8638,7 +10711,7 @@ index 5cf8d51..83e0f85 100644 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; -@@ -5133,7 +5490,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) +@@ -5133,7 +5525,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -12718,10 +14791,18 @@ index 9c1bdc5..24af52b 100644 /* radeon_probe.c */ diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 046c52b..c5ab0de 100644 +index 046c52b..b2d6fd1 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h -@@ -886,7 +886,35 @@ +@@ -265,6 +265,7 @@ + #define RADEON_BRUSH_Y_X 0x1474 + #define RADEON_BUS_CNTL 0x0030 + # define RADEON_BUS_MASTER_DIS (1 << 6) ++# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) + # define RADEON_BUS_RD_DISCARD_EN (1 << 24) + # define RADEON_BUS_RD_ABORT_EN (1 << 25) + # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) +@@ -886,7 +887,35 @@ # define RADEON_VERT_STRETCH_LINEREP (0 << 26) # define RADEON_VERT_STRETCH_BLEND (1 << 26) # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) @@ -12758,7 +14839,38 @@ index 046c52b..c5ab0de 100644 #define RADEON_GEN_INT_CNTL 0x0040 #define RADEON_GEN_INT_STATUS 0x0044 -@@ -1634,9 +1662,25 @@ +@@ -1018,10 +1047,12 @@ + # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) + # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) + #define RADEON_LCD_GPIO_MASK 0x01a0 ++#define RADEON_GPIOPAD_EN 0x01a0 + #define RADEON_LCD_GPIO_Y_REG 0x01a4 + #define RADEON_MDGPIO_A_REG 0x01ac + #define RADEON_MDGPIO_EN_REG 0x01b0 + #define RADEON_MDGPIO_MASK 0x0198 ++#define RADEON_GPIOPAD_MASK 0x0198 + #define RADEON_GPIOPAD_A 0x019c + #define RADEON_MDGPIO_Y_REG 0x01b4 + #define RADEON_MEM_ADDR_CONFIG 0x0148 +@@ -1056,6 +1087,9 @@ + #define RADEON_MPLL_CNTL 0x000e /* PLL */ + #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ + #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ ++#define RADEON_SEPROM_CNTL1 0x01c0 ++# define RADEON_SCK_PRESCALE_SHIFT 24 ++# define RADEON_SCK_PRESCALE_MASK (0xff << 24) + #define R300_MC_IND_INDEX 0x01f8 + # define R300_MC_IND_ADDR_MASK 0x3f + # define R300_MC_IND_WR_EN (1 << 8) +@@ -1620,6 +1654,7 @@ + # define RADEON_VIP_BUSY 0 + # define RADEON_VIP_IDLE 1 + # define RADEON_VIP_RESET 2 ++# define RADEON_VIPH_EN (1 << 21) + #define RADEON_VIPH_DV_LAT 0x0c44 + #define RADEON_VIPH_BM_CHUNK 0x0c48 + #define RADEON_VIPH_DV_INT 0x0c4c +@@ -1634,9 +1669,25 @@ #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) @@ -12784,7 +14896,7 @@ index 046c52b..c5ab0de 100644 #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ #define RADEON_XCLK_CNTL 0x000d /* PLL */ -@@ -3328,10 +3372,32 @@ +@@ -3328,10 +3379,32 @@ # define RADEON_TVPLL_TEST_DIS (1 << 31) # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) @@ -12821,7 +14933,7 @@ index 046c52b..c5ab0de 100644 #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff -@@ -3343,7 +3409,17 @@ +@@ -3343,7 +3416,17 @@ #define RS690_MC_AGP_LOCATION 0x101 #define RS690_MC_AGP_BASE 0x102 #define RS690_MC_STATUS 0x90 @@ -12840,7 +14952,16 @@ index 046c52b..c5ab0de 100644 #define AVIVO_MC_INDEX 0x0070 #define R520_MC_STATUS 0x00 -@@ -3475,6 +3551,8 @@ +@@ -3359,6 +3442,8 @@ + + #define AVIVO_HDP_FB_LOCATION 0x134 + ++#define AVIVO_VGA_RENDER_CONTROL 0x0300 ++# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) + #define AVIVO_D1VGA_CONTROL 0x0330 + # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) + # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) +@@ -3475,6 +3560,8 @@ #define AVIVO_D1CUR_SIZE 0x6410 #define AVIVO_D1CUR_POSITION 0x6414 #define AVIVO_D1CUR_HOT_SPOT 0x6418 @@ -12849,7 +14970,7 @@ index 046c52b..c5ab0de 100644 #define AVIVO_DC_LUT_RW_SELECT 0x6480 #define AVIVO_DC_LUT_RW_MODE 0x6484 -@@ -3555,6 +3633,8 @@ +@@ -3555,6 +3642,8 @@ #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 @@ -12858,7 +14979,7 @@ index 046c52b..c5ab0de 100644 #define AVIVO_DACA_ENABLE 0x7800 # define AVIVO_DAC_ENABLE (1 << 0) #define AVIVO_DACA_SOURCE_SELECT 0x7804 -@@ -3745,6 +3825,8 @@ +@@ -3745,6 +3834,8 @@ # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 @@ -12867,7 +14988,35 @@ index 046c52b..c5ab0de 100644 #define AVIVO_GPIO_0 0x7e30 #define AVIVO_GPIO_1 0x7e40 #define AVIVO_GPIO_2 0x7e50 -@@ -3832,6 +3914,7 @@ +@@ -3793,6 +3884,15 @@ + # define AVIVO_I2C_EN (1 << 0) + # define AVIVO_I2C_RESET (1 << 8) + ++#define R600_GENERAL_PWRMGT 0x618 ++# define R600_OPEN_DRAIN_PADS (1 << 11) ++ ++#define R600_LOWER_GPIO_ENABLE 0x710 ++#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 ++#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c ++#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 ++#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 ++ + #define R600_MC_VM_FB_LOCATION 0x2180 + #define R600_MC_VM_AGP_TOP 0x2184 + #define R600_MC_VM_AGP_BOT 0x2188 +@@ -3809,6 +3909,11 @@ + #define R600_CONFIG_F0_BASE 0x542C + #define R600_CONFIG_APER_SIZE 0x5430 + ++#define R600_ROM_CNTL 0x1600 ++# define R600_SCK_OVERWRITE (1 << 1) ++# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 ++# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) ++ + #define R600_BIOS_0_SCRATCH 0x1724 + #define R600_BIOS_1_SCRATCH 0x1728 + #define R600_BIOS_2_SCRATCH 0x172c +@@ -3832,6 +3937,7 @@ #define R300_GB_SELECT 0x401c #define R300_GB_ENABLE 0x4008 #define R300_GB_AA_CONFIG 0x4020 @@ -12875,7 +15024,7 @@ index 046c52b..c5ab0de 100644 #define R300_GB_MSPOS0 0x4010 # define R300_MS_X0_SHIFT 0 # define R300_MS_Y0_SHIFT 4 -@@ -3850,6 +3933,10 @@ +@@ -3850,6 +3956,10 @@ # define R300_MS_Y5_SHIFT 20 # define R300_MSBD1_SHIFT 24 @@ -12886,7 +15035,7 @@ index 046c52b..c5ab0de 100644 #define R300_GA_POLY_MODE 0x4288 # define R300_FRONT_PTYPE_POINT (0 << 4) # define R300_FRONT_PTYPE_LINE (1 << 4) -@@ -3889,6 +3976,8 @@ +@@ -3889,6 +3999,8 @@ # define R300_ALPHA3_SHADING_GOURAUD (2 << 14) #define R300_GA_OFFSET 0x4290 @@ -12895,7 +15044,7 @@ index 046c52b..c5ab0de 100644 #define R300_VAP_CNTL_STATUS 0x2140 # define R300_PVS_BYPASS (1 << 8) #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -@@ -3899,6 +3988,7 @@ +@@ -3899,6 +4011,7 @@ # define R300_VF_MAX_VTX_NUM_SHIFT 18 # define R300_GL_CLIP_SPACE_DEF (0 << 22) # define R300_DX_CLIP_SPACE_DEF (1 << 22) @@ -12903,7 +15052,7 @@ index 046c52b..c5ab0de 100644 #define R300_VAP_VTE_CNTL 0x20B0 # define R300_VPORT_X_SCALE_ENA (1 << 0) # define R300_VPORT_X_OFFSET_ENA (1 << 1) -@@ -3909,6 +3999,7 @@ +@@ -3909,6 +4022,7 @@ # define R300_VTX_XY_FMT (1 << 8) # define R300_VTX_Z_FMT (1 << 9) # define R300_VTX_W0_FMT (1 << 10) @@ -12911,7 +15060,7 @@ index 046c52b..c5ab0de 100644 #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 # define R300_DATA_TYPE_0_SHIFT 0 -@@ -3986,6 +4077,123 @@ +@@ -3986,6 +4100,123 @@ # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 @@ -13035,7 +15184,7 @@ index 046c52b..c5ab0de 100644 #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC #define R300_VAP_OUT_VTX_FMT_0 0x2090 # define R300_VTX_POS_PRESENT (1 << 0) -@@ -4019,6 +4227,9 @@ +@@ -4019,6 +4250,9 @@ # define R300_CLIP_DISABLE (1 << 16) # define R300_UCP_CULL_ONLY_ENA (1 << 17) # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) @@ -13045,7 +15194,7 @@ index 046c52b..c5ab0de 100644 #define R300_SU_TEX_WRAP 0x42a0 #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 -@@ -4036,6 +4247,7 @@ +@@ -4036,6 +4270,7 @@ # define R300_RS_COUNT_HIRES_EN (1 << 18) #define R300_RS_IP_0 0x4310 @@ -13053,7 +15202,7 @@ index 046c52b..c5ab0de 100644 # define R300_RS_TEX_PTR(x) (x << 0) # define R300_RS_COL_PTR(x) (x << 6) # define R300_RS_COL_FMT(x) (x << 9) -@@ -4063,7 +4275,10 @@ +@@ -4063,7 +4298,10 @@ # define R300_RS_W_EN (1 << 4) # define R300_TX_OFFSET_RS(x) (x << 5) #define R300_RS_INST_0 0x4330 @@ -13064,7 +15213,7 @@ index 046c52b..c5ab0de 100644 #define R300_TX_INVALTAGS 0x4100 #define R300_TX_FILTER0_0 0x4400 -@@ -4082,6 +4297,7 @@ +@@ -4082,6 +4320,7 @@ # define R300_TX_MIN_FILTER_NEAREST (1 << 11) # define R300_TX_MAG_FILTER_LINEAR (2 << 9) # define R300_TX_MIN_FILTER_LINEAR (2 << 11) @@ -13072,7 +15221,7 @@ index 046c52b..c5ab0de 100644 #define R300_TX_FILTER1_0 0x4440 #define R300_TX_FORMAT0_0 0x4480 # define R300_TXWIDTH_SHIFT 0 -@@ -4164,11 +4380,16 @@ +@@ -4164,11 +4403,16 @@ # define R300_TX_FORMAT_SWAP_YUV (1 << 24) #define R300_TX_FORMAT2_0 0x4500 @@ -13090,7 +15239,7 @@ index 046c52b..c5ab0de 100644 #define R300_TX_ENABLE 0x4104 # define R300_TEX_0_ENABLE (1 << 0) -@@ -4189,7 +4410,7 @@ +@@ -4189,7 +4433,7 @@ # define R300_OUT_FMT_C2_16_MPEG (7 << 0) # define R300_OUT_FMT_C2_4 (8 << 0) # define R300_OUT_FMT_C_3_3_2 (9 << 0) @@ -13099,7 +15248,7 @@ index 046c52b..c5ab0de 100644 # define R300_OUT_FMT_C_11_11_10 (11 << 0) # define R300_OUT_FMT_C_10_11_11 (12 << 0) # define R300_OUT_FMT_C_2_10_10_10 (13 << 0) -@@ -4227,28 +4448,221 @@ +@@ -4227,28 +4471,221 @@ # define R300_TEX_CODE_OFFSET(x) (x << 13) # define R300_TEX_CODE_SIZE(x) (x << 18) #define R300_US_CODE_ADDR_0 0x4610 @@ -13324,7 +15473,7 @@ index 046c52b..c5ab0de 100644 #define R300_RB3D_ZSTENCILCNTL 0x4f04 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 #define R300_RB3D_BW_CNTL 0x4f1c -@@ -4256,6 +4670,9 @@ +@@ -4256,6 +4693,9 @@ #define R300_RB3D_ZTOP 0x4f14 #define R300_RB3D_ROPCNTL 0x4e18 #define R300_RB3D_BLENDCNTL 0x4e04 @@ -13334,7 +15483,7 @@ index 046c52b..c5ab0de 100644 #define R300_RB3D_ABLENDCNTL 0x4e08 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c #define R300_RB3D_COLOROFFSET0 0x4e28 -@@ -4387,7 +4804,7 @@ +@@ -4387,7 +4827,7 @@ # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) @@ -13343,7 +15492,7 @@ index 046c52b..c5ab0de 100644 #define R500_US_ALU_RGBA_INST_0 0xb000 # define R500_ALU_RGBA_OP_MAD (0 << 0) # define R500_ALU_RGBA_OP_DP3 (1 << 0) -@@ -4540,7 +4957,7 @@ +@@ -4540,7 +4980,7 @@ # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) @@ -13352,7 +15501,7 @@ index 046c52b..c5ab0de 100644 #define R500_US_CMN_INST_0 0xb800 # define R500_INST_TYPE_ALU (0 << 0) # define R500_INST_TYPE_OUT (1 << 0) -@@ -4779,17 +5196,18 @@ +@@ -4779,17 +5219,18 @@ #define R500_GA_US_VECTOR_DATA 0x4254 #define R500_RS_INST_0 0x4320 @@ -13382,7 +15531,7 @@ index 046c52b..c5ab0de 100644 #define R500_US_FC_CTRL 0x4624 #define R500_US_CODE_ADDR 0x4630 -@@ -4797,16 +5215,18 @@ +@@ -4797,16 +5238,18 @@ #define R500_US_CODE_OFFSET 0x4638 #define R500_RS_IP_0 0x4074 diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 9e3c57a..167a4bb 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.8.0 -Release: 16%{?dist} +Release: 17%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -91,6 +91,10 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Wed May 28 2008 Dave Airlie 6.8.0-17 +- fix multiple VT switch issues on r600 cards +- assorted upstream goodness + * Sat May 24 2008 Dave Airlie 6.8.0-16 - Fix PLL on r600 LVDS (#444542) - update to other upstream fixes