From 8f268e09133aa0cba535861ed5b8612ae97a1111 Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Aug 27 2007 15:43:28 +0000 Subject: xf86-video-ati 6.7.192 --- diff --git a/.cvsignore b/.cvsignore index fca777c..685b951 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1,2 +1 @@ -xf86-video-ati-6.6.193.tar.bz2 -xf86-video-ati-6.7.191.tar.bz2 +xf86-video-ati-6.7.192.tar.bz2 diff --git a/radeon-6.6.192-dotclock-filter.patch b/radeon-6.6.192-dotclock-filter.patch deleted file mode 100644 index e0aa6b3..0000000 --- a/radeon-6.6.192-dotclock-filter.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- xf86-video-ati-6.6.192/src/radeon_display.c.dotclock-filter 2007-05-20 17:20:41.000000000 -0400 -+++ xf86-video-ati-6.6.192/src/radeon_display.c 2007-06-27 11:07:55.000000000 -0400 -@@ -222,9 +222,15 @@ - { - MonPtr mon = pScrn->monitor; - xf86MonPtr ddc = mon->DDC; -- int i; -+ int i, clock; - -- if (flag) { /* HSync */ -+ (void)flag; -+ -+ clock = ddc->det_mon[i].section.ranges.max_clock * 1000; -+ if (clock < pScrn->monitor->maxPixClock || !pScrn->monitor->maxPixClock) -+ pScrn->monitor->maxPixClock = clock; -+ -+ if (pScrn->monitor->nHsync <= 0) { - for (i = 0; i < 4; i++) { - if (ddc->det_mon[i].type == DS_RANGES) { - mon->nHsync = 1; -@@ -270,7 +276,8 @@ - i++; - } - mon->nHsync = i; -- } else { /* Vrefresh */ -+ } -+ if (pScrn->monitor->nVrefresh <= 0) { - for (i = 0; i < 4; i++) { - if (ddc->det_mon[i].type == DS_RANGES) { - mon->nVrefresh = 1; ---- xf86-video-ati-6.6.192/src/radeon_driver.c.dotclock-filter 2007-05-20 17:20:14.000000000 -0400 -+++ xf86-video-ati-6.6.192/src/radeon_driver.c 2007-06-27 11:08:47.000000000 -0400 -@@ -2115,10 +2115,7 @@ - * additional way to auto-detect sync ranges if they haven't - * been added to XF86Config manually. - */ -- if (pScrn->monitor->nHsync <= 0) -- RADEONSetSyncRangeFromEdid(pScrn, 1); -- if (pScrn->monitor->nVrefresh <= 0) -- RADEONSetSyncRangeFromEdid(pScrn, 0); -+ RADEONSetSyncRangeFromEdid(pScrn, 0); - } - - /* Get mode information */ diff --git a/radeon-6.7.191-git-master.patch b/radeon-6.7.191-git-master.patch deleted file mode 100644 index 59ebced..0000000 --- a/radeon-6.7.191-git-master.patch +++ /dev/null @@ -1,2041 +0,0 @@ -diff --git a/configure.ac b/configure.ac -index b178224..cdc6377 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -71,7 +71,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto) - XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) - - # Checks for pkg-config packages --PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES]) -+PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES]) - sdkdir=$(pkg-config --variable=sdkdir xorg-server) - - # Checks for libraries. -diff --git a/man/radeon.man b/man/radeon.man -index 8423cc9..88665bf 100644 ---- a/man/radeon.man -+++ b/man/radeon.man -@@ -150,14 +150,6 @@ affects the "true" overlay via xv, it won't affect things like textured video. - .br - The default value is either 1536 (for most chips) or 1920. - .TP --.BI "Option \*qUseFBDev\*q \*q" boolean \*q --Enable or disable use of an OS\-specific framebuffer device interface --(which is not supported on all OSs). MergedFB does not work when this --option is in use. See fbdevhw(__drivermansuffix__) for further information. --.br --The default is --.B off. --.TP - .BI "Option \*qAGPMode\*q \*q" integer \*q - Set AGP data transfer rate. - (used only when DRI is enabled) -diff --git a/src/atidri.c b/src/atidri.c -index d4fbead..07adda7 100644 ---- a/src/atidri.c -+++ b/src/atidri.c -@@ -1269,9 +1269,10 @@ Bool ATIDRIScreenInit( ScreenPtr pScreen ) - ErrorF( "[dri] Data does not fit in SAREA\n" ); - return FALSE; - } -- xf86DrvMsg( pScreenInfo->scrnIndex, X_INFO, "[drm] SAREA %d+%d: %d\n", -- sizeof(XF86DRISAREARec), sizeof(ATISAREAPrivRec), -- sizeof(XF86DRISAREARec) + sizeof(ATISAREAPrivRec) ); -+ xf86DrvMsg( pScreenInfo->scrnIndex, X_INFO, "[drm] SAREA %u+%u: %u\n", -+ (unsigned)sizeof(XF86DRISAREARec), -+ (unsigned)sizeof(ATISAREAPrivRec), -+ (unsigned)(sizeof(XF86DRISAREARec) + sizeof(ATISAREAPrivRec)) ); - pDRIInfo->SAREASize = SAREA_MAX; - - pATIDRI = (ATIDRIPtr) xnfcalloc( sizeof(ATIDRIRec), 1 ); -diff --git a/src/radeon.h b/src/radeon.h -index 1a91cfd..53fb5f7 100644 ---- a/src/radeon.h -+++ b/src/radeon.h -@@ -39,6 +39,7 @@ - - #include /* For abs() */ - #include /* For usleep() */ -+#include /* For gettimeofday() */ - - #include "xf86str.h" - #include "compiler.h" -@@ -122,7 +123,6 @@ typedef enum { - #endif - OPTION_DDC_MODE, - OPTION_IGNORE_EDID, -- OPTION_FBDEV, - OPTION_DISP_PRIORITY, - OPTION_PANEL_SIZE, - OPTION_MIN_DOTCLOCK, -@@ -159,6 +159,8 @@ typedef enum { - #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ - #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ - -+#define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ -+ - /* Buffer are aligned on 4096 byte boundaries */ - #define RADEON_BUFFER_ALIGN 0x00000fff - #define RADEON_VBIOS_SIZE 0x00010000 -@@ -434,8 +436,6 @@ typedef struct { - RADEONChipFamily ChipFamily; - RADEONErrata ChipErrata; - -- Bool FBDev; -- - unsigned long LinearAddr; /* Frame buffer physical address */ - unsigned long MMIOAddr; /* MMIO region physical address */ - unsigned long BIOSAddr; /* BIOS physical address */ -@@ -605,6 +605,7 @@ typedef struct { - Bool allowPageFlip; /* Enable 3d page flipping */ - #ifdef DAMAGE - DamagePtr pDamage; -+ RegionRec driRegion; - #endif - Bool have3DWindows; /* Are there any 3d clients? */ - -@@ -787,6 +788,7 @@ typedef struct { - int MaxLines; - - CARD32 tv_dac_adj; -+ CARD32 tv_dac_enable_mask; - - Bool want_vblank_interrupts; - RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; -@@ -1223,4 +1225,21 @@ static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) - #endif - } - -+static __inline__ void radeon_init_timeout(struct timeval *endtime, -+ unsigned int timeout) -+{ -+ gettimeofday(endtime, NULL); -+ endtime->tv_usec += timeout; -+ endtime->tv_sec += endtime->tv_usec / 1000000; -+ endtime->tv_usec %= 1000000; -+} -+ -+static __inline__ int radeon_timedout(const struct timeval *endtime) -+{ -+ struct timeval now; -+ gettimeofday(&now, NULL); -+ return now.tv_sec == endtime->tv_sec ? -+ now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; -+} -+ - #endif /* _RADEON_H_ */ -diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 975fc07..1ef0ff4 100644 ---- a/src/radeon_bios.c -+++ b/src/radeon_bios.c -@@ -619,8 +619,7 @@ Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) { - ErrorF("\n"); - - return TRUE; -- } else -- return FALSE; -+ } - } - } - return FALSE; -@@ -654,8 +653,11 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) - if (info->sclk == 0) info->sclk = 200; - if (info->mclk == 0) info->mclk = 200; - -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %ld, max_pll: %ld, xclk: %d, sclk: %f, mclk: %f\n", -- pll->reference_freq, pll->min_pll_freq, pll->max_pll_freq, pll->xclk, info->sclk, info->mclk); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " -+ "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", -+ pll->reference_freq, (unsigned)pll->min_pll_freq, -+ (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, -+ info->mclk); - - } else { - pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); -@@ -840,8 +842,9 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) - ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | - ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "TMDS PLL from BIOS: %ld %lx\n", -- radeon_output->tmds_pll[i].freq, radeon_output->tmds_pll[i].value); -+ "TMDS PLL from BIOS: %u %x\n", -+ (unsigned)radeon_output->tmds_pll[i].freq, -+ (unsigned)radeon_output->tmds_pll[i].value); - - if (maxfreq == radeon_output->tmds_pll[i].freq) { - radeon_output->tmds_pll[i].freq = 0xffffffff; -@@ -1077,7 +1080,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - case RADEON_TABLE_FLAG_WRITE_INDEXED: - val = RADEON_BIOS32(offset); - ErrorF("WRITE INDEXED: 0x%x 0x%x\n", -- index, val); -+ index, (unsigned)val); - OUTREG(RADEON_MM_INDEX, index); - OUTREG(RADEON_MM_DATA, val); - offset += 4; -@@ -1085,7 +1088,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - - case RADEON_TABLE_FLAG_WRITE_DIRECT: - val = RADEON_BIOS32(offset); -- ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, val); -+ ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val); - OUTREG(index, val); - offset += 4; - break; -@@ -1096,7 +1099,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - ormask = RADEON_BIOS32(offset); - offset += 4; - ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n", -- index, andmask, ormask); -+ index, (unsigned)andmask, (unsigned)ormask); - OUTREG(RADEON_MM_INDEX, index); - val = INREG(RADEON_MM_DATA); - val = (val & andmask) | ormask; -@@ -1109,7 +1112,7 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - ormask = RADEON_BIOS32(offset); - offset += 4; - ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", -- index, andmask, ormask); -+ index, (unsigned)andmask, (unsigned)ormask); - val = INREG(index); - val = (val & andmask) | ormask; - OUTREG(index, val); -@@ -1198,7 +1201,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - offset += 2; - - ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", -- RADEON_SDRAM_MODE_MASK, ormask); -+ RADEON_SDRAM_MODE_MASK, (unsigned)ormask); - - /* can this use direct access? */ - OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); -@@ -1209,7 +1212,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - ormask = (CARD32)index << 24; - - ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", -- RADEON_B3MEM_RESET_MASK, ormask); -+ RADEON_B3MEM_RESET_MASK, (unsigned)ormask); - - /* can this use direct access? */ - OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); -@@ -1224,7 +1227,6 @@ static void - RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - { - RADEONInfoPtr info = RADEONPTR (pScrn); -- unsigned char *RADEONMMIO = info->MMIO; - CARD16 offset = table_offset; - CARD8 index, shift; - CARD32 andmask, ormask, val, clk_pwrmgt_cntl; -@@ -1298,7 +1300,7 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - offset++; - - ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", -- index, shift, andmask, ormask); -+ index, shift, (unsigned)andmask, (unsigned)ormask); - val = INPLL(pScrn, index); - val = (val & andmask) | ormask; - OUTPLL(pScrn, index, val); -@@ -1306,7 +1308,7 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - - case RADEON_PLL_FLAG_WRITE: - val = RADEON_BIOS32(offset); -- ErrorF("PLL_WRITE 0x%x 0x%x\n", index, val); -+ ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val); - OUTPLL(pScrn, index, val); - offset += 4; - break; -diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index 434034c..026cd8a 100644 ---- a/src/radeon_crtc.c -+++ b/src/radeon_crtc.c -@@ -36,7 +36,6 @@ - /* X and server generic header files */ - #include "xf86.h" - #include "xf86_OSproc.h" --#include "fbdevhw.h" - #include "vgaHW.h" - #include "xf86Modes.h" - -@@ -104,7 +103,7 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) - } - - if (mode != DPMSModeOff) -- radeon_crtc_load_lut(crtc); -+ radeon_crtc_load_lut(crtc); - } - - static Bool -@@ -666,9 +665,9 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, - save->post_div = post_div->divider; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "dc=%ld, of=%ld, fd=%d, pd=%d\n", -- save->dot_clock_freq, -- save->pll_output_freq, -+ "dc=%u, of=%u, fd=%d, pd=%d\n", -+ (unsigned)save->dot_clock_freq, -+ (unsigned)save->pll_output_freq, - save->feedback_div, - save->post_div); - -@@ -735,9 +734,9 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, - save->post_div_2 = post_div->divider; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "dc=%ld, of=%ld, fd=%d, pd=%d\n", -- save->dot_clock_freq_2, -- save->pll_output_freq_2, -+ "dc=%u, of=%u, fd=%d, pd=%d\n", -+ (unsigned)save->dot_clock_freq_2, -+ (unsigned)save->pll_output_freq_2, - save->feedback_div_2, - save->post_div_2); - -@@ -753,28 +752,34 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, - } - - static void -+radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) -+{ -+ /* pixclks_cntl controls tv clock routing */ -+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); -+} -+ -+static void - radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode, int x, int y) - { - ScrnInfoPtr pScrn = crtc->scrn; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -- xf86OutputPtr output; -- RADEONOutputPrivatePtr radeon_output; - RADEONInfoPtr info = RADEONPTR(pScrn); -- RADEONMonitorType montype = MT_NONE; - Bool tilingOld = info->tilingEnabled; - int i = 0; - double dot_clock = 0; -+ Bool no_odd_post_div = FALSE; -+ Bool update_tv_routing = FALSE; - - - if (info->allowColorTiling) { -- info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; --#ifdef XF86DRI -+ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; -+#ifdef XF86DRI - if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { - RADEONSAREAPrivPtr pSAREAPriv; - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) -- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[drm] failed changing tiling status\n"); - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); - info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; -@@ -783,11 +788,12 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - } - - for (i = 0; i < xf86_config->num_output; i++) { -- output = xf86_config->output[i]; -- radeon_output = output->driver_private; -+ xf86OutputPtr output = xf86_config->output[i]; -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (output->crtc == crtc) { -- montype = radeon_output->MonType; -+ if (radeon_output->MonType != MT_CRT) -+ no_odd_post_div = TRUE; - } - } - -@@ -820,28 +826,36 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - dot_clock = adjusted_mode->Clock / 1000.0; - if (dot_clock) { - ErrorF("init pll2\n"); -- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, montype != MT_CRT); -+ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div); - } - break; - } - -- if (montype == MT_STV || montype == MT_CTV) { -- switch (radeon_crtc->crtc_id) { -- case 0: -- RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -- RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -- break; -- case 1: -- RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -- RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -- break; -+ for (i = 0; i < xf86_config->num_output; i++) { -+ xf86OutputPtr output = xf86_config->output[i]; -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ -+ if (output->crtc == crtc) { -+ if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { -+ switch (radeon_crtc->crtc_id) { -+ case 0: -+ RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -+ RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -+ update_tv_routing = TRUE; -+ break; -+ case 1: -+ RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -+ RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); -+ break; -+ } -+ } - } - } - - ErrorF("restore memmap\n"); - RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg); - ErrorF("restore common\n"); -- RADEONRestoreCommonRegisters(pScrn, &info->ModeReg); -+ RADEONRestoreCommonRegisters(pScrn, &info->ModeReg); - - switch (radeon_crtc->crtc_id) { - case 0: -@@ -859,8 +873,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - } - - /* pixclks_cntl handles tv-out clock routing */ -- if (montype == MT_STV || montype == MT_CTV) -- RADEONRestorePLL2Registers(pScrn, &info->ModeReg); -+ if (update_tv_routing) -+ radeon_update_tv_routing(pScrn, &info->ModeReg); - - if (info->DispPriority) - RADEONInitDispBandwidth(pScrn); -@@ -897,18 +911,8 @@ void radeon_crtc_load_lut(xf86CrtcPtr crtc) - - PAL_SELECT(radeon_crtc->crtc_id); - -- if (pScrn->depth == 15) { -- for (i = 0; i < 32; i++) { -- OUTPAL(i * 8, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); -- } -- } else if (pScrn->depth == 16) { -- for (i = 0; i < 64; i++) { -- OUTPAL(i * 4, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); -- } -- } else { -- for (i = 0; i < 256; i++) { -- OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); -- } -+ for (i = 0; i < 256; i++) { -+ OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); - } - - } -@@ -920,13 +924,20 @@ radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, - { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - ScrnInfoPtr pScrn = crtc->scrn; -- int i; -+ int i, j; - - if (pScrn->depth == 16) { - for (i = 0; i < 64; i++) { -- radeon_crtc->lut_r[i] = red[i/2] >> 8; -- radeon_crtc->lut_g[i] = green[i] >> 8; -- radeon_crtc->lut_b[i] = blue[i/2] >> 8; -+ if (i <= 31) { -+ for (j = 0; j < 8; j++) { -+ radeon_crtc->lut_r[i * 8 + j] = red[i] >> 8; -+ radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 8; -+ } -+ } -+ -+ for (j = 0; j < 4; j++) { -+ radeon_crtc->lut_g[i * 4 + j] = green[i] >> 8; -+ } - } - } else { - for (i = 0; i < 256; i++) { -diff --git a/src/radeon_display.c b/src/radeon_display.c -index c51fb5d..ed45d79 100644 ---- a/src/radeon_display.c -+++ b/src/radeon_display.c -@@ -36,7 +36,6 @@ - /* X and server generic header files */ - #include "xf86.h" - #include "xf86_OSproc.h" --#include "fbdevhw.h" - #include "vgaHW.h" - #include "xf86Modes.h" - -@@ -322,6 +321,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - unsigned char * RADEONMMIO = info->MMIO; - unsigned long tmp; - RADEONOutputPrivatePtr radeon_output; -+ int tv_dac_change = 0; - radeon_output = output->driver_private; - - if (bEnable) { -@@ -332,6 +332,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - tmp |= RADEON_CRTC_CRT_ON; - OUTREG(RADEON_CRTC_EXT_CNTL, tmp); - save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; -+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); - } else if (radeon_output->DACType == DAC_TVDAC) { - if (info->ChipFamily == CHIP_FAMILY_R200) { - tmp = INREG(RADEON_FP2_GEN_CNTL); -@@ -344,8 +345,8 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); - save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; - } -+ tv_dac_change = 1; - } -- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); - } else if (radeon_output->MonType == MT_DFP) { - if (radeon_output->TMDSType == TMDS_INT) { - tmp = INREG(RADEON_FP_GEN_CNTL); -@@ -371,7 +372,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - tmp = INREG(RADEON_TV_MASTER_CNTL); - tmp |= RADEON_TV_ON; - OUTREG(RADEON_TV_MASTER_CNTL, tmp); -- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); -+ tv_dac_change = 2; - } - } else { - ErrorF("disable montype: %d\n", radeon_output->MonType); -@@ -381,6 +382,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - tmp &= ~RADEON_CRTC_CRT_ON; - OUTREG(RADEON_CRTC_EXT_CNTL, tmp); - save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; -+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); - } else if (radeon_output->DACType == DAC_TVDAC) { - if (info->ChipFamily == CHIP_FAMILY_R200) { - tmp = INREG(RADEON_FP2_GEN_CNTL); -@@ -393,8 +395,8 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); - save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; - } -+ tv_dac_change = 1; - } -- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); - } else if (radeon_output->MonType == MT_DFP) { - if (radeon_output->TMDSType == TMDS_INT) { - tmp = INREG(RADEON_FP_GEN_CNTL); -@@ -428,9 +430,22 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - tmp = INREG(RADEON_TV_MASTER_CNTL); - tmp &= ~RADEON_TV_ON; - OUTREG(RADEON_TV_MASTER_CNTL, tmp); -- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); -+ tv_dac_change = 2; - } - } -+ -+ if (tv_dac_change) { -+ if (bEnable) -+ info->tv_dac_enable_mask |= tv_dac_change; -+ else -+ info->tv_dac_enable_mask &= ~tv_dac_change; -+ -+ if (bEnable && info->tv_dac_enable_mask) -+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); -+ else if (!bEnable && info->tv_dac_enable_mask == 0) -+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); -+ -+ } - } - - /* Calculate display buffer watermark to prevent buffer underflow */ -diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index 7949c5b..24018e8 100644 ---- a/src/radeon_dri.c -+++ b/src/radeon_dri.c -@@ -69,7 +69,12 @@ static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen); - static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen); - - #ifdef DAMAGE --static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox); -+static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg); -+ -+#if (DRIINFO_MAJOR_VERSION > 5 || \ -+ (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1)) -+static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num); -+#endif - #endif - - /* Initialize the visual configs that are supported by the hardware. -@@ -398,10 +403,10 @@ static void RADEONLeaveServer(ScreenPtr pScreen) - #ifdef DAMAGE - if (info->pDamage) { - RegionPtr pDamageReg = DamageRegion(info->pDamage); -+ int nrects = pDamageReg ? REGION_NUM_RECTS(pDamageReg) : 0; - -- if (pDamageReg) { -- RADEONDRIRefreshArea(pScrn, REGION_NUM_RECTS(pDamageReg), -- REGION_RECTS(pDamageReg)); -+ if (nrects) { -+ RADEONDRIRefreshArea(pScrn, pDamageReg); - } - } - #endif -@@ -1490,6 +1495,11 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) - pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; - pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; - pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; -+#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ -+ (DRIINFO_MAJOR_VERSION == 5 && \ -+ DRIINFO_MINOR_VERSION >= 1)) -+ pDRIInfo->ClipNotify = RADEONDRIClipNotify; -+#endif - - pDRIInfo->createDummyCtx = TRUE; - pDRIInfo->createDummyCtxPriv = FALSE; -@@ -1753,7 +1763,11 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONDRICloseScreen\n"); -- -+ -+#ifdef DAMAGE -+ REGION_UNINIT(pScreen, &info->driRegion); -+#endif -+ - if (info->irq) { - RADEONDRISetVBlankInterrupt (pScrn, FALSE); - drmCtlUninstHandler(info->drmFD); -@@ -1848,15 +1862,17 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) - */ - - --static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox) -+static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- int i; -+ int i, num; - ScreenPtr pScreen = pScrn->pScreen; - RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen); - #ifdef USE_EXA - PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); - #endif -+ RegionRec region; -+ BoxPtr pbox; - - if (!info->directRenderingInited || !info->CPStarted) - return; -@@ -1867,6 +1883,17 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox) - if (!pSAREAPriv->pfAllowPageFlip && pSAREAPriv->pfCurrentPage == 0) - return; - -+ REGION_NULL(pScreen, ®ion); -+ REGION_SUBTRACT(pScreen, ®ion, pReg, &info->driRegion); -+ -+ num = REGION_NUM_RECTS(®ion); -+ -+ if (!num) { -+ goto out; -+ } -+ -+ pbox = REGION_RECTS(®ion); -+ - /* pretty much a hack. */ - - #ifdef USE_EXA -@@ -1887,7 +1914,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox) - if (!info->useEXA) { - /* Make sure accel has been properly inited */ - if (info->accel == NULL || info->accel->SetupForScreenToScreenCopy == NULL) -- return; -+ goto out; - if (info->tilingEnabled) - info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; - (*info->accel->SetupForScreenToScreenCopy)(pScrn, -@@ -1923,6 +1950,8 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox) - info->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO; - #endif - -+out: -+ REGION_NULL(pScreen, ®ion); - DamageEmpty(info->pDamage); - } - -@@ -1936,16 +1965,13 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen) - - if (info->allowPageFlip) { - RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen); -+ BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1, -+ .y2 = pScrn->virtualY - 1 }; -+ RegionPtr pReg = REGION_CREATE(pScreen, &box, 1); - - pSAREAPriv->pfAllowPageFlip = 1; -- --#ifdef USE_XAA -- if (!info->useEXA) { -- BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1, -- .y2 = pScrn->virtualY - 1 }; -- RADEONDRIRefreshArea(pScrn, 1, &box); -- } --#endif -+ RADEONDRIRefreshArea(pScrn, pReg); -+ REGION_DESTROY(pScreen, pReg); - } - #endif - } -@@ -2101,6 +2127,33 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen) - xf86ForceHWCursor (pScreen, FALSE); - } - -+#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ -+ (DRIINFO_MAJOR_VERSION == 5 && \ -+ DRIINFO_MINOR_VERSION >= 1)) -+static void -+RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num) -+{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+ REGION_UNINIT(pScreen, &info->driRegion); -+ REGION_NULL(pScreen, &info->driRegion); -+ -+ if (num > 0) { -+ int i; -+ -+ for (i = 0; i < num; i++) { -+ WindowPtr pWin = ppWin[i]; -+ -+ if (pWin) { -+ REGION_UNION(pScreen, &info->driRegion, &pWin->clipList, -+ &info->driRegion); -+ } -+ } -+ } -+} -+#endif -+ - void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen) - { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 1f4d0c2..158e1e4 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c -@@ -98,11 +98,10 @@ - #include "xf86cmap.h" - #include "vbe.h" - -- /* fbdevhw * vgaHW definitions */ -+ /* vgaHW definitions */ - #ifdef WITH_VGAHW - #include "vgaHW.h" - #endif --#include "fbdevhw.h" - - #define DPMS_SERVER - #include -@@ -159,7 +158,6 @@ static const OptionInfoRec RADEONOptions[] = { - #endif - { OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, -- { OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, -@@ -208,34 +206,6 @@ static const char *vgahwSymbols[] = { - }; - #endif - --static const char *fbdevHWSymbols[] = { -- "fbdevHWInit", -- "fbdevHWUseBuildinMode", -- -- "fbdevHWGetVidmem", -- -- "fbdevHWDPMSSet", -- -- /* colormap */ -- "fbdevHWLoadPalette", -- /* ScrnInfo hooks */ -- "fbdevHWAdjustFrame", -- "fbdevHWEnterVT", -- "fbdevHWLeaveVT", -- "fbdevHWModeInit", -- "fbdevHWRestore", -- "fbdevHWSave", -- "fbdevHWSwitchMode", -- "fbdevHWValidModeWeak", -- -- "fbdevHWMapMMIO", -- "fbdevHWMapVidmem", -- "fbdevHWUnmapMMIO", -- "fbdevHWUnmapVidmem", -- -- NULL --}; -- - static const char *ddcSymbols[] = { - "xf86PrintEDID", - "xf86DoEDID_DDC1", -@@ -396,7 +366,6 @@ void RADEONLoaderRefSymLists(void) - drmSymbols, - driSymbols, - #endif -- fbdevHWSymbols, - vbeSymbols, - int10Symbols, - i2cSymbols, -@@ -553,15 +522,11 @@ static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - -- if (info->FBDev) { -- info->MMIO = fbdevHWMapMMIO(pScrn); -- } else { -- info->MMIO = xf86MapPciMem(pScrn->scrnIndex, -- VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, -- info->PciTag, -- info->MMIOAddr, -- info->MMIOSize); -- } -+ info->MMIO = xf86MapPciMem(pScrn->scrnIndex, -+ VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, -+ info->PciTag, -+ info->MMIOAddr, -+ info->MMIOSize); - - if (!info->MMIO) return FALSE; - return TRUE; -@@ -574,11 +539,8 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - -- if (info->FBDev) -- fbdevHWUnmapMMIO(pScrn); -- else { -- xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); -- } -+ xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); -+ - info->MMIO = NULL; - return TRUE; - } -@@ -588,17 +550,13 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - -- if (info->FBDev) { -- info->FB = fbdevHWMapVidmem(pScrn); -- } else { -- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); -- info->FB = xf86MapPciMem(pScrn->scrnIndex, -- VIDMEM_FRAMEBUFFER, -- info->PciTag, -- info->LinearAddr, -- info->FbMapSize); -- } -+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -+ "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); -+ info->FB = xf86MapPciMem(pScrn->scrnIndex, -+ VIDMEM_FRAMEBUFFER, -+ info->PciTag, -+ info->LinearAddr, -+ info->FbMapSize); - - if (!info->FB) return FALSE; - return TRUE; -@@ -609,10 +567,7 @@ static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - -- if (info->FBDev) -- fbdevHWUnmapVidmem(pScrn); -- else -- xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); -+ xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); - info->FB = NULL; - return TRUE; - } -@@ -724,7 +679,7 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - CARD32 crtc_gen_cntl; -- int i; -+ struct timeval timeout; - - crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); - if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || -@@ -735,10 +690,10 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) - OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); - - /* Wait for it to go back up */ -- for (i = 0; i < RADEON_TIMEOUT/1000; i++) { -- if (INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) break; -- usleep(1); -- } -+ radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); -+ while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && -+ !radeon_timedout(&timeout)) -+ usleep(100); - } - - /* Wait for vertical sync on secondary CRTC */ -@@ -747,7 +702,7 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - CARD32 crtc2_gen_cntl; -- int i; -+ struct timeval timeout; - - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || -@@ -758,10 +713,10 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) - OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); - - /* Wait for it to go back up */ -- for (i = 0; i < RADEON_TIMEOUT/1000; i++) { -- if (INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) break; -- usleep(1); -- } -+ radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); -+ while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && -+ !radeon_timedout(&timeout)) -+ usleep(100); - } - - -@@ -1051,10 +1006,11 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) - } - - xf86DrvMsg (pScrn->scrnIndex, X_INFO, -- "PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n", -+ "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n", - pll->reference_freq, - pll->reference_div, -- pll->min_pll_freq, pll->max_pll_freq, pll->xclk); -+ (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq, -+ pll->xclk); - - /* (Some?) Radeon BIOSes seem too lie about their minimum dot - * clocks. Allow users to override the detected minimum dot clock -@@ -1182,7 +1138,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- unsigned long mem_size; -+ CARD32 mem_size; - CARD32 aper_size; - - /* Default to existing values */ -@@ -1210,8 +1166,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - } - #endif - -- /* We won't try to change MC_FB_LOCATION when using fbdev */ -- if (!info->FBDev) { -+ { - if (info->IsIGP) - info->mc_fb_location = INREG(RADEON_NB_TOM); - else -@@ -1254,11 +1209,12 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "RADEONInitMemoryMap() : \n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- " mem_size : 0x%08lx\n", mem_size); -+ " mem_size : 0x%08x\n", (unsigned)mem_size); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- " MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location); -+ " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- " MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location); -+ " MC_AGP_LOCATION : 0x%08x\n", -+ (unsigned)info->mc_agp_location); - } - - static void RADEONGetVRamType(ScrnInfoPtr pScrn) -@@ -1321,8 +1277,8 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) - if (info->directRenderingEnabled && - info->pKernelDRMVersion->version_minor < 23) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "[dri] limiting video memory to one aperture of %ldK\n", -- aper_size); -+ "[dri] limiting video memory to one aperture of %uK\n", -+ (unsigned)aper_size); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "[dri] detected radeon kernel module version 1.%d but" - " 1.23 or newer is required for full memory mapping.\n", -@@ -1378,9 +1334,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) - MessageType from = X_PROBED; - CARD32 accessible, bar_size; - -- if (info->FBDev) -- pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024; -- else if ((info->IsIGP)) { -+ if ((info->IsIGP)) { - CARD32 tom = INREG(RADEON_NB_TOM); - - pScrn->videoRam = (((tom >> 16) - -@@ -1409,8 +1363,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) - accessible = bar_size; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "Detected total video RAM=%dK, accessible=%ldK (PCI BAR=%ldK)\n", -- pScrn->videoRam, accessible, bar_size); -+ "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", -+ pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); - if (pScrn->videoRam > accessible) - pScrn->videoRam = accessible; - -@@ -2291,12 +2245,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) - } - #endif /* XF86DRI */ - -- if ((info->allowColorTiling) && (info->FBDev)) { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Color tiling not supported with UseFBDev option\n"); -- info->allowColorTiling = FALSE; -- } -- else if (info->allowColorTiling) { -+ if (info->allowColorTiling) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); -@@ -2713,30 +2662,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - "X server will %skeep DPI constant for all screen sizes\n", - info->constantDPI ? "" : "not "); - -- if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, FALSE)) { -- /* check for Linux framebuffer device */ -- -- if (xf86LoadSubModule(pScrn, "fbdevhw")) { -- xf86LoaderReqSymLists(fbdevHWSymbols, NULL); -- -- if (fbdevHWInit(pScrn, info->PciInfo, NULL)) { -- pScrn->ValidMode = fbdevHWValidModeWeak(); -- info->FBDev = TRUE; -- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, -- "Using framebuffer device\n"); -- } else { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "fbdevHWInit failed, not using framebuffer device\n"); -- } -- } else { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Couldn't load fbdevhw module, not using framebuffer device\n"); -- } -- } -- -- if (!info->FBDev) -- if (!RADEONPreInitInt10(pScrn, &pInt10)) -- goto fail; -+ if (!RADEONPreInitInt10(pScrn, &pInt10)) -+ goto fail; - - RADEONPostInt10Check(pScrn, int10_save); - -@@ -2772,9 +2699,26 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - crtc_max_Y = 8192; - } - } else { -- crtc_max_X = 1600; -- crtc_max_Y = 1200; -+ if (pScrn->videoRam < 16384) { -+ crtc_max_X = 1600; -+ crtc_max_Y = 1200; -+ } else if (pScrn->videoRam <= 32768) { -+ crtc_max_X = 2048; -+ crtc_max_Y = 1200; -+ } else if (pScrn->videoRam > 32768) { -+ if (IS_R300_VARIANT) { -+ crtc_max_X = 2560; -+ crtc_max_Y = 2048; -+ } else { -+ crtc_max_X = 2048; -+ crtc_max_Y = 2048; -+ } -+ } - } -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", -+ crtc_max_X, crtc_max_Y); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, -+ "For a larger or smaller max desktop size, add a Virtual line to your xorg.conf\n"); - - /*xf86CrtcSetSizeRange (pScrn, 320, 200, info->MaxSurfaceWidth, info->MaxLines);*/ - xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y); -@@ -2887,9 +2831,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, - if (info->accelOn && pScrn->pScreen) - RADEON_SYNC(info, pScrn); - -- if (info->FBDev) { -- fbdevHWLoadPalette(pScrn, numColors, indices, colors, pVisual); -- } else { -+ { - - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86CrtcPtr crtc = xf86_config->crtc[c]; -@@ -2914,7 +2856,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, - case 16: - for (i = 0; i < numColors; i++) { - index = indices[i]; -- -+ - if (i <= 31) { - for (j = 0; j < 8; j++) { - lut_r[index * 8 + j] = colors[index].red << 8; -@@ -2932,7 +2874,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, - lut_r[index] = colors[index].red << 8; - lut_g[index] = colors[index].green << 8; - lut_b[index] = colors[index].blue << 8; -- } -+ } - break; - } - -@@ -3231,8 +3173,8 @@ Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) - info->depthOffset); - if (info->cardType==CARD_PCIE) - xf86DrvMsg(scrnIndex, X_INFO, -- "Will use %d kb for PCI GART table at offset 0x%lx\n", -- info->pciGartSize/1024, info->pciGartOffset); -+ "Will use %d kb for PCI GART table at offset 0x%x\n", -+ info->pciGartSize/1024, (unsigned)info->pciGartOffset); - xf86DrvMsg(scrnIndex, X_INFO, - "Will use %d kb for textures at offset 0x%x\n", - info->textureSize/1024, info->textureOffset); -@@ -3346,6 +3288,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int hasDRI = 0; -+ int i; - #ifdef RENDER - int subPixelOrder = SubPixelUnknown; - char* s; -@@ -3446,11 +3389,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - - /* empty the surfaces */ - unsigned char *RADEONMMIO = info->MMIO; -- unsigned int i; -- for (i = 0; i < 8; i++) { -- OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0); -- OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0); -- OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0); -+ unsigned int j; -+ for (j = 0; j < 8; j++) { -+ OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); -+ OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); -+ OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); - } - - #ifdef XF86DRI -@@ -3623,35 +3566,22 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - #endif - - pScrn->vtSema = TRUE; -- if (info->FBDev) { -- unsigned char *RADEONMMIO = info->MMIO; - -- if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE; -- pScrn->displayWidth = fbdevHWGetLineLength(pScrn) -- / info->CurrentLayout.pixel_bytes; -- RADEONSaveMemMapRegisters(pScrn, &info->ModeReg); -- info->fbLocation = (info->ModeReg.mc_fb_location & 0xffff) << 16; -- info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); -- info->ModeReg.surface_cntl &= ~RADEON_SURF_TRANSLATION_DIS; -- } else { -- int i; -- for (i = 0; i < xf86_config->num_crtc; i++) -- { -- xf86CrtcPtr crtc = xf86_config->crtc[i]; -+ for (i = 0; i < xf86_config->num_crtc; i++) { -+ xf86CrtcPtr crtc = xf86_config->crtc[i]; - -- /* Mark that we'll need to re-set the mode for sure */ -- memset(&crtc->mode, 0, sizeof(crtc->mode)); -- if (!crtc->desiredMode.CrtcHDisplay) { -- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode); -- crtc->desiredRotation = RR_Rotate_0; -- crtc->desiredX = 0; -- crtc->desiredY = 0; -- } -+ /* Mark that we'll need to re-set the mode for sure */ -+ memset(&crtc->mode, 0, sizeof(crtc->mode)); -+ if (!crtc->desiredMode.CrtcHDisplay) { -+ crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode); -+ crtc->desiredRotation = RR_Rotate_0; -+ crtc->desiredX = 0; -+ crtc->desiredY = 0; -+ } - -- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, crtc->desiredX, crtc->desiredY)) -- return FALSE; -+ if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, crtc->desiredX, crtc->desiredY)) -+ return FALSE; - -- } - } - - RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); -@@ -3755,9 +3685,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - int width, height; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "Using hardware cursor (scanline %ld)\n", -- info->cursor_offset / pScrn->displayWidth -- / info->CurrentLayout.pixel_bytes); -+ "Using hardware cursor (scanline %u)\n", -+ (unsigned)(info->cursor_offset / pScrn->displayWidth -+ / info->CurrentLayout.pixel_bytes)); - if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, - 0, 0, 0)) { - xf86DrvMsg(scrnIndex, X_INFO, -@@ -3835,9 +3765,11 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "RADEONRestoreMemMapRegisters() : \n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- " MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location); -+ " MC_FB_LOCATION : 0x%08x\n", -+ (unsigned)restore->mc_fb_location); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- " MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location); -+ " MC_AGP_LOCATION : 0x%08x\n", -+ (unsigned)restore->mc_agp_location); - - /* Write memory mapping registers only if their value change - * since we must ensure no access is done while they are -@@ -3982,21 +3914,19 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - CARD32 fb, agp; -- int fb_loc_changed; - - fb = INREG(RADEON_MC_FB_LOCATION); - agp = INREG(RADEON_MC_AGP_LOCATION); -- fb_loc_changed = (fb != info->mc_fb_location); - -- if (fb_loc_changed || agp != info->mc_agp_location) { -+ if (fb != info->mc_fb_location || agp != info->mc_agp_location) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "DRI init changed memory map, adjusting ...\n"); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", -- info->mc_fb_location, fb); -+ " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n", -+ (unsigned)info->mc_fb_location, (unsigned)fb); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", -- info->mc_agp_location, agp); -+ " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n", -+ (unsigned)info->mc_agp_location, (unsigned)agp); - info->mc_fb_location = fb; - info->mc_agp_location = agp; - info->fbLocation = (save->mc_fb_location & 0xffff) << 16; -@@ -4007,9 +3937,8 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - - RADEONInitMemMapRegisters(pScrn, save, info); - -- /* If MC_FB_LOCATION was changed, adjust the various offsets */ -- if (fb_loc_changed) -- RADEONRestoreMemMapRegisters(pScrn, save); -+ /* Adjust the various offsets */ -+ RADEONRestoreMemMapRegisters(pScrn, save); - } - - #ifdef USE_EXA -@@ -4072,32 +4001,6 @@ void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, - } - } - --/* Write miscellaneous registers which might have been destroyed by an fbdevHW -- * call -- */ --static void RADEONRestoreFBDevRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore) --{ --#ifdef XF86DRI -- RADEONInfoPtr info = RADEONPTR(pScrn); -- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -- unsigned char *RADEONMMIO = info->MMIO; -- -- /* Restore register for vertical blank interrupts */ -- if (info->irq) { -- OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl); -- } -- -- /* Restore registers for page flipping */ -- if (info->allowPageFlip) { -- OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); -- if (pRADEONEnt->HasCRTC2) { -- OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); -- } -- } --#endif --} -- - void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore) - { -@@ -4142,8 +4045,8 @@ void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, - unsigned char *RADEONMMIO = info->MMIO; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Programming CRTC1, offset: 0x%08lx\n", -- restore->crtc_offset); -+ "Programming CRTC1, offset: 0x%08x\n", -+ (unsigned)restore->crtc_offset); - - /* We prevent the CRTC from hitting the memory controller until - * fully programmed -@@ -4195,8 +4098,8 @@ void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, - /* CARD32 crtc2_gen_cntl;*/ - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Programming CRTC2, offset: 0x%08lx\n", -- restore->crtc2_offset); -+ "Programming CRTC2, offset: 0x%08x\n", -+ (unsigned)restore->crtc2_offset); - - /* We prevent the CRTC from hitting the memory controller until - * fully programmed -@@ -4748,10 +4651,10 @@ void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, - | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n", -+ "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", - restore->ppll_ref_div, - restore->ppll_div_3, -- restore->htotal_cntl, -+ (unsigned)restore->htotal_cntl, - INPLL(pScrn, RADEON_PPLL_CNTL)); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote: rd=%d, fd=%d, pd=%d\n", -@@ -4821,16 +4724,17 @@ void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, - | RADEON_P2PLL_ATOMIC_UPDATE_EN)); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Wrote2: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", -- restore->p2pll_ref_div, -- restore->p2pll_div_0, -- restore->htotal_cntl2, -+ "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", -+ (unsigned)restore->p2pll_ref_div, -+ (unsigned)restore->p2pll_div_0, -+ (unsigned)restore->htotal_cntl2, - INPLL(pScrn, RADEON_P2PLL_CNTL)); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Wrote2: rd=%ld, fd=%ld, pd=%ld\n", -- restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, -- restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, -- (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16); -+ "Wrote2: rd=%u, fd=%u, pd=%u\n", -+ (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, -+ (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, -+ (unsigned)((restore->p2pll_div_0 & -+ RADEON_P2PLL_POST0_DIV_MASK) >>16)); - - usleep(5000); /* Let the clock to lock */ - -@@ -5060,29 +4964,6 @@ static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); - } - --/* Read miscellaneous registers which might be destroyed by an fbdevHW call */ --static void RADEONSaveFBDevRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) --{ --#ifdef XF86DRI -- RADEONInfoPtr info = RADEONPTR(pScrn); -- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -- unsigned char *RADEONMMIO = info->MMIO; -- -- /* Save register for vertical blank interrupts */ -- if (info->irq) { -- save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); -- } -- -- /* Save registers for page flipping */ -- if (info->allowPageFlip) { -- save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); -- if (pRADEONEnt->HasCRTC2) { -- save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); -- } -- } --#endif --} -- - /* Read CRTC registers */ - static void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - { -@@ -5306,10 +5187,10 @@ static void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Read: 0x%08x 0x%08x 0x%08lx\n", -+ "Read: 0x%08x 0x%08x 0x%08x\n", - save->ppll_ref_div, - save->ppll_div_3, -- save->htotal_cntl); -+ (unsigned)save->htotal_cntl); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Read: rd=%d, fd=%d, pd=%d\n", - save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, -@@ -5326,15 +5207,16 @@ static void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) - save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Read: 0x%08lx 0x%08lx 0x%08lx\n", -- save->p2pll_ref_div, -- save->p2pll_div_0, -- save->htotal_cntl2); -+ "Read: 0x%08x 0x%08x 0x%08x\n", -+ (unsigned)save->p2pll_ref_div, -+ (unsigned)save->p2pll_div_0, -+ (unsigned)save->htotal_cntl2); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Read: rd=%ld, fd=%ld, pd=%ld\n", -- save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, -- save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, -- (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16); -+ "Read: rd=%u, fd=%u, pd=%u\n", -+ (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK), -+ (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK), -+ (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) -+ >> 16)); - } - - /* Read palette data */ -@@ -5391,13 +5273,6 @@ static void RADEONSave(ScrnInfoPtr pScrn) - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONSave\n"); - -- if (info->FBDev) { -- RADEONSaveMemMapRegisters(pScrn, save); -- fbdevHWSave(pScrn); -- return; -- } -- -- - #ifdef WITH_VGAHW - if (info->VGAAccess) { - vgaHWPtr hwp = VGAHWPTR(pScrn); -@@ -5444,10 +5319,6 @@ void RADEONRestore(ScrnInfoPtr pScrn) - OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); - #endif - -- if (info->FBDev) { -- fbdevHWRestore(pScrn); -- return; -- } - RADEONBlank(pScrn); - - OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); -@@ -5615,17 +5486,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) - if (info->accelOn) - RADEON_SYNC(info, pScrn); - -- if (info->FBDev) { -- RADEONSaveFBDevRegisters(pScrn, &info->ModeReg); -- -- ret = fbdevHWSwitchMode(scrnIndex, mode, flags); -- pScrn->displayWidth = fbdevHWGetLineLength(pScrn) -- / info->CurrentLayout.pixel_bytes; -- -- RADEONRestoreFBDevRegisters(pScrn, &info->ModeReg); -- } else { -- ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); -- } -+ ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); - - if (info->tilingEnabled != tilingOld) { - /* need to redraw front buffer, I guess this can be considered a hack ? */ -@@ -5821,14 +5682,10 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) - RADEON_SYNC(info, pScrn); - - if (crtc && crtc->enabled) { -- if (info->FBDev) { -- fbdevHWAdjustFrame(scrnIndex, crtc->desiredX + x, crtc->desiredY + y, flags); -- } else { -- if (crtc == pRADEONEnt->pCrtc[0]) -- RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); -- else -- RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); -- } -+ if (crtc == pRADEONEnt->pCrtc[0]) -+ RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); -+ else -+ RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); - crtc->x = output->initial_x + x; - crtc->y = output->initial_y + y; - } -@@ -5848,11 +5705,12 @@ Bool RADEONEnterVT(int scrnIndex, int flags) - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -+ int i; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONEnterVT\n"); - -- if (INREG(RADEON_CONFIG_MEMSIZE) == 0) { /* Softboot V_BIOS */ -+ if ((INREG(RADEON_CONFIG_MEMSIZE)) == 0) { /* Softboot V_BIOS */ - xf86Int10InfoPtr pInt; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); -@@ -5867,34 +5725,22 @@ Bool RADEONEnterVT(int scrnIndex, int flags) - /* Makes sure the engine is idle before doing anything */ - RADEONWaitForIdleMMIO(pScrn); - -- if (info->FBDev) { -- unsigned char *RADEONMMIO = info->MMIO; -- if (!fbdevHWEnterVT(scrnIndex,flags)) return FALSE; -- info->PaletteSavedOnVT = FALSE; -- info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); -- -- RADEONRestoreFBDevRegisters(pScrn, &info->ModeReg); -- } else { -- int i; -- -- pScrn->vtSema = TRUE; -- for (i = 0; i < xf86_config->num_crtc; i++) -- { -- xf86CrtcPtr crtc = xf86_config->crtc[i]; -- /* Mark that we'll need to re-set the mode for sure */ -- memset(&crtc->mode, 0, sizeof(crtc->mode)); -- if (!crtc->desiredMode.CrtcHDisplay) { -- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode); -- crtc->desiredRotation = RR_Rotate_0; -- crtc->desiredX = 0; -- crtc->desiredY = 0; -- } -+ pScrn->vtSema = TRUE; -+ for (i = 0; i < xf86_config->num_crtc; i++) { -+ xf86CrtcPtr crtc = xf86_config->crtc[i]; -+ /* Mark that we'll need to re-set the mode for sure */ -+ memset(&crtc->mode, 0, sizeof(crtc->mode)); -+ if (!crtc->desiredMode.CrtcHDisplay) { -+ crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode); -+ crtc->desiredRotation = RR_Rotate_0; -+ crtc->desiredX = 0; -+ crtc->desiredY = 0; -+ } - -- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, -- crtc->desiredX, crtc->desiredY)) -- return FALSE; -+ if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, -+ crtc->desiredX, crtc->desiredY)) -+ return FALSE; - -- } - } - - RADEONRestoreSurfaces(pScrn, &info->ModeReg); -@@ -5940,7 +5786,6 @@ void RADEONLeaveVT(int scrnIndex, int flags) - { - ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); -- RADEONSavePtr save = &info->ModeReg; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONLeaveVT\n"); -@@ -5972,15 +5817,6 @@ void RADEONLeaveVT(int scrnIndex, int flags) - } - #endif - -- if (info->FBDev) { -- RADEONSavePalette(pScrn, save); -- info->PaletteSavedOnVT = TRUE; -- -- RADEONSaveFBDevRegisters(pScrn, &info->ModeReg); -- -- fbdevHWLeaveVT(scrnIndex,flags); -- } -- - RADEONRestore(pScrn); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -diff --git a/src/radeon_output.c b/src/radeon_output.c -index 9650a39..c2b749a 100644 ---- a/src/radeon_output.c -+++ b/src/radeon_output.c -@@ -36,7 +36,6 @@ - /* X and server generic header files */ - #include "xf86.h" - #include "xf86_OSproc.h" --#include "fbdevhw.h" - #include "vgaHW.h" - #include "xf86Modes.h" - -@@ -77,7 +76,7 @@ const char *TMDSTypeName[4] = { - }; - - const char *DDCTypeName[6] = { -- "NONE", -+ "None", - "MONID", - "DVI_DDC", - "VGA_DDC", -@@ -580,7 +579,6 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr - - - if (radeon_output->type == OUTPUT_LVDS) { -- if (INREG(RADEON_BIOS_4_SCRATCH) & 4) - MonType = MT_LCD; - } else if (radeon_output->type == OUTPUT_DVI) { - if (radeon_output->TMDSType == TMDS_INT) { -@@ -654,8 +652,6 @@ static Bool - radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, - DisplayModePtr adjusted_mode) - { -- ScrnInfoPtr pScrn = output->scrn; -- RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) { -@@ -848,21 +844,22 @@ static void RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, - if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) { - save->fp_horz_stretch |= ((xres/8-1)<<16); - } else { -- save->fp_horz_stretch |= ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX + -- 0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK) | -- RADEON_HORZ_STRETCH_BLEND | -- RADEON_HORZ_STRETCH_ENABLE | -- ((radeon_output->PanelXRes/8-1)<<16)); -+ save->fp_horz_stretch |= ((((unsigned long) -+ (Hratio * RADEON_HORZ_STRETCH_RATIO_MAX)) & -+ RADEON_HORZ_STRETCH_RATIO_MASK) | -+ RADEON_HORZ_STRETCH_BLEND | -+ RADEON_HORZ_STRETCH_ENABLE | -+ ((radeon_output->PanelXRes/8-1)<<16)); - } - - if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) { - save->fp_vert_stretch |= ((yres-1)<<12); - } else { -- save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX + -- 0.5)) & RADEON_VERT_STRETCH_RATIO_MASK) | -- RADEON_VERT_STRETCH_ENABLE | -- RADEON_VERT_STRETCH_BLEND | -- ((radeon_output->PanelYRes-1)<<12)); -+ save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX)) & -+ RADEON_VERT_STRETCH_RATIO_MASK) | -+ RADEON_VERT_STRETCH_ENABLE | -+ RADEON_VERT_STRETCH_BLEND | -+ ((radeon_output->PanelYRes-1)<<12)); - } - - } -@@ -1228,12 +1225,9 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) - - /* save the regs we need */ - pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); -- if (IS_R300_VARIANT) { -- gpiopad_a = INREG(RADEON_GPIOPAD_A); -- disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); -- } else { -- disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG); -- } -+ gpiopad_a = IS_R300_VARIANT ? INREG(RADEON_GPIOPAD_A) : 0; -+ disp_output_cntl = IS_R300_VARIANT ? INREG(RADEON_DISP_OUTPUT_CNTL) : 0; -+ disp_hw_debug = !IS_R300_VARIANT ? INREG(RADEON_DISP_HW_DEBUG) : 0; - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); -@@ -2285,10 +2279,7 @@ RADEONGetTMDSInfo(xf86OutputPtr output) - static void - RADEONGetTVInfo(xf86OutputPtr output) - { -- ScrnInfoPtr pScrn = output->scrn; -- RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; -- int i; - - radeon_output->hPos = 0; - radeon_output->vPos = 0; -diff --git a/src/radeon_probe.c b/src/radeon_probe.c -index d7ff643..c697f65 100644 ---- a/src/radeon_probe.c -+++ b/src/radeon_probe.c -@@ -303,6 +303,7 @@ RADEONProbe(DriverPtr drv, int flags) - foundScreen = TRUE; - } - -+ xfree(pEnt); - pEnt = xf86GetEntityInfo(usedChips[i]); - - /* create a RADEONEntity for all chips, even with -diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 9eae40d..af62a69 100644 ---- a/src/radeon_reg.h -+++ b/src/radeon_reg.h -@@ -1094,6 +1094,7 @@ - # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L - # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L - # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L -+# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L - #define RADEON_OV0_SCALE_CNTL 0x0420 - # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L - # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L -diff --git a/src/radeon_tv.c b/src/radeon_tv.c -index 522f7ed..c5917bc 100644 ---- a/src/radeon_tv.c -+++ b/src/radeon_tv.c -@@ -13,7 +13,6 @@ - /* X and server generic header files */ - #include "xf86.h" - #include "xf86_OSproc.h" --#include "fbdevhw.h" - #include "vgaHW.h" - #include "xf86Modes.h" - -@@ -187,9 +186,7 @@ static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; - static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode) - { -- ScrnInfoPtr pScrn = output->scrn; - RADEONOutputPrivatePtr radeon_output = output->driver_private; -- RADEONInfoPtr info = RADEONPTR(pScrn); - int restart; - unsigned hTotal; - unsigned vTotal; -@@ -274,7 +271,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, - save->tv_frestart = restart % fTotal; - - ErrorF("computeRestarts: F/H/V=%u,%u,%u\n", -- save->tv_frestart , save->tv_vrestart , save->tv_hrestart); -+ (unsigned)save->tv_frestart, (unsigned)save->tv_vrestart, -+ (unsigned)save->tv_hrestart); - - /* Compute H_INC from hSize */ - if (radeon_output->tvStd == TV_STD_NTSC || -@@ -570,7 +568,6 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode) - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- RADEONOutputPrivatePtr radeon_output = output->driver_private; - Bool reloadTable; - RADEONSavePtr restore = &info->ModeReg; - -diff --git a/src/radeon_video.c b/src/radeon_video.c -index a38931c..271f7fe 100644 ---- a/src/radeon_video.c -+++ b/src/radeon_video.c -@@ -1325,21 +1325,21 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) - } else { - t->wComp0Connector=RT_COMP1; - } -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Composite connector is port %ld\n", t->wComp0Connector); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Composite connector is port %u\n", (unsigned)t->wComp0Connector); - break; - case 3: if(a & 0x4){ - t->wSVideo0Connector=RT_YCR_COMP4; - } else { - t->wSVideo0Connector=RT_YCF_COMP4; - } -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SVideo connector is port %ld\n", t->wSVideo0Connector); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SVideo connector is port %u\n", (unsigned)t->wSVideo0Connector); - break; - default: - break; - } - } -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rage Theatre: Connectors (detected): tuner=%ld, composite=%ld, svideo=%ld\n", -- t->wTunerConnector, t->wComp0Connector, t->wSVideo0Connector); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rage Theatre: Connectors (detected): tuner=%u, composite=%u, svideo=%u\n", -+ (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector); - - } - -@@ -1347,8 +1347,8 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) - if(info->RageTheatreCompositePort>=0)t->wComp0Connector=info->RageTheatreCompositePort; - if(info->RageTheatreSVideoPort>=0)t->wSVideo0Connector=info->RageTheatreSVideoPort; - -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RageTheatre: Connectors (using): tuner=%ld, composite=%ld, svideo=%ld\n", -- t->wTunerConnector, t->wComp0Connector, t->wSVideo0Connector); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RageTheatre: Connectors (using): tuner=%u, composite=%u, svideo=%u\n", -+ (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector); - - switch((info->RageTheatreCrystal>=0)?info->RageTheatreCrystal:pll->reference_freq){ - case 2700: -@@ -1437,9 +1437,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) - info->ecp_div = 1; - ecp = (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (info->ecp_div << 8); - -- if ((info->ChipFamily == CHIP_FAMILY_RS100) || -- (info->ChipFamily == CHIP_FAMILY_RS200) || -- (info->ChipFamily == CHIP_FAMILY_RS300)) { -+ if (info->IsIGP) { - /* Force the overlay clock on for integrated chips - */ - ecp |= (1<<18); -@@ -1564,7 +1562,7 @@ RADEONSetupImageVideo(ScreenPtr pScreen) - return NULL; - - adapt->type = XvWindowMask | XvInputMask | XvImageMask; -- adapt->flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; -+ adapt->flags = VIDEO_OVERLAID_IMAGES /*| VIDEO_CLIP_TO_VIEWPORT*/; - adapt->name = "ATI Radeon Video Overlay"; - adapt->nEncodings = 1; - adapt->pEncodings = &DummyEncoding; -@@ -1883,7 +1881,8 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, - else if(attribute == xvAdjustment) - { - pPriv->adjustment=value; -- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Setting pPriv->adjustment to %ld\n", pPriv->adjustment); -+ xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Setting pPriv->adjustment to %u\n", -+ (unsigned)pPriv->adjustment); - if(pPriv->tda9885!=0){ - pPriv->tda9885->top_adjustment=value; - RADEON_TDA9885_SetEncoding(pPriv); -@@ -2589,20 +2588,19 @@ RADEONDisplayVideo( - y_mult = 2; - } - -+ v_inc = (src_h << v_inc_shift) / drw_h; -+ - for (i = 0; i < xf86_config->num_output; i++) { - output = xf86_config->output[i]; - if (output->crtc == crtc) { - radeon_output = output->driver_private; -+ if (radeon_output->Flags & RADEON_USE_RMX) -+ v_inc = ((src_h * mode->CrtcVDisplay / -+ radeon_output->PanelYRes) << v_inc_shift) / drw_h; - break; - } - } - -- if (radeon_output->Flags & RADEON_USE_RMX) { -- v_inc = ((src_h * mode->CrtcVDisplay / radeon_output->PanelYRes) << v_inc_shift) / drw_h; -- } else { -- v_inc = (src_h << v_inc_shift) / drw_h; -- } -- - h_inc = (1 << (12 + ecp_div)); - - step_by_y = 1; -@@ -2862,7 +2860,6 @@ RADEONPutImage( - DrawablePtr pDraw - ){ - RADEONInfoPtr info = RADEONPTR(pScrn); -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - INT32 xa, xb, ya, yb; - unsigned char *dst_start; -@@ -2966,8 +2963,14 @@ RADEONPutImage( - - offset = (pPriv->video_offset) + (top * dstPitch); - -- if(pPriv->doubleBuffer) -+ if(pPriv->doubleBuffer) { -+ unsigned char *RADEONMMIO = info->MMIO; -+ -+ /* Wait for last flip to take effect */ -+ while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_FLIP_READBACK)); -+ - offset += pPriv->currentBuffer * new_size; -+ } - - dst_start = info->FB + offset; - -@@ -3255,7 +3258,6 @@ RADEONDisplaySurface( - ){ - OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr; - ScrnInfoPtr pScrn = surface->pScrn; -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr; - -@@ -3328,8 +3330,8 @@ RADEONInitOffscreenImages(ScreenPtr pScreen) - return; - - offscreenImages[0].image = &Images[0]; -- offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES | -- VIDEO_CLIP_TO_VIEWPORT; -+ offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES /*| -+ VIDEO_CLIP_TO_VIEWPORT*/; - offscreenImages[0].alloc_surface = RADEONAllocateSurface; - offscreenImages[0].free_surface = RADEONFreeSurface; - offscreenImages[0].display = RADEONDisplaySurface; -@@ -3358,7 +3360,6 @@ RADEONPutVideo( - ){ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - INT32 xa, xb, ya, yb, top; - unsigned int pitch, new_size, alloc_size; -@@ -3372,7 +3373,6 @@ RADEONPutVideo( - int mult; - int vbi_line_width, vbi_start, vbi_end; - xf86CrtcPtr crtc; -- RADEONCrtcPrivatePtr radeon_crtc; - - RADEON_SYNC(info, pScrn); - /* -@@ -3444,7 +3444,8 @@ RADEONPutVideo( - id = FOURCC_YUY2; - - top = ya>>16; -- -+#if 0 -+ /* setting the ID above makes this useful - needs revisiting */ - switch(id) { - case FOURCC_YV12: - case FOURCC_I420: -@@ -3462,6 +3463,10 @@ RADEONPutVideo( - srcPitch = (width<<1); - break; - } -+#else -+ dstPitch = ((width<<1) + 15) & ~15; -+ srcPitch = (width<<1); -+#endif - - new_size = dstPitch * height; - new_size = new_size + 0x1f; /* for aligning */ -diff --git a/src/theatre.c b/src/theatre.c -index 0a635fa..a5aadfb 100644 ---- a/src/theatre.c -+++ b/src/theatre.c -@@ -1796,7 +1796,9 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) - counter++; - } - dwTempContrast = ReadRT_fld (fld_LP_CONTRAST); -- if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Rage Theatre: timeout waiting for line count (%ld)\n", ReadRT_fld (fld_VS_LINE_COUNT)); -+ if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO, -+ "Rage Theatre: timeout waiting for line count (%u)\n", -+ (unsigned)ReadRT_fld (fld_VS_LINE_COUNT)); - - - WriteRT_fld (fld_LP_CONTRAST, 0x0); -@@ -1851,7 +1853,9 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) - counter++; - } - WriteRT_fld (fld_LP_CONTRAST, dwTempContrast); -- if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Rage Theatre: timeout waiting for line count (%ld)\n", ReadRT_fld (fld_VS_LINE_COUNT)); -+ if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO, -+ "Rage Theatre: timeout waiting for line count (%u)\n", -+ (unsigned)ReadRT_fld (fld_VS_LINE_COUNT)); - - - -@@ -1942,7 +1946,8 @@ void DumpRageTheatreRegs(TheatrePtr t) - for(i=0;i<0x900;i+=4) - { - RT_regr(i, &data); -- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register 0x%04x is equal to 0x%08lx\n", i, data); -+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO, -+ "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); - } - - } -@@ -2147,7 +2152,9 @@ void DumpRageTheatreRegsByName(TheatrePtr t) - - for(i=0; rt_reg_list[i].name!=NULL;i++){ - RT_regr(rt_reg_list[i].addr, &data); -- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register (0x%04lx) %s is equal to 0x%08lx\n", rt_reg_list[i].addr, rt_reg_list[i].name, data); -+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO, -+ "register (0x%04lx) %s is equal to 0x%08x\n", -+ rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); - } - - } -diff --git a/src/theatre200.c b/src/theatre200.c -index ff86395..672f01e 100644 ---- a/src/theatre200.c -+++ b/src/theatre200.c -@@ -1799,10 +1799,12 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) - t->wConnector = wConnector; - - theatre_read(t, VIP_GPIO_CNTL, &data); -- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %lx\n", data); -+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", -+ (unsigned)data); - - theatre_read(t, VIP_GPIO_INOUT, &data); -- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %lx\n", data); -+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", -+ (unsigned)data); - - switch (wConnector) - { -@@ -1851,10 +1853,12 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) - } - - theatre_read(t, VIP_GPIO_CNTL, &data); -- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %lx\n", data); -+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", -+ (unsigned)data); - - theatre_read(t, VIP_GPIO_INOUT, &data); -- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %lx\n", data); -+ xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", -+ (unsigned)data); - - - dsp_configure_i2s_port(t, 0, 0, 0); -@@ -2007,7 +2011,8 @@ void DumpRageTheatreRegs(TheatrePtr t) - for(i=0;i<0x900;i+=4) - { - RT_regr(i, &data); -- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register 0x%04x is equal to 0x%08lx\n", i, data); -+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO, -+ "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); - } - - } -@@ -2212,7 +2217,9 @@ void DumpRageTheatreRegsByName(TheatrePtr t) - - for(i=0; rt_reg_list[i].name!=NULL;i++){ - RT_regr(rt_reg_list[i].addr, &data); -- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "register (0x%04lx) %s is equal to 0x%08lx\n", rt_reg_list[i].addr, rt_reg_list[i].name, data); -+ xf86DrvMsg(t->VIP->scrnIndex, X_INFO, -+ "register (0x%04lx) %s is equal to 0x%08x\n", -+ rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); - } - - } -diff --git a/src/theatre_detect.c b/src/theatre_detect.c -index e754832..8770911 100644 ---- a/src/theatre_detect.c -+++ b/src/theatre_detect.c -@@ -67,7 +67,7 @@ static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) - TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - { - TheatrePtr t; -- CARD32 i; -+ int i; - CARD32 val; - char s[20]; - -@@ -88,7 +88,9 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - { - if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) - { -- if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %ld on VIP bus ids as 0x%08lx\n",i,val); -+ if(val)xf86DrvMsg(b->scrnIndex, X_INFO, -+ "Device %d on VIP bus ids as 0x%08x\n", i, -+ (unsigned)val); - if(t->theatre_num>=0)continue; /* already found one instance */ - switch(val){ - case RT100_ATI_ID: -@@ -101,10 +103,12 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - break; - } - } else { -- xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %ld on VIP bus\n",i); -+ xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i); - } - } -- if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre as device %d on VIP bus with id 0x%08lx\n",t->theatre_num,t->theatre_id); -+ if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO, -+ "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n", -+ t->theatre_num, (unsigned)t->theatre_id); - - if(t->theatre_num < 0) - { -@@ -113,7 +117,8 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - } - - RT_regr(VIP_VIP_REVISION_ID, &val); -- xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8lX\n", val); -+ xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n", -+ (unsigned)val); - - #if 0 - DumpRageTheatreRegsByName(t); diff --git a/sources b/sources index c94a746..041e608 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -f350217d7b56890ba714f0479866210f xf86-video-ati-6.7.191.tar.bz2 +b3207c1df5f6f8cf344efe4842bb2db7 xf86-video-ati-6.7.192.tar.bz2 diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 587df90..e08e942 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -4,8 +4,8 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati -Version: 6.7.191 -Release: 2%{?dist} +Version: 6.7.192 +Release: 1%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -17,8 +17,6 @@ Source2: r128.xinf Source3: radeon.xinf # Radeon patches (0-99) -#Patch0: radeon-6.6.192-dotclock-filter.patch -Patch1: radeon-6.7.191-git-master.patch Patch2: radeon-6.6.3-renderaccel-buglet.patch # Rage 128 patches (100-199) @@ -42,8 +40,6 @@ X.Org X11 ati video driver. %prep %setup -q -n %{tarball}-%{version} -#%patch0 -p1 -b .dotclock-filter -%patch1 -p1 -b .git-master %patch2 -p1 -b .renderaccel %build @@ -85,6 +81,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Mon Aug 27 2007 Adam Jackson 6.7.192-1 +- xf86-video-ati 6.7.192 + * Mon Aug 27 2007 Dave Airlie 6.7.191-2 - radeon-6.7.191-git-master.patch - upgrade to git head f36720377737210c985b196d9a988efdd767f1c7