diff --git a/sources b/sources index 362570b..e69de29 100644 --- a/sources +++ b/sources @@ -1 +0,0 @@ -85839104f7f245879e7db41fc632fee0 verilator-3.712.tgz diff --git a/verilator-3.804.tgz b/verilator-3.804.tgz new file mode 100644 index 0000000..a2fe03b Binary files /dev/null and b/verilator-3.804.tgz differ diff --git a/verilator-driver.patch b/verilator-driver.patch deleted file mode 100644 index f489ed0..0000000 --- a/verilator-driver.patch +++ /dev/null @@ -1,92 +0,0 @@ -diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp -index eab63c2..b5dca8b 100644 ---- a/src/V3Tristate.cpp -+++ b/src/V3Tristate.cpp -@@ -344,14 +344,15 @@ private: - } - } - if (!complete) { -- if (found_one) { -- UINFO(9, " Problem mixing tristate and low-Z on " << lhsp << endl); -- UINFO(9, " Found " << found_one << " __en signals from of " << refs->size() << " possible drivers" << endl); -- // not sure what I should do here other than error that they are mixing low-Z and tristate drivers. -- // The other scenerio, and probably more likely, is that they are using a high-Z construct that -- // is not supported. Improving the high-Z detection logic will reduce the occurance of this failure. -- v3error("Mixing tristate and low-Z drivers. Perhaps you are using a high-Z construct not supported"); -- } else { -+// if (found_one) { -+// UINFO(9, " Problem mixing tristate and low-Z on " << lhsp << endl); -+// UINFO(9, " Found " << found_one << " __en signals from of " << refs->size() << " possible drivers" << endl); -+// // not sure what I should do here other than error that they are mixing low-Z and tristate drivers. -+// // The other scenerio, and probably more likely, is that they are using a high-Z construct that -+// // is not supported. Improving the high-Z detection logic will reduce the occurance of this failure. -+// v3error("Mixing tristate and low-Z drivers. Perhaps you are using a high-Z construct not supported"); -+// } else { -+ if(found_one==0) { - UINFO(9, " No tristates found on " << lhsp <erase(lhsp); -@@ -377,6 +378,19 @@ private: - - // create a new var for this assignment. - AstVar* enp = (AstVar*)refp->user1p(); -+ if(!enp) { -+ enp = new AstVar(lhsp->fileline(), -+ AstVarType::MODULETEMP, -+ lhsp->name()+"__en"+cvtToStr(m_unique), -+ (w>1) ? new AstRange(nodep->fileline(), w-1, 0) : (AstRange *) NULL); -+ V3Number ones(lhsp->fileline(), wfill, 0); -+ ones.setAllBits1(); -+ nodep->addStmtp(enp); -+ nodep->addStmtp(new AstAssignW(lhsp->fileline(), -+ new AstVarRef(lhsp->fileline(), enp, true), -+ new AstConst(lhsp->fileline(), ones))); -+ -+ } - AstVar* newlhsp = new AstVar(lhsp->fileline(), - AstVarType::MODULETEMP, - lhsp->name()+"__lhs"+cvtToStr(m_unique++), -@@ -649,17 +663,38 @@ private: - if (m_state == CONVERT_PINS) { - if (nodep->modVarp()->user1p()) { - // create the input pin -- AstVarRef* refp = nodep->exprp()->castVarRef(); -+ AstPin *pinp; -+ AstVarRef *refp; -+ AstSel *selp = nodep->exprp()->castSel(); -+ if(selp) { -+ refp = selp->fromp()->castVarRef(); -+ } else { -+ refp = nodep->exprp()->castVarRef(); -+ } -+ if(!refp) { -+ v3error("Unsupported inout type"); -+ return; -+ } - AstVar* inp; - if (refp->varp()->user1p()) { // this is a tristate - inp = (AstVar*) refp->varp()->user1p(); - } else { - inp = refp->varp(); - } -- AstPin* pinp = new AstPin(nodep->fileline(), -- nodep->pinNum(), -- nodep->name() + "__in", -- new AstVarRef(nodep->fileline(), inp, false)); -+ AstNode* newnodep; -+ if(selp) { -+ newnodep = new AstSel(selp->fileline(), -+ new AstVarRef(nodep->fileline(), inp, false), -+ selp->lsbp()->cloneTree(false), -+ selp->widthp()->cloneTree(false)); -+ } else { -+ newnodep = new AstVarRef(nodep->fileline(), inp, false); -+ } -+ -+ pinp = new AstPin(nodep->fileline(), -+ nodep->pinNum(), -+ nodep->name() + "__in", -+ newnodep); - m_cellp->addPinsp(pinp); - - // now link it diff --git a/verilator.spec b/verilator.spec index b8aa77e..7ab62af 100644 --- a/verilator.spec +++ b/verilator.spec @@ -1,15 +1,14 @@ Name: verilator -Version: 3.712 +Version: 3.804 Release: 1%{?dist} Summary: A fast simulator for synthesizable Verilog License: GPLv2 -Group: Applications/Engineering +Group: Applications/Engineering URL: http://www.veripool.com/verilator.html Source0: http://www.veripool.org/verilator/ftp/%{name}-%{version}.tgz BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) BuildRequires: perl, flex, bison, perl-SystemPerl-devel Requires: perl-SystemPerl-devel >= 1.320 -Patch0: verilator-driver.patch %description @@ -20,24 +19,17 @@ where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. -Authors: --------- - -Wilson Snyder -Paul Wasson -Duane Galbi - %prep %setup -q -%patch0 -p1 + find . -name .gitignore -exec rm {} \; export VERILATOR_ROOT=%{_datadir} -%{configure} --enable-envdef --prefix=%{_prefix} --mandir=%{_mandir} +%{configure} --enable-envdef --prefix=%{_prefix} --mandir=%{_mandir} %{__sed} -i "s|CPPFLAGSNOWALL +=|CPPFLAGSNOWALL +=%{optflags}|" \ {src,test_c,test_regress,test_sc,test_sp,test_verilated}/Makefile_obj %build -SYSTEMPERL_INCLUDE=%{_includedir}/perl-SystemPerl %{__make} %{?_smp_mflags} +SYSTEMPERL_INCLUDE=%{_includedir}/perl-SystemPerl %{__make} %{?_smp_mflags} %install @@ -53,7 +45,7 @@ SYSTEMPERL_INCLUDE=%{_includedir}/perl-SystemPerl %{__make} %{?_smp_mflags} %{__rm} -rf %{buildroot}%{_bindir}/verilator_includer %clean -%{__rm} -rf %{buildroot} +%{__rm} -rf %{buildroot} %files @@ -73,6 +65,11 @@ SYSTEMPERL_INCLUDE=%{_includedir}/perl-SystemPerl %{__make} %{?_smp_mflags} %changelog +* Sat Sep 25 2010 Chitlesh Goorah - 3.804-1 +- updated to 3.804 + +* Sun Jul 11 2010 Chitlesh Goorah - 3.803-1 +- updated to 3.803 * Fri Jul 24 2009 Lane Brooks - 3.712-1 - Updated to verilator 3.712 @@ -80,7 +77,7 @@ SYSTEMPERL_INCLUDE=%{_includedir}/perl-SystemPerl %{__make} %{?_smp_mflags} * Fri Jun 26 2009 Lane Brooks - 3.711-1 - Updated to verilator 3.711 - Added Artistic file -- Fixed permissions on man file +- Fixed permissions on man file * Tue Jun 9 2009 Lane Brooks - 3.710-1 - Updated to verilator 3.710