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@@ -0,0 +1,192 @@
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+ From 4ca2ef813fe1956b6ec9167cb5a8057d1e9f551e Mon Sep 17 00:00:00 2001
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+ From: Bjorn Pettersson <bjorn.a.pettersson@ericsson.com>
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+ Date: Thu, 28 Nov 2019 23:18:28 +0100
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+ Subject: [PATCH] [InstCombine] Fix big-endian miscompile of (bitcast
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+ (zext/trunc (bitcast)))
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+
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+ Summary:
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+ optimizeVectorResize is rewriting patterns like:
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+ %1 = bitcast vector %src to integer
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+ %2 = trunc/zext %1
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+ %dst = bitcast %2 to vector
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+
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+ Since bitcasting between integer an vector types gives
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+ different integer values depending on endianness, we need
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+ to take endianness into account. As it happens the old
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+ implementation only produced the correct result for little
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+ endian targets.
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+
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+ Fixes: https://bugs.llvm.org/show_bug.cgi?id=44178
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+
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+ Reviewers: spatel, lattner, lebedev.ri
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+
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+ Reviewed By: spatel, lebedev.ri
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+
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+ Subscribers: lebedev.ri, hiraditya, uabelho, llvm-commits
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+
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+ Tags: #llvm
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+
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+ Differential Revision: https://reviews.llvm.org/D70844
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+
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+ (cherry picked from commit a9d6b0e5444741d08ff1df7cf71d1559e7fefc1f)
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+ ---
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+ .../InstCombine/InstCombineCasts.cpp | 79 +++++++++++++------
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+ llvm/test/Transforms/InstCombine/cast.ll | 6 +-
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+ 2 files changed, 60 insertions(+), 25 deletions(-)
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+
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+ diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
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+ index 1201ac196ec0..2924146d1600 100644
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+ --- a/lib/Transforms/InstCombine/InstCombineCasts.cpp
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+ +++ b/lib/Transforms/InstCombine/InstCombineCasts.cpp
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+ @@ -19,6 +19,7 @@
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+ #include "llvm/IR/DIBuilder.h"
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+ #include "llvm/IR/PatternMatch.h"
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+ #include "llvm/Support/KnownBits.h"
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+ +#include <numeric>
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+ using namespace llvm;
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+ using namespace PatternMatch;
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+
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+ @@ -1815,12 +1816,24 @@ Instruction *InstCombiner::visitPtrToInt(PtrToIntInst &CI) {
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+ }
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+
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+ /// This input value (which is known to have vector type) is being zero extended
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+ -/// or truncated to the specified vector type.
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+ +/// or truncated to the specified vector type. Since the zext/trunc is done
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+ +/// using an integer type, we have a (bitcast(cast(bitcast))) pattern,
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+ +/// endianness will impact which end of the vector that is extended or
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+ +/// truncated.
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+ +///
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+ +/// A vector is always stored with index 0 at the lowest address, which
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+ +/// corresponds to the most significant bits for a big endian stored integer and
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+ +/// the least significant bits for little endian. A trunc/zext of an integer
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+ +/// impacts the big end of the integer. Thus, we need to add/remove elements at
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+ +/// the front of the vector for big endian targets, and the back of the vector
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+ +/// for little endian targets.
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+ +///
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+ /// Try to replace it with a shuffle (and vector/vector bitcast) if possible.
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+ ///
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+ /// The source and destination vector types may have different element types.
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+ -static Instruction *optimizeVectorResize(Value *InVal, VectorType *DestTy,
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+ - InstCombiner &IC) {
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+ +static Instruction *optimizeVectorResizeWithIntegerBitCasts(Value *InVal,
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+ + VectorType *DestTy,
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+ + InstCombiner &IC) {
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+ // We can only do this optimization if the output is a multiple of the input
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+ // element size, or the input is a multiple of the output element size.
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+ // Convert the input type to have the same element type as the output.
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+ @@ -1839,31 +1852,53 @@ static Instruction *optimizeVectorResize(Value *InVal, VectorType *DestTy,
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+ InVal = IC.Builder.CreateBitCast(InVal, SrcTy);
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+ }
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+
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+ + bool IsBigEndian = IC.getDataLayout().isBigEndian();
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+ + unsigned SrcElts = SrcTy->getNumElements();
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+ + unsigned DestElts = DestTy->getNumElements();
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+ +
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+ + assert(SrcElts != DestElts && "Element counts should be different.");
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+ +
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+ // Now that the element types match, get the shuffle mask and RHS of the
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+ // shuffle to use, which depends on whether we're increasing or decreasing the
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+ // size of the input.
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+ - SmallVector<uint32_t, 16> ShuffleMask;
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+ + SmallVector<uint32_t, 16> ShuffleMaskStorage;
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+ + ArrayRef<uint32_t> ShuffleMask;
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+ Value *V2;
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+
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+ - if (SrcTy->getNumElements() > DestTy->getNumElements()) {
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+ - // If we're shrinking the number of elements, just shuffle in the low
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+ - // elements from the input and use undef as the second shuffle input.
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+ - V2 = UndefValue::get(SrcTy);
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+ - for (unsigned i = 0, e = DestTy->getNumElements(); i != e; ++i)
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+ - ShuffleMask.push_back(i);
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+ + // Produce an identify shuffle mask for the src vector.
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+ + ShuffleMaskStorage.resize(SrcElts);
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+ + std::iota(ShuffleMaskStorage.begin(), ShuffleMaskStorage.end(), 0);
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+
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+ + if (SrcElts > DestElts) {
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+ + // If we're shrinking the number of elements (rewriting an integer
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+ + // truncate), just shuffle in the elements corresponding to the least
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+ + // significant bits from the input and use undef as the second shuffle
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+ + // input.
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+ + V2 = UndefValue::get(SrcTy);
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+ + // Make sure the shuffle mask selects the "least significant bits" by
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+ + // keeping elements from back of the src vector for big endian, and from the
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+ + // front for little endian.
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+ + ShuffleMask = ShuffleMaskStorage;
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+ + if (IsBigEndian)
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+ + ShuffleMask = ShuffleMask.take_back(DestElts);
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+ + else
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+ + ShuffleMask = ShuffleMask.take_front(DestElts);
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+ } else {
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+ - // If we're increasing the number of elements, shuffle in all of the
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+ - // elements from InVal and fill the rest of the result elements with zeros
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+ - // from a constant zero.
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+ + // If we're increasing the number of elements (rewriting an integer zext),
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+ + // shuffle in all of the elements from InVal. Fill the rest of the result
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+ + // elements with zeros from a constant zero.
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+ V2 = Constant::getNullValue(SrcTy);
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+ - unsigned SrcElts = SrcTy->getNumElements();
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+ - for (unsigned i = 0, e = SrcElts; i != e; ++i)
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+ - ShuffleMask.push_back(i);
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+ -
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+ - // The excess elements reference the first element of the zero input.
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+ - for (unsigned i = 0, e = DestTy->getNumElements()-SrcElts; i != e; ++i)
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+ - ShuffleMask.push_back(SrcElts);
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+ + // Use first elt from V2 when indicating zero in the shuffle mask.
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+ + uint32_t NullElt = SrcElts;
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+ + // Extend with null values in the "most significant bits" by adding elements
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+ + // in front of the src vector for big endian, and at the back for little
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+ + // endian.
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+ + unsigned DeltaElts = DestElts - SrcElts;
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+ + if (IsBigEndian)
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+ + ShuffleMaskStorage.insert(ShuffleMaskStorage.begin(), DeltaElts, NullElt);
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+ + else
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+ + ShuffleMaskStorage.append(DeltaElts, NullElt);
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+ + ShuffleMask = ShuffleMaskStorage;
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+ }
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+
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+ return new ShuffleVectorInst(InVal, V2,
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+ @@ -2330,8 +2365,8 @@ Instruction *InstCombiner::visitBitCast(BitCastInst &CI) {
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+ CastInst *SrcCast = cast<CastInst>(Src);
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+ if (BitCastInst *BCIn = dyn_cast<BitCastInst>(SrcCast->getOperand(0)))
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+ if (isa<VectorType>(BCIn->getOperand(0)->getType()))
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+ - if (Instruction *I = optimizeVectorResize(BCIn->getOperand(0),
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+ - cast<VectorType>(DestTy), *this))
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+ + if (Instruction *I = optimizeVectorResizeWithIntegerBitCasts(
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+ + BCIn->getOperand(0), cast<VectorType>(DestTy), *this))
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+ return I;
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+ }
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+
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+ diff --git a/llvm/test/Transforms/InstCombine/cast.ll b/llvm/test/Transforms/InstCombine/cast.ll
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+ index b6d1eda0601d..3ce8de033422 100644
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+ --- a/test/Transforms/InstCombine/cast.ll
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+ +++ b/test/Transforms/InstCombine/cast.ll
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+ @@ -824,7 +824,7 @@ define i64 @test59(i8 %A, i8 %B) {
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+
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+ define <3 x i32> @test60(<4 x i32> %call4) {
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+ ; CHECK-LABEL: @test60(
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+ -; CHECK-NEXT: [[P10:%.*]] = shufflevector <4 x i32> [[CALL4:%.*]], <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
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+ +; CHECK-NEXT: [[P10:%.*]] = shufflevector <4 x i32> [[CALL4:%.*]], <4 x i32> undef, <3 x i32> <i32 1, i32 2, i32 3>
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+ ; CHECK-NEXT: ret <3 x i32> [[P10]]
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+ ;
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+ %p11 = bitcast <4 x i32> %call4 to i128
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+ @@ -836,7 +836,7 @@ define <3 x i32> @test60(<4 x i32> %call4) {
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+
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+ define <4 x i32> @test61(<3 x i32> %call4) {
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+ ; CHECK-LABEL: @test61(
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+ -; CHECK-NEXT: [[P10:%.*]] = shufflevector <3 x i32> [[CALL4:%.*]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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+ +; CHECK-NEXT: [[P10:%.*]] = shufflevector <3 x i32> [[CALL4:%.*]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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+ ; CHECK-NEXT: ret <4 x i32> [[P10]]
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+ ;
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+ %p11 = bitcast <3 x i32> %call4 to i96
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+ @@ -848,7 +848,7 @@ define <4 x i32> @test61(<3 x i32> %call4) {
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+ define <4 x i32> @test62(<3 x float> %call4) {
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+ ; CHECK-LABEL: @test62(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <3 x float> [[CALL4:%.*]] to <3 x i32>
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+ -; CHECK-NEXT: [[P10:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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+ +; CHECK-NEXT: [[P10:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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+ ; CHECK-NEXT: ret <4 x i32> [[P10]]
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+ ;
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+ %p11 = bitcast <3 x float> %call4 to i96
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+ --
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+ 2.26.2
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+
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