diff -up binutils-2012.09/bfd/doc/bfd.texinfo.fixtex binutils-2012.09/bfd/doc/bfd.texinfo --- binutils-2012.09/bfd/doc/bfd.texinfo.fixtex 2012-10-30 18:24:00.000000000 +0100 +++ binutils-2012.09/bfd/doc/bfd.texinfo 2013-02-20 14:37:36.405844568 +0100 @@ -1,7 +1,7 @@ \input texinfo.tex @setfilename bfd.info @c Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1997, 2000, -@c 2001, 2002, 2003, 2006, 2007, 2008, 2009 +@c 2001, 2002, 2003, 2006, 2007, 2008, 2009, 2013 @c Free Software Foundation, Inc. @c @synindex fn cp @@ -16,7 +16,8 @@ @copying This file documents the BFD library. -Copyright @copyright{} 1991, 2000, 2001, 2003, 2006, 2007, 2008 Free Software Foundation, Inc. +Copyright @copyright{} 1991, 2000, 2001, 2003, 2006, 2007, 2008, 2013 +Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or @@ -64,7 +65,8 @@ included in the section entitled ``GNU F @end tex @vskip 0pt plus 1filll -Copyright @copyright{} 1991, 2001, 2003, 2006, 2008 Free Software Foundation, Inc. +Copyright @copyright{} 1991, 2001, 2003, 2006, 2008, 2013 +Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 @@ -322,7 +324,7 @@ All of BFD lives in one directory. @printindex cp @tex -% I think something like @colophon should be in texinfo. In the +% I think something like @@colophon should be in texinfo. In the % meantime: \long\def\colophon{\hbox to0pt{}\vfill \centerline{The body of this manual is set in} @@ -333,7 +335,7 @@ All of BFD lives in one directory. \centerline{{\sl\fontname\tensl\/}} \centerline{are used for emphasis.}\vfill} \page\colophon -% Blame: doc@cygnus.com, 28mar91. +% Blame: doc@@cygnus.com, 28mar91. @end tex @bye diff -up binutils-2012.09/binutils/doc/binutils.texi.fixtex binutils-2012.09/binutils/doc/binutils.texi --- binutils-2012.09/binutils/doc/binutils.texi.fixtex 2012-10-30 18:23:59.000000000 +0100 +++ binutils-2012.09/binutils/doc/binutils.texi 2013-02-20 14:37:36.406844576 +0100 @@ -4375,7 +4375,7 @@ equivalent. At least one of the @option{ @table @env -@itemx --input-mach=@var{machine} +@item --input-mach=@var{machine} Set the matching input ELF machine type to @var{machine}. If @option{--input-mach} isn't specified, it will match any ELF machine types. @@ -4383,21 +4383,21 @@ machine types. The supported ELF machine types are, @var{L1OM}, @var{K1OM} and @var{x86-64}. -@itemx --output-mach=@var{machine} +@item --output-mach=@var{machine} Change the ELF machine type in the ELF header to @var{machine}. The supported ELF machine types are the same as @option{--input-mach}. -@itemx --input-type=@var{type} +@item --input-type=@var{type} Set the matching input ELF file type to @var{type}. If @option{--input-type} isn't specified, it will match any ELF file types. The supported ELF file types are, @var{rel}, @var{exec} and @var{dyn}. -@itemx --output-type=@var{type} +@item --output-type=@var{type} Change the ELF file type in the ELF header to @var{type}. The supported ELF types are the same as @option{--input-type}. -@itemx --input-osabi=@var{osabi} +@item --input-osabi=@var{osabi} Set the matching input ELF file OSABI to @var{osabi}. If @option{--input-osabi} isn't specified, it will match any ELF OSABIs. @@ -4407,7 +4407,7 @@ The supported ELF OSABIs are, @var{none} @var{FreeBSD}, @var{TRU64}, @var{Modesto}, @var{OpenBSD}, @var{OpenVMS}, @var{NSK}, @var{AROS} and @var{FenixOS}. -@itemx --output-osabi=@var{osabi} +@item --output-osabi=@var{osabi} Change the ELF OSABI in the ELF header to @var{osabi}. The supported ELF OSABI are the same as @option{--input-osabi}. diff -up binutils-2012.09/gas/doc/c-arc.texi.fixtex binutils-2012.09/gas/doc/c-arc.texi --- binutils-2012.09/gas/doc/c-arc.texi.fixtex 2012-10-30 18:23:49.000000000 +0100 +++ binutils-2012.09/gas/doc/c-arc.texi 2013-02-20 14:37:36.406844576 +0100 @@ -220,7 +220,7 @@ The extension instructions are not macro encodings for use of these instructions according to the specification by the user. The parameters are: -@table @bullet +@table @code @item @var{name} Name of the extension instruction diff -up binutils-2012.09/gas/doc/c-arm.texi.fixtex binutils-2012.09/gas/doc/c-arm.texi --- binutils-2012.09/gas/doc/c-arm.texi.fixtex 2012-10-30 18:23:49.000000000 +0100 +++ binutils-2012.09/gas/doc/c-arm.texi 2013-02-20 15:55:48.682995079 +0100 @@ -20,6 +20,7 @@ * ARM Options:: Options * ARM Syntax:: Syntax * ARM Floating Point:: Floating Point +* ARM Relocations:: ARM relocation generation * ARM Directives:: ARM Machine Directives * ARM Opcodes:: Opcodes * ARM Mapping Symbols:: Mapping Symbols @@ -38,7 +39,7 @@ This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are -recognized: +recognized: @code{arm1}, @code{arm2}, @code{arm250}, @@ -131,25 +132,25 @@ recognized: @code{i80200} (Intel XScale processor) @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and -@code{xscale}. +@code{xscale}. The special name @code{all} may be used to allow the assembler to accept instructions valid for any ARM processor. -In addition to the basic instruction set, the assembler can be told to -accept various extension mnemonics that extend the processor using the +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, @code{-mcpu=arm920+maverick} -is equivalent to specifying @code{-mcpu=ep9312}. +is equivalent to specifying @code{-mcpu=ep9312}. -Multiple extensions may be specified, separated by a @code{+}. The +Multiple extensions may be specified, separated by a @code{+}. The extensions should be specified in ascending alphabetical order. -Some extensions may be restricted to particular architectures; this is +Some extensions may be restricted to particular architectures; this is documented in the list of extensions below. -Extension mnemonics may also be removed from those the assembler accepts. -This is done be prepending @code{no} to the option that adds the extension. -Extensions that are removed should be listed after all extensions which have -been added, again in ascending alphabetical order. For example, +Extension mnemonics may also be removed from those the assembler accepts. +This is done be prepending @code{no} to the option that adds the extension. +Extensions that are removed should be listed after all extensions which have +been added, again in ascending alphabetical order. For example, @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}. @@ -164,7 +165,7 @@ The following extensions are currently s @code{os} (Operating System for v6M architecture), @code{sec} (Security Extensions for v6K and v7-A architectures), @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), -@code{virt} (Virtualization Extensions for v7-A architecture, implies +@code{virt} (Virtualization Extensions for v7-A architecture, implies @code{idiv}), and @code{xscale}. @@ -173,8 +174,8 @@ and @item -march=@var{architecture}[+@var{extension}@dots{}] This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which -will not execute on the target architecture. The following architecture -names are recognized: +will not execute on the target architecture. The following architecture +names are recognized: @code{armv1}, @code{armv2}, @code{armv2a}, @@ -218,7 +219,7 @@ extension options as the @code{-mcpu} op This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble -an instruction which will not execute on the target floating point unit. +an instruction which will not execute on the target floating point unit. The following format options are recognized: @code{softfpa}, @code{fpe}, @@ -260,14 +261,14 @@ In addition to determining which instruc also affects the way in which the @code{.double} assembler directive behaves when assembling little-endian code. -The default is dependent on the processor selected. For Architecture 5 or -later, the default is to assembler for VFP instructions; for earlier +The default is dependent on the processor selected. For Architecture 5 or +later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions. @cindex @code{-mthumb} command line option, ARM @item -mthumb This option specifies that the assembler should start assembling Thumb -instructions; that is, it should behave as though the file starts with a +instructions; that is, it should behave as though the file starts with a @code{.code 16} directive. @cindex @code{-mthumb-interwork} command line option, ARM @@ -303,7 +304,7 @@ Calling Standard. @cindex @code{-matpcs} command line option, ARM @item -matpcs -This option specifies that the output generated by the assembler should +This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can @@ -376,7 +377,6 @@ features. The default is to warn. * ARM-Instruction-Set:: Instruction Set * ARM-Chars:: Special Characters * ARM-Regs:: Register Names -* ARM-Relocations:: Relocations * ARM-Neon-Alignment:: NEON Alignment Specifiers @end menu @@ -388,7 +388,7 @@ ARM and THUMB instructions had their own @code{unified} syntax, which can be selected via the @code{.syntax} directive, and has the following main features: -@table @bullet +@table @code @item Immediate operands do not require a @code{#} prefix. @@ -471,8 +471,8 @@ so @samp{: @var{align}} is used instead. @cindex ARM floating point (@sc{ieee}) The ARM family uses @sc{ieee} floating-point numbers. -@node ARM-Relocations -@subsection ARM relocation generation +@node ARM Relocations +@section ARM relocation generation @cindex data relocations, ARM @cindex ARM data relocations @@ -546,13 +546,13 @@ boundary). This is for compatibility wi Select the target architecture. Valid values for @var{name} are the same as for the @option{-march} commandline option. -Specifying @code{.arch} clears any previously selected architecture +Specifying @code{.arch} clears any previously selected architecture extensions. @cindex @code{.arch_extension} directive, ARM @item .arch_extension @var{name} -Add or remove an architecture extension to the target architecture. Valid -values for @var{name} are the same as those accepted as architectural +Add or remove an architecture extension to the target architecture. Valid +values for @var{name} are the same as those accepted as architectural extensions by the @option{-mcpu} commandline option. @code{.arch_extension} may be used multiple times to add or remove extensions @@ -592,7 +592,7 @@ selects Thumb, with the value 32 selecti Select the target processor. Valid values for @var{name} are the same as for the @option{-mcpu} commandline option. -Specifying @code{.cpu} clears any previously selected architecture +Specifying @code{.cpu} clears any previously selected architecture extensions. @c DDDDDDDDDDDDDDDDDDDDDDDDDD @@ -658,7 +658,7 @@ The @var{value} is either a @code{number @code{number, "string"} depending on the tag. Note - the following legacy values are also accepted by @var{tag}: -@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, +@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, @cindex @code{.even} directive, ARM @@ -950,7 +950,7 @@ used in favour of @code{.save} for savin @cindex opcodes for ARM @code{@value{AS}} implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load -instructions. +instructions. @table @code @@ -964,7 +964,7 @@ This pseudo op will always evaluate to a nothing. Currently it will evaluate to MOV r0, r0. @cindex @code{LDR reg,=